JPH07283417A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To obtain a highly reliable, high-speed pulse-operable FET capable of preventing a gate lag that occurs during a pulse operation of turning an FET on and off with a gate voltage, having a small gate leak current. [Constitution] In a dual-gate FET having first and second gates, the recess width-gate length of each gate is expressed by
It has a dual gate FET structure in which the second gate 3 which is turned on and off by the pulse is smaller than the side of the other first gate 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a MESF requiring high speed operation.
ET (Metal Semiconductor Field Effect Transistor
) Is used for the structure of the dual gate FET.

[0002]

2. Description of the Related Art According to Japanese Patent Publication No. 5-62462,
In a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as GaAs, there is a large difference in characteristics depending on the structure of the FET, and Takeuchi et al. Taking the MES-FET of the structure and actually using the type C or the configuration intermediate between the types B and C, the gate current Ig (R
F), saturation of output, and optimization from the viewpoint of efficiency.

That is, FIGS. 11 (a), 11 (b) and 11 (c) show a general recess type GaAs-type semiconductor device shown in FIG.
FIG. 12 is a sectional side view of a main part of the MESFET. In FIG. 11, 11 is a semi-insulating GaAs substrate, 12 is a GaAs active layer, 18 is a recess, 14 is a source electrode, 15 is a drain electrode, 16 is a gate electrode, and 17 is a surface. Protective film, Lr is the recess width, where ME of FIGS. 11 (a), (b) and (c) is used.
The gate width of each of the SFETs is Lr = 1 [μm] Lr = 2 [μm] Lr = 3 [μm], and they are type A, type B, and type C, respectively.
It is what

The input / output characteristics of these three types of MESFETs are shown in FIG. 12, and as can be seen from FIG.
In Type A (white circle), the linear gain is 6
Although it is about dB, the input power Pin does not saturate up to about 20 dBm, the linearity of the input / output characteristic is extremely good, and the power added efficiency ηadd reaches 30%. However, the gate current Ig during high frequency operation
(RF) has an extremely large value in the negative direction, which is not practical.

In the type B (black circle), the linear gain is about 8 [dB], and the output saturation is Pin.
It starts from about 14 dBm, and ηadd barely exceeds 15%. Further, Ig once flows in the minus direction by about several hundred μA and then flows in the plus direction.

In Type C (square mark), its linear gain is as high as 10 dB, but saturation has already started at Pin = 10 dBm, and ηadd often does not reach 15%. Ig (RF) hardly flows, flows a few μA in the negative direction, and flows in the positive direction when Pin is increased to about 20 dBm.

Ideally, for this type of FET, it is desirable that Ig (RF) does not flow at all, output saturation does not easily occur, and the efficiency is 30% or more, but in reality, reliability is considered. Thus, the above-mentioned optimization is achieved by adopting a type C configuration in which Ig (RF) hardly flows or by adopting an intermediate configuration between type C and type B.

As described above, in the above publication, when the gate length is the same and the recess width is wide, the depletion layer extends from the surface of the GaAs layer to the inside due to the surface level of the FET, which adversely affects the high frequency operation of the FET. There is. It is known that this also adversely affects the high frequency operation of the FET even in the pulse operation in which the FET is actually turned on and off by the gate voltage. For example, R. Yeats of Hewlett-Packard Co., et al. When the recess width is widened, channel confinement occurs due to the surface level of the FET, and thus gate lag (gate transients) is generated. It is reported that it can be greatly reduced by doing.

Two types of conventional dual gate FETs
9 and 10 show a semiconductor device constituting the above. In both figures, 6 is a semiconductor substrate made of GaAs, 5 is a p-type GaAs operating layer formed on the semiconductor substrate 6, 1 and 4 are source electrodes and drain electrodes formed on the operating layer 5, and 8 , 9 are first and second recesses formed on the operation layer 5, 2 and 3 are first and second gate electrodes formed on the first and second recesses 8 and 9, and 7 is a surface protective film that covers these.

In the semiconductor device of FIG. 9, first and second
The recess widths of both the recesses 8 and 9 are wider than those of the first and second gate electrodes 3 and 2. In the semiconductor device of FIG. 10, the recess widths of the first and second recesses 8 and 9 are The width is as narrow as the width of the second gate electrodes 2 and 3, and the shape of the gate groove is such that the gate electrode matches the bottom of the gate groove without any gap.

In the conventional dual gate FET semiconductor device shown in FIGS. 9 and 10, the first gate 2 and the second gate 3 are formed at the same time.
The structure of the gate 2 and the recess 8 of FIG. 2 and the structure of the second gate 3 and the recess 9 are exactly the same. In such a structure, as described above, the gate lag caused by the surface level of the FET when the recess width is widened. It has been difficult to prevent both of the above and to reduce the gate current Ig (RF).

Further, in JP-A-60-101972, the first gate 5 formed in the first recess having the recess depth d1 and the recess depth d2 (= d1) in FIG.
Discloses a dual-gate FET having a second gate 6 formed in the second recess of FIG. 4, and in FIG. 4, the first gate formed in the first recess having a recess depth d1 = 0.3 .mu.m. 5 and a dual gate FET having a second gate 6 formed in a second recess having a recess depth d2 = 0.2 .mu.m, both of which have the same gate length from the first gate 5 to the second gate. The gate 6 has a long gate length. However, in both figures of this publication, as the width of the recess, the width corresponding to the gate length capable of accommodating each gate, that is, the type A is shown.

Further, in JP-A-61-212069, FIG. 4 shows that the first gate length lg1 and the second gate length lg2 have the same size (lg1 = lg2) in FIG. Describes that the second gate length lg2 is made larger than the first gate length lg1 (lg2> lg1). However, as for these FETs, the recess width is shown to be a width corresponding to the gate length capable of accommodating each gate, that is, the type A described above.

[0014]

[Problems to be Solved by the Invention] As described above,
In a MES-FET that requires high-speed operation, if the gate length is the same and the recess width is wide, a depletion layer extends from the surface of the GaAs layer to the inside due to the surface level of the FET.
It had a bad influence on the high frequency operation of. In particular,
In fact, even in the pulse operation of turning the FET on and off with the gate voltage, if the recess width is widened in this way, the FET
The gate lag (gate transients) is caused by the channel confinement caused by the surface level of
In particular, it adversely affects the high frequency operation of the FET that performs the pulse operation.

The present invention has been made to solve the above problems, and in a dual gate FET having a gate that performs a pulse operation to turn on / off by a gate voltage, it is possible to prevent a gate lag, and
It is an object of the present invention to provide a semiconductor device capable of reducing gate leakage and a method for manufacturing the semiconductor device.

[0016]

A semiconductor device according to the present invention includes an operating layer formed on a semiconductor substrate, a source electrode and a drain electrode formed at respective required positions on the operating layer, and the above-described operation. First and second recesses respectively having first and second recess widths respectively formed at two required positions between the source electrode and the drain electrode on the layer, and the first and second recesses. A first gate electrode and a second gate electrode respectively formed on the gate electrode, the second gate electrode being turned on and off by a pulse, and the difference between the recess width and the gate length of each gate electrode. Indicates that the second gate is smaller than the first gate.

Further, according to the present invention, in the above semiconductor device, the first and second recesses are both etched in the operation layer through an etching mask opening having an opening width approximately the same as the recess width to be formed. It is supposed to be formed by.

According to the present invention, in the semiconductor device, the first recess is an etching mask opening having an opening width which is approximately the same as the recess width to be formed, and the second recess is the recess width to be formed. The operating layer is etched through an etching mask opening having a smaller opening width, and the second recess is formed by deeper etching to form a recess width larger than the etching mask opening by side etching. It was done.

Further, according to the present invention, in the above semiconductor device, the gate length of the second gate electrode is substantially equal to the gate length of the first gate electrode. Further, according to the present invention, in the above semiconductor device, the gate length of the second gate electrode is longer than the gate length of the first gate electrode.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an operation layer on a semiconductor substrate, a step of forming a source electrode and a drain electrode at respective required positions on the operation layer, and the operation layer. The two required positions between the source electrode and the drain electrode are etched through an etching mask opening for the first and second recesses, the opening having an opening width approximately the same as the recess width to be formed. The step of forming the first and second recesses having a width, and the difference between the recess width and the gate length of each gate electrode on the first and second recesses is And a step of forming first and second gate electrodes each having a required gate length smaller than that of the first gate.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an operation layer on a semiconductor substrate, a step of forming a source electrode and a drain electrode at respective required positions on the operation layer, and the operation layer. In the two required positions between the source electrode and the drain electrode, the first recess is an etching mask opening having the same opening width as the recess width to be formed, and the second recess is the recess to be formed. Etching is performed from an etching mask opening having an opening width smaller than the width, the second recess is etched deeper, and the side etching is performed so that the recess width is larger than the etching mask opening. A step of forming the first and second recesses, and a recess width and a gate length of each gate electrode on each of the first and second recesses. Difference, in which the direction of the second gate is smaller than the first gate, the first, characterized in that it comprises a step of forming a second gate electrode having the required respective gate lengths.

[0022]

In the semiconductor device according to the present invention, the operation layer formed on the semiconductor substrate, the source electrode and the drain electrode formed at respective required positions on the operation layer, and the operation layer formed on the operation layer The first and second electrodes are respectively formed at two required positions between the source electrode and the drain electrode.
The first and second recesses having a recess width of
A first gate electrode and a second gate electrode respectively formed on the second recess, and the second gate electrode is turned on and off by a pulse, and the recess width and the gate length of each gate electrode are provided. Since the second gate has an FET structure smaller than that of the first gate, the second gate has a smaller leak current at the first gate and is turned on / off by pulse operation. With less gate lag,
Reliable dual gate F capable of high-speed pulse operation
You can get ET.

Further, according to the present invention, in the above semiconductor device, the first and second recesses are both etched in the operation layer through an etching mask opening having an opening width approximately equal to a recess width to be formed. Since the first and second recesses have the same depth, the difference between the recess width of each gate electrode and the gate length is
Since the second gate is smaller than the first gate, the leakage current in the first gate is small, and the gate lag in the second gate that is turned on / off by pulse operation is small and the reliability is high. A dual gate FET capable of high-speed pulse operation can be configured.

According to the present invention, in the above semiconductor device, the first recess is an etching mask opening having an opening width approximately equal to the recess width to be formed, and the second recess is the recess width to be formed. The operating layer is etched through an etching mask opening having a smaller opening width, and the second recess is formed by deeper etching to form a recess width larger than the resist opening by side etching. Therefore, the depth of the first and second recesses is deeper in the first recess,
The difference between the recess width of each gate electrode and the gate length is the second
Since the first gate is smaller than the first gate, the leakage current in the first gate is small, and the gate lag in the second gate that is turned on / off by pulse operation is small, the reliability is high, and the speed is high. A dual gate FET capable of pulse operation can be constructed.

According to the present invention, in the above semiconductor device, the gate length of the second gate electrode is substantially equal to the gate length of the first gate electrode, and the recess width and the gate length of each gate electrode. And the second gate is smaller than the first gate, the leak current in the first gate is small and the gate lag in the second gate that is turned on / off by pulse operation is small. ,
Reliable dual gate F capable of high-speed pulse operation
ET can be configured.

According to the present invention, in the semiconductor device, the gate length of the second gate electrode is the first length.
Is longer than the gate length of the first gate electrode, and the difference between the recess width and the gate length of each gate electrode is smaller in the second gate than in the first gate. Low current and pulse operation
A highly reliable dual-gate FET capable of high-speed pulse operation with less gate lag at the second gate to be turned off can be constructed.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming an operation layer on a semiconductor substrate, a step of forming a source electrode and a drain electrode at respective required positions on the operation layer, and the operation described above. The two required positions of the layer between the source electrode and the drain electrode are etched through an etching mask opening for the first and second recesses having an opening width similar to the recess width to be formed, and each required position is etched. Forming first and second recesses having a recess width,
A first gate having a required gate length on each of the first and second recesses, wherein a difference between a recess width and a gate length of each gate electrode is smaller in the second gate than in the first gate. , The step of forming the second gate electrode is included, the difference between the recess width and the gate length of each gate electrode is
Is smaller than the first gate, the leak current in the first gate is small, the gate lag is small in the second gate that is turned on / off by pulse operation, and the reliability is high. A dual gate FET capable of high speed pulse operation can be manufactured.

In the method of manufacturing a semiconductor device according to the present invention, the step of forming an operating layer on a semiconductor substrate, the step of forming a source electrode and a drain electrode at each required position on the operating layer, and the operation described above. The two required positions of the layer between the source electrode and the drain electrode, the first recess,
The second recess is etched by an etching mask opening having an opening width smaller than the recess width to be formed, and the second recess is etched by an etching mask opening having an opening width smaller than the recess width to be formed. Etching deeply and etching by its side etching so that the recess width is larger than the above etching mask opening,
The step of forming the first and second recesses each having a required recess width, and the difference between the recess width and the gate length of each gate electrode on the first and second recesses is the second gate. And the step of forming first and second gate electrodes each having a required gate length smaller than that of the first gate. Therefore, the difference between the recess width of each gate electrode and the gate length is However, since the second gate is smaller than the first gate, there is less leakage current in the first gate, and there is less gate lag in the second gate that turns on and off by pulse operation, and Dual-gate FET with deep recess depth, high reliability, and high-speed pulse operation
Can be manufactured.

[0029]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a dual gate FET according to the first embodiment of the present invention. In FIG. 1, 6 is GaA.
a semiconductor substrate made of s, 5 is a p-type GaAs operating layer formed on the semiconductor substrate 6, 1 and 4 are source and drain electrodes formed on the operating layer 5, and 8 is on the operating layer 5. Formed on the first recess, 9 is also the second recess, 2 is the first gate electrode formed on the first recess 8, and 3 is the second gate formed on the second recess 9. The electrodes 7 are formed so as to cover the source electrode 1, the drain electrode 4, the first recess 8, the first gate electrode 8, the second recess 9 and the second gate 3, SiO2, S.
It is a surface protective film made of iN or the like.

FIG. 5 is a process chart showing a method of manufacturing the dual gate FET of the first embodiment shown in FIG. 1. Hereinafter, the dual gate FET of the first embodiment will be described with reference to FIG.
The manufacturing method of will be described.

First, as shown in FIG. 5A, an impurity concentration of 1 to 3 × 10 ¹⁷ cm is formed on a semiconductor substrate 1 made of GaAs.
^-3 , n-type GaAs operating layer 5 having a thickness of 0.1 to 0.5 μm
And a source electrode 1 and a drain electrode 4 made of, for example, AuGe and having a thickness of several thousand angstroms are formed at required positions on the left and right in the figure by vapor deposition and lift-off.

Next, as also shown in FIG. 5A, a photoresist 10 is applied to the entire surface of the substrate 6 and then,
For the second recess forming opening in which the second gate electrode is to be formed in the photoresist 10 by photolithography, a resist opening 21 having a width equal to the gate length of 0.5 μm is formed. As for the first recess forming opening for forming the first gate electrode, a resist opening 22a having a width larger than the gate length of the gate electrode to be formed, for example, 0.9 μm is formed.

Thereafter, using the photoresist 10 as an etching mask, a required voltage is applied between the electrodes 4 and 1 while a current is passed through the operating layer 5 and the operating layer 5 is observed while checking the current value. When the second recess 9 having a depth of 3000 angstroms is formed as shown in FIG. 5 (b) by etching or performing etching for a predetermined time (for example, wet etching using a tartaric acid / sulfuric acid-based etchant), At this time, from the resist opening 21a of 0.5 μm, which is the same as the above gate length, to 0.
By performing the side etching for 3 μm or less, the second recess 9 has a recess width of about 1.1 μm or less. At the same time, the first recess 8 is also etched to a depth of 3000 angstroms to form a resist opening 22 having a width of about 0.9 μm.
From a, a first recess having a recess width of about 1.5 μm or less which is widened by 0.3 μm or less on one side by side etching.
Recess 8 is formed. After that, the photoresist 10 is removed.

Then, as shown in FIG.
l, WSi and other gate metal vapor deposition, lift-off,
Alternatively, by performing sputter milling, the second
The first gate electrode 3 is formed on the recess 9 and the second gate electrode 2 is formed on the first recess 8 with a gate length of 0.5 μm and a thickness of several thousand angstroms. After that, the surface protection film 7 made of SiO2 or the like is formed on the entire surface to complete the formation of the dual gate FET of the first embodiment shown in FIG.

In the FET of the first embodiment, the recess width of the first gate 2 and its recess 8 is larger than the gate length, and the recess width Wr-gate length Lg becomes large. 62462), type C, or an intermediate structure between types B and C, is optimized in terms of reduction of gate leakage current, output saturation, and efficiency, while the second gate 3 and its The recess 9 has a type A configuration in which the recess width is substantially equal to the gate length and the recess width Wr-the gate length Lg is small, and a pulse operation for turning on / off the second gate 3 is performed. The gate lag at that time is made smaller.
As described above, in the first gate electrode 2, since the recess width-gate length is large, the leak current of the gate can be reduced, and in the second gate electrode 3, the recess width-gate length is small. As a result, the channel confinement due to the surface level, and hence the gate lag due to this, can be made small, and as a result, the gate current is small and the gate lag in pulse operation can be prevented. The gate FET can be obtained.

As described above, Japanese Patent Laid-Open No. 60-10
In FIG. 4 of Japanese Patent Laid-Open No. 1972, in a dual gate FET, a first gate 5 formed in a first recess having a recess depth d1 = 0.3 μm and a recess depth d2 = 0.2 μm.
a second gate 6 formed in a second recess of m,
Regarding the gate length, a gate length of the second gate 6 is longer than that of the first gate 5 is disclosed, and Japanese Patent Application Laid-Open No. 61-212069 discloses that in FIG.
The first gate length lg1 and the second gate length lg2 have the same size (lg1 = lg2), and in FIG. 4, the second gate length lg2 is larger than the first gate length lg1. (Lg2> lg1) is described, and regarding the recess width of these FETs, the recess width of the FET is almost equal to the gate length and the type A is shown.

On the other hand, according to the present invention, the relation between the width of the recess and the gate length is expressed as follows: recess width Wr-gate length Lg
It is characterized in that the second gate 3 which is turned on and off by a pulse is configured to be smaller than the other first gate 2, whereby the first gate 2 side has a larger recess width-gate length. The type C or the type B and C intermediate structure referred to in the above document is optimized in terms of reduction of gate leak current, saturation of output, and efficiency, while the second gate 3 performs pulse operation. The side is made to have a type A configuration in which the above recess width-gate length is small, thereby optimizing the gate lag in pulse operation. Therefore, in this way, the recess width-gate length of each gate is
The gate 3 can be made smaller than the other first gate gate length, so that the gate current can be reduced and the gate lag during pulse operation can be greatly reduced.
It is possible to obtain a highly reliable dual gate FET capable of high-speed pulse operation. In this respect, according to the present invention, the dual gate FE described in the above two publications has the same recess width-gate length between the first gate and the second gate.
T is a completely different feature.

In the first embodiment, the operating layer is p-type G.
The case of the dual gate FET semiconductor device of the MESFET which is the aAs layer has been described, but in the present Example 1, the AlGaAs in the GaAs layer is formed on the semi-insulating GaAs substrate.
HEMT (Hi
gh Electron Mobility Transistor) The present invention can also be applied to a semiconductor device and has the same effect as that of the first embodiment.

In the first embodiment described above, the case where the etching is wet etching has been described. However, this may be performed using dry etching using a chlorine-based gas, for example, and dry etching is used for resist opening. Considering that the side etching can be reduced with respect to the width, for example, a method in which the recess 8 of the first gate is wet-etched and the recess 9 of the second gate is dry-etched can be considered.

Example 2. In the first embodiment shown in FIG. 1, the gate lengths of the first gate 2 and the second gate 3 are almost the same, and the recess width thereof is the second recess 8 is the second.
By making the recess width larger than the recess 9 width, the recess width-gate length becomes smaller than the first recess in the pulse-operated second recess, and this recess width is smaller than that in the first gate. Structures larger than two recess widths are
It was realized by making the resist opening for forming the gate larger than the resist opening for forming the second recess and etching.

The second embodiment of the present invention realizes the above structure by deeply etching the first gate and then increasing the recess width by side etching at that time.

That is, FIG. 6 is a process diagram showing a method of manufacturing the dual gate FET according to the second embodiment shown in FIG. 2. Hereinafter, the manufacturing of the dual gate FET according to the second embodiment will be described with reference to FIG. The method will be described.

First, as shown in FIG. 6A, the first embodiment described above is used.
In the same manner as in the manufacturing method described above, the operating layer 5 made of n-type GaAs or the like is grown on the semiconductor substrate 1 made of GaAs, and the source electrode 1 and the drain electrode 4 are further formed on the operating layer 5 by vapor deposition and lift-off. Form.

Next, as also shown in FIG. 6A, the photoresist 1 having the first and second openings 22b and 21 corresponding to the first and second recesses to be formed on the substrate 6 is formed.
Form 0. Here, the width of the second opening 21 is 0.5 μm, which is the same as that of the first embodiment, and the width of the first opening 22b is the first recess width 1. It is set to an amount of 5 μm, which is removed by side etching by deep etching, for example, 0.7 μm obtained by subtracting 0.4 μm on one side.

After that, such first and second openings 22 are formed.
Using the photoresist 10 having b and 21 as an etching mask, a required voltage is applied between the electrodes 1 and 4 to pass a current through the operating layer 5 to etch the operating layer 5 while checking the current value. The second recess 9 has a depth of 3000 angstroms and a recess width of, for example, 3000 angstroms when the etching is completed when a predetermined current value is obtained or when a predetermined time elapses. From the resist opening width of 0.5 μm, side etching spreads by 0.3 μm or less on each side to 1.1 μm.
A second recess 9 having a length of m or less is formed. Also, the first
The recess 8 is etched more deeply than the second recess 9 described above, and the etching is finished at a stage when another predetermined current value is obtained or when another predetermined time passes. For example, the first recess 8 having a depth of 4000 angstrom and having a recess width of about 1.5 μm which is 0.4 μm wide on one side from the resist opening width of 0.7 μm by side etching is formed. In this way, the first recess 8 is formed by deeply etching the first recess 8 so that the recess width increases as the side etching amount increases. In this case, the same recess forming resist opening is formed. By etching using a resist having a width, the first and second recesses 8 and 9 having different recess widths can be formed.

Next, as shown in FIG. 6C, vapor deposition of the gate metal of Al or WSi, lift-off, or milling of the sputter is performed, and the second recess 9 is formed.
A second gate 3 is formed on the first recess 2, and a first gate 2 is formed on the first recess 8. After that, the surface protection film 7 is formed on the entire surface to complete the formation of the dual gate FET of the second embodiment shown in FIG.

As described above, in the second embodiment, the first gate 2
The recess 8 is made deeper than the recess 9 of the second gate 3 so that the recess width becomes larger due to the large amount of side etching at the time of forming the recess. With the resist having the same opening width with respect to the recess, the recess width of the recess 9 of the second gate 3 which is pulse-driven is narrower than the recess width of the recess 8 of the first gate 2, and as a result, the recess width-gate length becomes It is possible to manufacture a second gate smaller than the first gate, which makes it possible to reduce the gate current and also greatly reduce the gate lag during pulse operation, which is highly reliable and has high-speed pulse operation. There is an effect that a dual gate FET capable of

Example 3. The third aspect of the present invention shown in FIG.
In the second embodiment, the gate length of the second gate 3 that performs the pulse operation is made longer than that of the first embodiment in FIG. 1, and accordingly, the second recess width is also longer. Regarding the recess width of the gate-gate length, the second gate 3 performing the pulse operation is smaller than the other first gate 2 as in the first embodiment.

That is, FIG. 7 is a process chart showing a method of manufacturing the dual gate FET of the third embodiment shown in FIG. 3, and the manufacturing of the dual gate FET according to the third embodiment will be described below with reference to FIG. The method will be described.

First, as shown in FIG. 7 (a), the operating layer 5 is grown on the semiconductor substrate 1 made of GaAs in the same manner as in the manufacturing method of the first and second embodiments, and then the source electrode is formed by vapor deposition and lift-off. 1, and the drain electrode 4 is formed.

Next, as also shown in FIG. 7A, a photoresist 1 having first and second openings 22c and 21 corresponding to the first and second recesses to be formed on the substrate 1 is formed.
Form 0. Here, the size of the first opening 22c is 0.9 μm or more, which is the same as the first embodiment,
The size of the second opening 22 is the same as the gate length of the second gate to be formed, which is about 1 μm.

After that, such first and second openings 22 are formed.
By using the photoresist 10 having c and 21 as an etching mask, a required voltage is applied between the electrodes 1 and 4 to flow a current through the operating layer 5 and the operating layer 5 is observed while the current value is observed. If the first recess 8 and the second recess 9 having a depth of 3000 angstroms are formed by etching, the etching is terminated when a predetermined current value is obtained or when a predetermined time has elapsed. The first recess 8 is formed to have a recess width of about 1.5 μm by adding a side etching amount of 0.3 μm or less on one side to the width of 0.9 μm, while the second recess 9 is formed to have a recess width of about 1.5 μm. Resist opening width of about 1.0 μm 0.3 on one side
Approximately 1.6μ including side etching amount of less than μm
The recess width is less than or equal to m.

Next, as shown in FIG. 7 (c), vapor deposition of the gate metal, lift-off, or milling of the sputter is performed to form the first gate 2 on the first recess 8 and the second gate 2. By forming the second gate 3 on the recess 9 and then forming the surface protection film 7 on the entire surface, the formation of the dual gate FET of the third embodiment shown in FIG. 3 is completed.

As described above, in the third embodiment, the gate length of the second gate 3 that performs the pulse operation is set to be about 1 μm longer than that of the first embodiment, whereby the first recess 8 is formed. Has a recess width of about 1.5 μm, and the second recess 9 has
The recess width will be about 1.6 μm or less.
The recess width-gate length relationship of each gate is similar to that of the first embodiment in that the second gate 3 performing the pulse operation has the first relationship.
It is smaller than Gate 2 of
The first gate 2 side is configured to have a large recess width-gate length to reduce the gate current, while the second gate 3 side performing pulse operation is configured to have a small recess width-gate length. As a result, the gate lag in the pulse operation can be reduced. Therefore, this makes it possible to reduce the gate current and
There is an effect that it is possible to obtain a highly reliable dual gate FET capable of greatly reducing the gate lag during pulse operation and capable of high-speed pulse operation.

Example 4. 4 shows a semiconductor device according to a fourth embodiment of the present invention, which is the same as the semiconductor device according to the third embodiment.
As described above, the gate length of the second gate 3 is longer than the gate length of the first gate 2, so that the recess 9 width of the second gate 3 is almost the same as the recess 8 width of the first gate 2. In this structure, the recess 8 of the first gate 2 is formed in the same manner as in the second embodiment.
Is made deeper than the recess 9 of the second gate 3 and the width of the recess 8 of the first gate 2 is increased by the side etching amount at the time of forming the recess.

FIG. 8 is a process chart showing a method of manufacturing the dual gate FET of the fourth embodiment shown in FIG. 4, and the dual gate FET of the fourth embodiment will be described below with reference to FIG.
The manufacturing method of will be described.

First, as shown in FIG. 8 (a), the operating layer 5 is grown on the semiconductor substrate 1 made of GaAs, and the drain electrodes 4 and The source electrode 1 is formed.

Next, as also shown in FIG. 8A, the first and second recesses corresponding to the first and second recesses to be formed on the substrate.
The photoresist 10 having the second openings 22d and 21 is formed. Here, the size of the second opening 21 is about 1 μm, which is the gate length of the second gate to be formed as in the third embodiment, and the size of the first opening 22d is As in Example 2 above, the thickness is 0.7 μm.

After that, such first and second openings 22 are formed.
Using the photoresist 10 having d and 21 as an etching mask, a required voltage is applied between the two electrodes 1 and 4 while applying a current to the operating layer 5 and observing the current value of the operating layer 5. As for the second recess 9 by etching, the second recess 9 having a depth of 3000 angstrom is formed by terminating the etching when a predetermined current value is obtained or when a predetermined time has passed. Then, at this time, the recess width is increased to 0.3 μm or less on one side by side etching from the resist opening of about 1 μm and becomes 1.6 μm or less. Further, the first recess 8 is etched deeper than the second recess 9 and is etched at a stage when another predetermined current value is obtained or at a stage when another predetermined time passes. When the first recess 8 having a depth of 4000 angstroms is formed by completing the above step, the recess width is expanded from 0.7 μm to 0.4 μm on one side by side etching to about 1.5 μm.

Next, as shown in FIG. 8 (c), vapor deposition of the gate metal, lift-off, or sputter milling is performed to place the first gate 2 on the first recess 8 and the second recess 9 on the second recess 9. The second gate 3 is formed on the surface of the second gate 3 and then the surface protection film 7 is formed on the entire surface to complete the formation of the dual gate FET of the fourth embodiment shown in FIG.

As described above, the fourth embodiment has a structure in which the gate length of the second gate 3 is longer than that of the first gate 2 as in the third embodiment, and the recess formation in the second embodiment is performed. The width of the recess 8 of the first gate 2 is increased by the side etching amount at the time, and the recess width on the side of the first gate 2 and the recess 8 is the same as in the first, second, and third embodiments. -With a large gate length, on the other hand, on the side of the second gate 3 and the recess 9 that perform pulse operation,
By making the recess width-gate length small, it is possible to reduce the gate leakage current in the first gate and prevent the gate lag in the second gate that operates in a pulsed manner, which is highly reliable and There is an effect that an FET capable of high speed pulse operation can be obtained.

In the first and second embodiments, the first
The gate length of the second gate and the gate length of the second gate are substantially equal, and in the third and fourth embodiments, the gate length of the second gate is longer than the gate length of the first gate. However, in the present invention, assuming that the gate length of the first gate is the same value as in the first and second embodiments, the gate length of the second gate is
The second gate of the first and second embodiments may have an intermediate value of the gate length.
It suffices that the gate length of the second gate performing the pulse operation is smaller than that of the other first gate, and the same effect as that of the above-described embodiment can be obtained.

[0063]

As described above, according to the semiconductor device of the present invention, the operating layer formed on the semiconductor substrate, the source electrode and the drain electrode formed at respective required positions on the operating layer, First and second recesses having first and second recess widths respectively formed at two required positions between the source electrode and the drain electrode on the operation layer, and the first and second recesses. A first gate electrode and a second gate electrode respectively formed on the recesses, the second gate electrode is turned on and off by a pulse, and the recess width and the gate length of each gate electrode are The difference between the first gate and the second gate is smaller than the first gate.
Dual-gate FE with high leak rate, low leakage current in the gate, small gate lag in the second gate that turns on and off by pulse operation, and high reliability
There is an effect that T can be obtained.

According to the invention, in the above semiconductor device, the gate length of the second gate electrode is substantially equal to the gate length of the first gate electrode, and the recess width and the gate length of each gate electrode are the same. Since the difference between the second gate and the second gate is smaller than that of the first gate, the leakage current in the first gate is small, and the gate lag is small in the second gate that is turned on / off by pulse operation There is an effect that a highly efficient dual gate FET capable of high-speed pulse operation can be configured.

According to the invention, in the above semiconductor device, the gate length of the second gate electrode is longer than the gate length of the first gate electrode, and the recess width and the gate length of each gate electrode are equal to each other. Since the difference between the second gate and the first gate is smaller than that of the first gate, the leakage current in the first gate is small, and the gate lag is small in the second gate which is turned on / off by the pulse operation. There is an effect that a high-reliability dual-gate FET capable of high-speed pulse operation can be configured.

Further, according to the invention, in the semiconductor device, the first and second recesses are both etched in the operation layer through an etching mask opening having an opening width approximately equal to a recess width to be formed. Since the first and second recesses have the same depth, the difference between the recess width and the gate length of each of the gate electrodes is larger in the second gate than in the first gate. FET smaller than gate
Due to the structure, a dual-gate FET having a high leak rate at the first gate, a small gate lag at the second gate which is turned on and off by pulse operation, and high reliability and capable of high-speed pulse operation is provided. There is an effect that can be configured.

According to the present invention, in the semiconductor device, the first and second recesses are formed by etching the etching mask opening having an opening width approximately equal to the recess width to be formed. In the second recess, the operation layer is etched through an etching mask opening having an opening width smaller than the recess width to be formed, and the second recess is formed.
Since the recess is formed to have a recess width larger than the above resist opening by deeper etching and side etching, the depth of the first and second recesses is deeper in the first recess. Since the difference between the recess width and the gate length of each gate electrode is smaller in the second gate than in the first gate, the leakage current in the first gate is small and the pulse operation is turned on and off. There is an effect that a highly reliable dual gate FET having a small gate lag at the second gate and capable of high-speed pulse operation can be configured.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an operation layer on a semiconductor substrate,
A step of forming a source electrode and a drain electrode at respective required positions on the operating layer, and two required positions of the operating layer between the source electrode and the drain electrode for the first and second recesses, A step of forming first and second recesses each having a desired recess width by etching through an etching mask opening having an opening width approximately equal to the recess width to be formed; and each of the first and second recesses. A step of forming first and second gate electrodes each having a required gate length such that the difference between the recess width and the gate length of each gate electrode is smaller in the second gate than in the first gate. Since the difference between the recess width of each gate electrode and the gate length is
Since the second gate is smaller than the first gate, the leakage current in the first gate is small, the gate lag in the second gate that is turned on / off by pulse operation is small, and the reliability is high. Moreover, there is an effect that a dual gate FET capable of high-speed pulse operation can be manufactured.

According to the method of manufacturing a semiconductor device of the present invention, the step of forming an operating layer on a semiconductor substrate, the step of forming a source electrode and a drain electrode at each required position on the operating layer, At the two required positions between the source electrode and the drain electrode of the operating layer, the first recess is formed by an etching mask opening having the same opening width as the recess width to be formed, and the second recess is formed. Etching is performed through an etching mask opening having an opening width smaller than the desired recess width, and the second recess is etched deeper, and the side etching is performed so that the recess width is larger than the etching mask opening. A step of forming first and second recesses having a width, and a recess width and a gate of each gate electrode on each of the first and second recesses. A step of forming first and second gate electrodes having required gate lengths in which the difference between the gate length and the second gate is smaller than that of the first gate. Since the difference between the recess width of the electrode and the gate length of the second gate is smaller than that of the first gate, the leakage current at the first gate is small and the second gate is turned on and off by the pulse operation. There is an effect that it is possible to manufacture a dual gate FET having a small gate lag in the gate, a large depth of the first recess, a high reliability, and a high-speed pulse operation.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a first conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a second conventional semiconductor device.

11 is a cutaway side view of a main part of a general recess type GaAs-MESFET having three types of structures of A, B and C shown in FIG. 2 of Japanese Patent Publication No. 5-62462 (FIG. 11).
(a), (b), (c)).

FIG. 12 shows the three types of M shown in FIG. 3 of the publication.
It is a figure which shows the input-output characteristic of ESFET.

[Explanation of symbols]

 1 Source Electrode 2 First Gate 3 Second Gate 4 Drain Electrode 5 Working Layer 6 Semiconductor Substrate 7 Surface Protection Film 8 Recess of First Gate 9 Recess of Second Gate 10 Etching Mask 11 Semi-insulating GaAs Substrate 12 GaAs Active Layer 13 Recess 14 Source electrode 15 Drain electrode 16 Gate electrode 17 Surface protective film Wr Recess width Lg Gate length 22a, 22b, 22c, 22d First opening 21 First opening

Claims (7)

[Claims] 1. An operating layer formed on a semiconductor substrate, a source electrode and a drain electrode formed at respective required positions on the operating layer, and between the source electrode and the drain electrode on the operating layer. Two
First and second recesses formed at two required positions and respectively having first and second recess widths, and first and second recesses formed on the first and second recesses, respectively.
A second gate electrode is provided, and the second gate electrode is turned on / off by a pulse, and the difference between the recess width and the gate length of each gate electrode is larger in the second gate. A semiconductor device characterized by being smaller than the first gate. 2. The semiconductor device according to claim 1, wherein both the first and second recesses are etched in the operation layer through an etching mask opening having an opening width approximately equal to a recess width to be formed. A semiconductor device which is formed by performing 3. The semiconductor device according to claim 1, wherein the first recess is an etching mask opening having an opening width substantially equal to a recess width to be formed, and the second recess is to be formed. The operating layer is etched through an etching mask opening having an opening width smaller than the recess width, and the second recess is formed by etching sideways to have a recess width larger than the etching mask opening by side etching. A semiconductor device characterized by being a thing. 4. The semiconductor device according to claim 2, wherein the gate length of the second gate electrode is substantially equal to the gate length of the first gate electrode. 5. The semiconductor device according to claim 2, wherein a gate length of the second gate electrode is longer than a gate length of the first gate electrode. 6. A step of forming an operating layer on a semiconductor substrate, a step of forming a source electrode and a drain electrode at required positions on the operating layer, and a step of forming a source electrode and a drain electrode on the operating layer. Are etched from the etching mask openings for the first and second recesses having opening widths approximately the same as the recess width to be formed, and the first and second recesses having the required recess widths are formed.
The step of forming the second recess, and the difference between the recess width and the gate length of each gate electrode on the first and second recesses is smaller in the second gate than in the first gate. And a step of forming first and second gate electrodes having respective required gate lengths. 7. A step of forming an operating layer on a semiconductor substrate, a step of forming a source electrode and a drain electrode at respective required positions on the operating layer, and a step of forming a portion between the source electrode and the drain electrode of the operating layer. The two required positions of the first recess are defined by an etching mask opening having an opening width as large as the recess width to be formed,
The second recess is etched from an etching mask opening having an opening width smaller than the recess width to be formed, and the second recess is etched deeper to have a recess width larger than the etching mask opening by side etching. So as to form the first and second recesses each having a required recess width, and the difference between the recess width and the gate length of each gate electrode on each of the first and second recesses, And a step of forming first and second gate electrodes each having a required gate length in which the second gate is smaller than the first gate.