JPH06232207A - Method for sealing semiconductor device, and sealing structure - Google Patents
Method for sealing semiconductor device, and sealing structureInfo
- Publication number
- JPH06232207A JPH06232207A JP5013930A JP1393093A JPH06232207A JP H06232207 A JPH06232207 A JP H06232207A JP 5013930 A JP5013930 A JP 5013930A JP 1393093 A JP1393093 A JP 1393093A JP H06232207 A JPH06232207 A JP H06232207A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- sealing
- thermoplastic resin
- face down
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000007789 sealing Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 24
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 229920005989 resin Polymers 0.000 abstract description 14
- 239000011347 resin Substances 0.000 abstract description 14
- 230000008646 thermal stress Effects 0.000 abstract description 7
- 230000035882 stress Effects 0.000 abstract description 5
- 230000008961 swelling Effects 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置を回路基板
に実装する際の封止に関するものであり、特にフェース
ダウンで実装してなる半導体装置の封止方法と封止構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sealing method for mounting a semiconductor device on a circuit board, and more particularly to a method and structure for sealing a semiconductor device mounted face down. .
【０００２】[0002]
【従来の技術】従来、半導体装置の回路基板上への実装
には半田付けがよく利用されていたが、近年、半導体装
置のパッケージの小型化と接続端子数の増加により、接
続端子間隔が狭くなり、従来の半田付け技術で対処する
ことが次第に困難になってきた。2. Description of the Related Art Conventionally, soldering has been often used for mounting a semiconductor device on a circuit board. In recent years, however, due to the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals, the connection terminal spacing has become narrow. It has become increasingly difficult to deal with the conventional soldering technology.
【０００３】そこで、最近では裸の半導体装置を回路基
板上に直付けして実装面積の小型化と効率的使用を図ろ
うとする方法が考えだされてきた。一例として、半導体
装置を回路基板に接続するに際し、予め半導体装置のア
ルミ電極パッド上に密着金属や拡散防止金属の蒸着膜
と、この蒸着膜上にメッキにより形成した半田層とから
なる電極構造を有する半導体装置をフェースダウンに
し、高温に加熱して半田を回路基板の端子電極に融着す
る。この実装構造は、接続後の機械的強度が強く、接続
が一括にできることなどから有効な方法であるとされて
いる(例えば、工業調査会、1980年１月15日発行、日本
マイクロエレクトロニクス協会編、「ＩＣ化実装技
術」)。Therefore, recently, a method of directly mounting a bare semiconductor device on a circuit board to reduce the mounting area and efficiently use it has been considered. As an example, when connecting a semiconductor device to a circuit board, an electrode structure including a vapor deposition film of an adhesion metal or a diffusion preventing metal on an aluminum electrode pad of the semiconductor device in advance and a solder layer formed by plating on the vapor deposition film is used. The semiconductor device is placed face down and heated to a high temperature to fuse the solder to the terminal electrodes of the circuit board. This mounting structure is said to be an effective method because it has high mechanical strength after connection and can be connected all at once (for example, Industrial Research Society, published on January 15, 1980, edited by Japan Microelectronics Association). , "IC packaging technology").
【０００４】以下、図面を参照しながら上述した従来の
半導体装置の封止方法と、封止構造の一例について説明
する。An example of the conventional method for sealing a semiconductor device and an example of the sealing structure will be described below with reference to the drawings.
【０００５】図３は従来のフェースダウンで実装された
半導体装置の封止構造の要部断面図である。FIG. 3 is a cross-sectional view of a main part of a conventional face-down mounted semiconductor device sealing structure.
【０００６】この図３において、１は半導体装置、２は
回路基板、３は回路基板２の表面に形成された端子電
極、４は半導体装置１の電極パッド部に設けられた半田
バンプ電極、８は半導体装置１を封止した封止樹脂であ
る。In FIG. 3, 1 is a semiconductor device, 2 is a circuit board, 3 is a terminal electrode formed on the surface of the circuit board 2, 4 is a solder bump electrode provided on an electrode pad portion of the semiconductor device 1, and 8 is a solder bump electrode. Is a sealing resin that seals the semiconductor device 1.
【０００７】以上のように構成された従来のフェースダ
ウンで実装された半導体装置の封止方法について、以下
その概略を説明する。An outline of a conventional method for sealing a face-down mounted semiconductor device having the above structure will be described below.
【０００８】まず、半田バンプ電極４を有する半導体装
置１を、回路基板２の端子電極３の所定の位置に位置合
わせを行なってフェースダウンで積載した後、200〜300
℃の高温に加熱して半田を溶融し、半導体装置１の実装
を行なう。First, the semiconductor device 1 having the solder bump electrode 4 is aligned with a predetermined position of the terminal electrode 3 of the circuit board 2 and loaded face down, and then 200 to 300.
The semiconductor device 1 is mounted by heating to a high temperature of ℃ to melt the solder.
【０００９】その後、半導体装置１の周囲とこの半導体
装置１と回路基板２との間隙に液状の封止樹脂８を充填
し、熱硬化することで半導体装置１の封止構造を得るも
のである。After that, a liquid sealing resin 8 is filled in the periphery of the semiconductor device 1 and in the gap between the semiconductor device 1 and the circuit board 2 and heat-cured to obtain a sealing structure of the semiconductor device 1. .
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、上記の
ような半導体装置の封止構造においては、次のような問
題がある。However, the above-mentioned semiconductor device sealing structure has the following problems.
【００１１】１．半導体装置１と回路基板２との間隙に
充填した液状の封止樹脂８を熱硬化する際に、封止樹脂
８の硬化収縮などによる熱応力が半導体装置１と回路基
板２との接合部に加わる。1. When the liquid encapsulating resin 8 filled in the gap between the semiconductor device 1 and the circuit board 2 is thermally cured, thermal stress due to curing shrinkage of the encapsulating resin 8 is applied to the joint between the semiconductor device 1 and the circuit board 2. Join.
【００１２】２．半導体装置１と回路基板２との間隙に
充填した封止樹脂８の吸湿による膨潤のために前記接合
部に応力が加わる。2. Stress is applied to the joint portion due to swelling of the sealing resin 8 filled in the gap between the semiconductor device 1 and the circuit board 2 due to moisture absorption.
【００１３】３．半導体装置１と回路基板２との間隙に
充填した封止樹脂８の弾性率が大きいため、高温時や低
温時に前記接合部に応力が加わる。3. Since the elastic modulus of the sealing resin 8 filled in the gap between the semiconductor device 1 and the circuit board 2 is large, stress is applied to the joint portion at high temperature or low temperature.
【００１４】その結果、半導体装置１と回路基板２との
接続の信頼性が乏しいといった課題を有していた。As a result, there is a problem that the reliability of the connection between the semiconductor device 1 and the circuit board 2 is poor.
【００１５】本発明は上記の課題に鑑みてなされたもの
であり、その目的とするところは、半導体装置と回路基
板との接続を信頼性の高い半導体装置の封止方法と封止
構造とを提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable semiconductor device sealing method and a sealing structure for connecting a semiconductor device and a circuit board. To provide.
【００１６】[0016]
【課題を解決するための手段】本発明の半導体装置の封
止方法は、半導体装置をフェースダウンで回路基板に実
装した前記半導体装置の周囲に熱可塑性樹脂からなる枠
を設置する工程と、前記熱可塑性樹脂からなる枠を加熱
して可塑化させる工程と、可塑化した熱可塑性樹脂によ
り半導体装置の周囲を保持すると同時に半導体装置と回
路基板との間隙に空隙を設ける工程とからなることを特
徴とする。A method for sealing a semiconductor device according to the present invention comprises a step of installing a frame made of a thermoplastic resin around the semiconductor device in which the semiconductor device is mounted face down on a circuit board, and It is characterized by comprising a step of heating a frame made of a thermoplastic resin to plasticize it, and a step of holding the periphery of the semiconductor device with the plasticized thermoplastic resin and at the same time providing a gap in the gap between the semiconductor device and the circuit board. And
【００１７】また、本発明の半導体装置の封止構造は、
フェースダウンで実装した半導体装置と回路基板との間
隙に空隙を有し、前記半導体装置の周囲を熱可塑性樹脂
で半導体装置を回路基板に保持したことを特徴とする。The semiconductor device sealing structure of the present invention is
It is characterized in that a gap is provided between the semiconductor device mounted face down and the circuit board, and the periphery of the semiconductor device is held on the circuit board by a thermoplastic resin.
【００１８】[0018]
【作用】本発明によれば、フェースダウンで実装した半
導体装置と回路基板との間隙に空隙を有し、半導体装置
の周囲を熱可塑性樹脂で封止する封止構造を有すること
により、フェースダウンで実装した半導体装置を封止す
る製造時や封止樹脂の膨潤などによる半導体装置と回路
基板との接合部への熱応力の影響を小さくすることがで
き、信頼性の高い半導体装置の封止方法および封止構造
が実現できる。According to the present invention, by providing a gap between the semiconductor device mounted by face down and the circuit board and having a sealing structure for sealing the periphery of the semiconductor device with a thermoplastic resin, the face down A highly reliable semiconductor device that can reduce the influence of thermal stress on the joint between the semiconductor device and the circuit board due to the swelling of the encapsulation resin during the encapsulation of the semiconductor device mounted in The method and the sealing structure can be realized.
【００１９】[0019]
【実施例】以下、本発明の一実施例の半導体装置の封止
方法と封止構造について、図面を参照しながら説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device sealing method and structure according to an embodiment of the present invention will be described below with reference to the drawings.
【００２０】図１は本発明の一実施例における半導体装
置の封止方法を説明する工程図、図２は前記図１の封止
方法により作製された半導体装置の封止構造の要部断面
図である。FIG. 1 is a process diagram for explaining a method of sealing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of an essential part of a semiconductor device sealing structure produced by the sealing method of FIG. Is.
【００２１】図１および図２において、１は半導体装
置、２は半導体装置１を取り付ける回路基板、３は回路
基板２の表面に形成された端子電極、４は半導体装置１
の電極パッドに設けられた半田バンプ電極である。これ
らは従来と同様である。本実施例における５は熱可塑性
樹脂からなる枠、６は可塑化した熱可塑性樹脂、７は半
導体装置１と回路基板２との間隙に設けられた空隙であ
る。1 and 2, 1 is a semiconductor device, 2 is a circuit board on which the semiconductor device 1 is mounted, 3 is a terminal electrode formed on the surface of the circuit board 2, and 4 is a semiconductor device 1.
Is a solder bump electrode provided on the electrode pad. These are the same as conventional ones. In this embodiment, 5 is a frame made of a thermoplastic resin, 6 is a plasticized thermoplastic resin, and 7 is a gap provided in the gap between the semiconductor device 1 and the circuit board 2.
【００２２】以上のように構成された半導体装置の封止
方法について、以下、図１を用いて説明する。A method of sealing the semiconductor device having the above structure will be described below with reference to FIG.
【００２３】まず、半田バンプ電極４を有する半導体装
置１を、回路基板２の端子電極３の所定の位置に位置合
わせを行なってフェースダウンで積載した後、200〜300
℃の高温に加熱して半田を溶融して、図１(1)に示す半
導体装置１の実装体を得る。First, the semiconductor device 1 having the solder bump electrodes 4 is aligned with a predetermined position of the terminal electrodes 3 of the circuit board 2 and loaded face down, and then 200 to 300.
The solder is melted by heating to a high temperature of ℃, to obtain a mounting body of the semiconductor device 1 shown in FIG.
【００２４】その後、図１(2)に示すように、半導体装
置１の周囲を取り囲むように熱可塑性樹脂からなる枠５
を設置する。Thereafter, as shown in FIG. 1 (2), a frame 5 made of a thermoplastic resin is formed so as to surround the semiconductor device 1.
Set up.
【００２５】さらに、熱可塑性樹脂からなる枠５を樹脂
の熱可塑点以上に加熱することにより、図１(3)に示す
ように半導体装置１の周囲に設置した熱可塑性樹脂から
なる枠５を熱可塑化させて、半導体装置１の周囲を可塑
化した熱可塑性樹脂６により回路基板２に保持すると同
時に半導体装置１と回路基板２との間隙に空隙７を設け
た半導体装置１の封止構造を得るものである。Further, by heating the frame 5 made of thermoplastic resin to a temperature not lower than the thermoplastic point of the resin, the frame 5 made of thermoplastic resin installed around the semiconductor device 1 as shown in FIG. A sealing structure of the semiconductor device 1 in which the periphery of the semiconductor device 1 is thermoplasticized and held on the circuit board 2 by the plasticized thermoplastic resin 6 and at the same time, a gap 7 is provided in the gap between the semiconductor device 1 and the circuit board 2. Is what you get.
【００２６】最後に、可塑化した熱可塑性樹脂６を常温
に冷却して再硬化することによって、図２に示す半導体
装置１と回路基板２との間隙に空隙７を設け、かつ可塑
化した熱可塑性樹脂６により半導体装置１の周囲を回路
基板２に保持した構造の半導体装置１の封止構造を得る
ものである。Finally, the plasticized thermoplastic resin 6 is cooled to room temperature and re-cured to form a gap 7 between the semiconductor device 1 and the circuit board 2 shown in FIG. It is intended to obtain a sealing structure of the semiconductor device 1 in which the periphery of the semiconductor device 1 is held on the circuit board 2 by the plastic resin 6.
【００２７】本発明の半導体装置の封止方法は、上記し
た方法により、従来のフェースダウンで実装した半導体
装置の封止方法で問題であった封止樹脂の熱硬化時の硬
化収縮などによる半導体装置１と回路基板２との接合部
への熱応力が空隙７を設けたことによりほとんどなくな
り、極めて安定で信頼性高く半導体装置を封止すること
ができる。The method for sealing a semiconductor device according to the present invention uses the above-mentioned method, which is a problem in the conventional method for sealing a semiconductor device mounted facedown, due to curing shrinkage during heat curing of the sealing resin. The thermal stress on the joint between the device 1 and the circuit board 2 is almost eliminated by providing the air gap 7, and the semiconductor device can be sealed extremely stably and highly reliably.
【００２８】さらに、上記した方法により作製した本発
明の半導体装置の封止構造は、従来のフェースダウンで
実装した半導体装置の封止構造で問題であった封止樹脂
の吸湿による膨潤のための半導体装置１と回路基板２と
の接合部への応力や、高温時や低温時の接合部への熱応
力が空隙７を設けたことによりほとんどなくなり、極め
て安定で信頼性の高い半導体装置の封止構造を得ること
ができる。Further, the sealing structure of the semiconductor device of the present invention manufactured by the above-mentioned method is for swelling due to moisture absorption of the sealing resin, which is a problem in the conventional sealing structure of the semiconductor device mounted face down. The stress on the joint between the semiconductor device 1 and the circuit board 2 and the thermal stress on the joint at high temperature and low temperature are almost eliminated by providing the voids 7, and the sealing of the semiconductor device is extremely stable and highly reliable. A stop structure can be obtained.
【００２９】なお、本実施例では、半導体装置１を半田
バンプ電極４にて回路基板２にフェースダウンで実装す
るとしたが、導電性接着剤を用いた実装方法など他の方
法で半導体装置１をフェースダウンで実装してもよい。In this embodiment, the semiconductor device 1 is mounted face down on the circuit board 2 with the solder bump electrodes 4, but the semiconductor device 1 is mounted by another method such as a mounting method using a conductive adhesive. You may implement face down.
【００３０】また、半導体装置１と回路基板２との間隙
の空隙７には、不活性ガスを封入してもよい。An inert gas may be filled in the space 7 between the semiconductor device 1 and the circuit board 2.
【００３１】[0031]
【発明の効果】以上説明したように本発明の半導体装置
の封止方法によれば、従来のフェースダウンで実装した
半導体装置の封止方法で問題であった封止樹脂の熱硬化
時の硬化収縮などによる半導体装置と回路基板との接合
部への熱応力が空隙を設けたことによりほとんどなくな
り、極めて安定で信頼性高く半導体装置を封止すること
ができる。As described above, according to the method for sealing a semiconductor device of the present invention, curing of the sealing resin at the time of thermosetting, which has been a problem in the conventional method for sealing a semiconductor device mounted face down. By providing the void, the thermal stress to the joint between the semiconductor device and the circuit board due to shrinkage or the like is almost eliminated, and the semiconductor device can be sealed extremely stably and highly reliably.
【００３２】さらに、上記した方法により作製された本
発明の半導体装置の封止構造は、、従来のフェースダウ
ンで実装した半導体装置の封止構造で問題であった封止
樹脂の吸湿による膨潤のための半導体装置と回路基板と
の接合部への応力や、高温時や低温時の前記接合部への
熱応力が、空隙を設けたことによりほとんどなくなり、
極めて安定で信頼性の高い半導体装置の封止構造を得る
ことができる。Furthermore, the semiconductor device encapsulation structure of the present invention manufactured by the above-described method has the problem of swelling due to moisture absorption of the encapsulation resin, which has been a problem in the conventional face-down mounted semiconductor device encapsulation structure. For the stress to the joint portion of the semiconductor device and the circuit board for, and the thermal stress to the joint portion at high temperature or low temperature is almost eliminated by providing the void,
An extremely stable and highly reliable semiconductor device sealing structure can be obtained.
【図１】本発明の一実施例における半導体装置の封止方
法を説明する工程図である。FIG. 1 is a process diagram illustrating a method for sealing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例における半導体装置の封止構
造の要部断面図である。FIG. 2 is a cross-sectional view of a main part of a semiconductor device sealing structure according to an embodiment of the present invention.
【図３】従来のフェースダウンで実装された半導体装置
の封止構造の要部断面図である。FIG. 3 is a cross-sectional view of a principal part of a conventional face-down mounted semiconductor device sealing structure.
１…半導体装置、 ２…回路基板、 ３…端子電極、
４…半田バンプ電極、５…熱可塑性樹脂からなる枠、
６…可塑化した熱可塑性樹脂、 ７…空隙、８…封止樹
脂。1 ... Semiconductor device, 2 ... Circuit board, 3 ... Terminal electrode,
4 ... Solder bump electrodes, 5 ... Frame made of thermoplastic resin,
6 ... Plasticized thermoplastic resin, 7 ... Void, 8 ... Sealing resin.
Claims (6)
に実装した前記半導体装置の周囲に熱可塑性樹脂からな
る枠を設置する工程と、前記熱可塑性樹脂からなる枠を
加熱して可塑化させる工程と、可塑化した熱可塑性樹脂
により半導体装置の周囲を保持すると同時に半導体装置
と回路基板との間隙に空隙を設ける工程とからなること
を特徴とする半導体装置の封止方法。1. A step of installing a frame made of a thermoplastic resin around the semiconductor device in which a semiconductor device is mounted face down on a circuit board, and a step of heating the frame made of the thermoplastic resin to plasticize the frame. And a step of holding a periphery of the semiconductor device with a plasticized thermoplastic resin and at the same time providing a space in a gap between the semiconductor device and the circuit board.
フェースダウンで実装したことを特徴とする請求項１記
載の半導体装置の封止方法。2. The method for encapsulating a semiconductor device according to claim 1, wherein the semiconductor device is mounted face down on a circuit board with solder bumps.
にフェースダウンで実装したことを特徴とする請求項１
記載の半導体装置の封止方法。3. The semiconductor device is mounted face down on a circuit board with a conductive adhesive.
A method for sealing a semiconductor device as described above.
回路基板との間隙に空隙を有し、前記半導体装置の周囲
を熱可塑性樹脂で半導体装置を回路基板に保持したこと
を特徴とする半導体装置の封止構造。4. A semiconductor device, characterized in that a gap is provided between a semiconductor device mounted face down and a circuit board, and the periphery of the semiconductor device is held on the circuit board by a thermoplastic resin. Sealing structure.
フェースダウンで実装したことを特徴とする請求項４記
載の半導体装置の封止構造。5. The encapsulation structure for a semiconductor device according to claim 4, wherein the semiconductor device is mounted face down on the circuit board with solder bumps.
にフェースダウンで実装したことを特徴とする請求項４
記載の半導体装置の封止構造。6. The semiconductor device is mounted face down on a circuit board with a conductive adhesive.
A sealing structure for a semiconductor device as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5013930A JPH06232207A (en) | 1993-01-29 | 1993-01-29 | Method for sealing semiconductor device, and sealing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5013930A JPH06232207A (en) | 1993-01-29 | 1993-01-29 | Method for sealing semiconductor device, and sealing structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06232207A true JPH06232207A (en) | 1994-08-19 |
Family
ID=11846910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5013930A Pending JPH06232207A (en) | 1993-01-29 | 1993-01-29 | Method for sealing semiconductor device, and sealing structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06232207A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998010465A1 (en) * | 1996-09-05 | 1998-03-12 | Seiko Epson Corporation | Connecting structure of semiconductor element, liquid crystal display device using the structure, and electronic equipment using the display device |
-
1993
- 1993-01-29 JP JP5013930A patent/JPH06232207A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998010465A1 (en) * | 1996-09-05 | 1998-03-12 | Seiko Epson Corporation | Connecting structure of semiconductor element, liquid crystal display device using the structure, and electronic equipment using the display device |
| US6940180B1 (en) | 1996-09-05 | 2005-09-06 | Seiko Epson Corporation | Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit |
| US7084517B2 (en) | 1996-09-05 | 2006-08-01 | Seiko Epson Corporation | Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit |
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