JPH05291941A - Programmable logic device - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention relates to a programmable logic device, and in particular, to a programmable logic device capable of realizing multi-stage logic in one chip. The purpose is to be able to configure multi-level logic of. [Structure] An input section 1 to which an external input is input, a front-stage AND array section 2-1 and a front-stage OR array section 2-2 to which an output of the input section is input, and an output of the front-stage AND array section 2-1 are connected to the front-stage. Input to the OR array section 2-2, and the OR array section of the preceding stage
A feedback matrix section that feeds back the output of 2-2 to the input of the preceding AND array section 2-1.
5-1 and 5-2, a rear-stage OR array unit 3-1 to which the output of the front-stage AND array unit 2-1 is input, and a front-stage OR array unit 2-2
Of the output of the latter stage AND array unit 3-2 and the latter stage O
The output section 4 outputs the outputs of the R array section 3-1 and the post-stage AND array section 3-2 to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device, and more particularly to a programmable logic device capable of realizing multi-stage logic in one chip.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional PLD including a combination of an AND array section and an OR array section.

A conventional PLD (Programmable Logic Device) for realizing a programmable combinational logic circuit on an IC
However, since it is composed of a two-stage combination of an AND array section and an OR array section, only a two-stage logic circuit can be realized inside the PLD.

Therefore, in order to realize a multi-stage combinational logic circuit having two or more stages, it is necessary to add an external feedback circuit as shown in FIG. 3 and feed back the output to the input.

That is, in FIG. 3, 1 is an input section composed of an input buffer, 2 is an AND array section, 3 is an OR array section, and 4 is an output section composed of an output buffer. In the AND array section, a logical product between input signals selectively connected to the product term line from a plurality of inputs is obtained (schematically represented by an AND gate). A plurality of product term lines output from the AND array section 1 are input to the OR array section 3 and selectively connected to the output line (sum term line) to obtain a logical sum, and the output section 4 outputs external signals. Is output to.

In order to realize a multi-stage logic of three or more stages, the output of the PLD is fed via the external feedback line 5.
It was realized by connecting to the input. For example, in Fig. 3, if you program so that the intersections marked with ● are connected, the input to i2 to i5 is output to the o2 output terminal as f = (i2 * i4 + i2 * i5) * i5 + i2 * i5 The result of the 4-stage logical operation is output. Although this example is illustrated as a simple logic in order to explain the 4-stage logic, it is actually necessary to realize a more complex and complex logic.

[0007]

SUMMARY OF THE INVENTION In the above-mentioned conventional method of realizing multi-stage logic by an external feedback line of a PLD,
Since the feedback signal passes through the input / output buffer and the external circuit, the signal delay time is large and the high speed is sacrificed.

Since the input / output pins are used for feedback, there is a shortage of input / output pins assigned to external input / output. The problem has arisen.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a PLD capable of constructing an arbitrary multistage logic while minimizing the time delay due to feedback.

[0010]

FIG. 1 is a block diagram of a programmable logic device of the present invention. As shown in FIG. 1, the above-mentioned problem is caused by the input unit 1 that receives an external input.
And the preceding AND array section 2-1 to which the output of the input section is input
And the preceding OR array section 2-2 and the preceding AND array section
The output of 2-1 is input to the preceding-stage OR array section 2-2, and the output of the preceding-stage OR array section 2-2 is referred to as the preceding-stage AND array section 2-.
Feedback matrix sections 5-1 and 5-2 which respectively feed back to the input of 1 and the preceding AND array section
2-1 output of the rear OR array section 3-1 and the output of the previous OR array section 2-2 input of the rear AND array section
3-2 and an output unit 4 for outputting the outputs of the latter-stage OR array unit 3-1 and the latter-stage AND array unit 3-2 to the outside, which is solved by the programmable logic device of the present invention. It

[0011]

The same input can be connected to the two front-end array sections of AND and OR, and one output can be arbitrarily fed back to the other input in the front-end array section by the feedback matrix, so that the delay time is remarkable. And increase the number of I / O pins and AND-O
R-AND -... Or OR-AND-OR -...
It is possible to realize an arbitrary number of stages of logic circuits in combination.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The programmable logic device of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a circuit diagram of an embodiment of the programmable logic device of the present invention. Note that the same reference numeral represents the same object throughout the drawings.

In FIG. 2, 1 is an input unit, 2-1 is a front stage A.
ND array section, 2-2 is the front stage OR array section, 3-1 is the rear stage O
R array section, 3-2 is the latter AND array section, 4 is the output section,
5-1 and 5-2 are feedback matrix sections. 6
-1, 6-2 are product term lines, 7-1, 7-2 are sum term lines.

When a plurality of inputs are selectively connected via diodes or transistors, the product term lines 6-1 and 6-2 output a logical product of the connected inputs, and the sum term line 7- 1
, 7-2 similarly outputs the logical sum of the selectively connected inputs. Dotted logic element symbols indicate these functions equivalently.

51 and 52 are feedback lines. The feedback line 51 is an extension of the product term line 6-1 and the sum term line 7-1.
The feedback line 5-1 is provided so as to intersect with the extension of the sum term line 7-1 and the product term line 6-1 respectively.
Configure 5-2.

The sum term line 7-2 is an output line, one end of which is input to the buffer amplifier of the output section 4 and intersects the output side of the product term line 7-1 in the middle. The product term line 6-2 is also an output line, which is also input to the output section 4 and intersects the output side of the sum term line 7-1.

It is possible to obtain a multi-stage logic circuit having a desired logic configuration by programming the connection and non-connection of these intersections by a known conventional technique. For example, in Figure 2
The indicia indicate intersections programmed and connected to the PLD of the present invention to implement the same logic described in the prior art of FIG. 3, other intersections indicate no connections.

The external inputs i1 to i5 pass through the buffer amplifier of the input section 1, and are connected to the preceding AND array section 2-1 and the preceding OR.
Input to array section 2-2. Product term line of previous AND array
AND of i2 and i4 obtained by 6-1 i2 * i4 and i2 and i5
The logical product i2 * i5 of the above is fed back to the sum line 7-1 through the feedback matrix 5-1 as shown by the arrow, and is input to the preceding OR array section 2-2 to obtain the logical sum (i2 * i4 + i2 * I5) is obtained. This result is fed back to the product term line 6-1 of the preceding AND array section 2-2 via the feedback matrix section 5-2 as shown by the arrow, and the logical product (i2 * i4 + i2 * i5) * i5 with i5 is obtained. .. Then, this value and i2 * i5 are logically ORed by the output sum term line 7-2, and through the output unit 4, the external output o1 is the 4-stage logical operation result f = (i2 * i4 + i2 * i5) * I5 + i2 * i5 is output externally.

FIG. 2 also shows a case where the external output o3 is programmed so that the result of three-stage logical operation, g = (i2 * i4 + i2 * i5) * i1, is output.

As described above, the external feedback line is used by providing both the AND gate and the OR gate as the gate array unit in the preceding stage for receiving the external input and providing the hood back matrix for feeding back the output as the other input. Without this, a multi-stage logic can be realized by a two-stage PLD, so that a multi-stage logic circuit with a small operation delay and a sufficient number of input / output pins can be constructed.

[0021]

As described above, according to the PLD of the present invention, it is possible to realize a more complex multi-stage logic circuit with a degree of integration equivalent to that of a conventional PLD, a small time delay.

[Brief description of drawings]

FIG. 1 is a block diagram of a programmable logic device of the present invention.

FIG. 2 is a circuit diagram of a programmable logic device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a conventional programmable logic device.

[Explanation of symbols]

1 ... Input part, 2-1 ... Pre-stage AND array part, 2-2 ... Pre-stage O
R array section, 3-1 ... rear stage OR array section, 3-2 ... rear stage AN
D array section, 4 ... Output section, 5-1, 5-2 ... Feedback matrix section

Claims (1)

[Claims] 1. An input section (1) to which an external input is input and a pre-stage AND array section (2-) to which an output of the input section (1) is input.
1) and the preceding OR array section (2-2) and the output of the preceding AND array section (2-1) to the input of the preceding OR array section (2-2), and the preceding OR array section (2- The feedback matrix section (5-1, 5) that feeds back the output of 2) to the input of the preceding AND array section (2-1), respectively.
-2), and the output of the preceding AND array section (2-1) inputs the following OR
The array section (3-1) and the latter stage AND to which the output of the former stage OR array section (2-2) is input
An array section (3-2), the latter-stage OR array section (3-1) and the latter-stage AND array section (3
-2) The output part (4) which outputs the output to the outside, The programmable logic device characterized by the above-mentioned.