JPH05235048A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To arrange dispersedly operating layer and to reduce the heat resistance of an element. CONSTITUTION:In a field-effect transistor of a constitution, wherein a plurality of gate finer electrodes 6, 7, 8 and 9 are formed in arrangement o operating layers 10b, 10a and 10c on a semiconductor substrate and source finger electrodes 4, 5, 14 and 15 and drain finger electrodes 1, 2 and 3 are formed on both sides of the electrodes 6, 7, 8 and 9, the layer 10a, 10b and 10c are dispersedly formed and the plurality of the electrodes 6, 7, 8 and 9 are alternately formed in the opposite direction to one another.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a GaAs MESFET and a Si MOSFET for high frequency and high output.

[0002]

2. Description of the Related Art A conventional high-power GaAs MESFET having a unit gate width of 200 μm and a total gate width of 800 μm will be described with reference to FIG.

That is, in this GaAs MESFET, gate finger electrodes 6, 7, 8 and 9 having a gate width of 200 μm are sequentially arranged in the X direction on the operating layer 10 of the semiconductor substrate. A drain finger electrode 1 and a source finger electrode 4 are formed on both sides of the gate finger electrode 6, and a source finger electrode 4 and a drain finger electrode 2 are formed on both sides of the gate finger electrode 7.
, The drain finger electrode 2 and the source finger electrode 5 are formed on both sides of the gate finger electrode 8, and the source finger electrode 5 and the drain finger electrode 3 are formed on both sides of the gate finger electrode 9. Further, a drain pad electrode 11 connected to the drain finger electrodes 1, 2 and 3 is formed on one side of the operating layer 10 in the Y direction, and source finger electrodes 4, 5 are connected to the other side of the operating layer 10 in the Y direction. The source pad electrode 12 and the gate pad electrode 13 in which the gate finger electrodes 6, 7, 8, 9 are connected to the central portion of the source pad electrode 12.
Were formed respectively.

[0004]

However, in the above-mentioned conventional GaAs MESFET, since the elements are arranged in a concentrated manner, the thermal resistance increases and the cooling efficiency decreases, so that the characteristics and reliability of the element decrease. There was a problem.

The object of the present invention is to solve the above-mentioned problems.
The present invention provides a field effect transistor in which operating layers are arranged in a distributed manner and the thermal resistance of the device is reduced.

[0006]

In order to achieve the above-mentioned object, the present invention has a plurality of gate finger electrodes arrayed on an operating layer of a semiconductor substrate, and a source finger electrode and a drain finger electrode are formed on both sides of the gate finger electrode. In a field effect transistor having electrodes, the operation layer is dispersedly formed and the plurality of gate finger electrodes are alternately formed in opposite directions.

[0007]

In the present invention, since the operating layers are dispersed and arranged, the thermal resistance of the device is lowered.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the field effect transistor of the present invention will be described with reference to FIG. That is, the operating layer 1 is located at a position where both sides of the operating layer 10a of the semiconductor substrate are folded back in the Y direction.
0b and 10c are formed respectively. Gate finger electrodes 7 and 8 having a gate width of 200 μm are arranged in the X direction on the operation layer 10a, and source and drain finger electrodes 4 and 2 are formed on both sides of the gate finger electrode 7. A drain finger electrode 2 and a source finger electrode 5 are formed on both sides of the finger electrode 8. A gate finger electrode 6 having a gate width of 200 μm is formed on the operating layer 10b of the semiconductor substrate, and a source finger electrode 15 and a drain finger electrode 1 are formed on both sides of the gate finger electrode 6. Further, a gate finger electrode 9 having a gate width of 200 μm is formed on the operating layer 10c of the semiconductor substrate, and drain finger electrodes 3 and source finger electrodes 14 are formed on both sides of the gate finger electrode 9. Then, the operation layer 10
The drain pad electrode 11 to which the drain finger electrodes 1, 2 and 3 are connected is formed between b and 10c.
Source finger electrodes 4, 5, 14, 15 around 0a
Is formed, and the gate pad electrode 13 to which the gate finger electrodes 6, 7, 8 and 9 are connected is formed at approximately the center of the drain pad electrode 11.

As described above, in this embodiment, the operation layer 10 is used.
Since a, 10b, and 10c are formed in a dispersed manner, the thermal resistance of the element is reduced and the cooling efficiency is improved.

Needless to say, the present embodiment is not limited to GaAs MESFETs and can be applied to Si MOSFETs and the like.

[0011]

As described above, according to the present invention, since the operating layers are dispersedly formed, the thermal resistance of the element is lowered and the cooling efficiency is improved. Therefore, the characteristics and reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a field effect transistor of the present invention.

FIG. 2 is a plan view of a conventional field effect transistor.

[Explanation of symbols]

 1, 2, 3 Drain finger electrodes 4, 5, 14, 15 Source finger electrodes 6, 7, 8, 9 Gate finger electrodes 10a, 10b, 10c Operating layer 11 Drain pad electrode 12 Source pad electrode 13 Gate pad electrode

Claims (1)

[Claims] 1. A field effect transistor having a plurality of gate finger electrodes arrayed and formed on an operating layer of a semiconductor substrate, and a source finger electrode and a drain finger electrode formed on both sides of the gate finger electrode. A field effect transistor, wherein the plurality of gate finger electrodes are formed alternately in opposite directions.