JPH05204744A - Two-dimensionally arranged data access device - Google Patents

Abstract

PURPOSE:To realize the more compact two-dimensionally arranged data access device without lowering high-speed rotation. CONSTITUTION:This device is composed of plural memory units 20, a address translater 21 to generate addresses mutually different and a common address for all respective memory units, a rotary unit 10 equipped with a function to rotate arranged data for the unit of a block by 90 deg. while enabling mutual access between the memory units, and a means to transfer the arranged data of the unit of the block held in the respective rotary units to the memory unit different from an access source. Thus, assuming that the rotation by 90 deg. is parallelly executed for the unit of the block, the rearrangement of data and the address translation of the unit memory can be wholly executed for the unit of the block. Therefore, two-dimensional access is realized for the unit of 90 deg. rotation, data arranged in the shape of laterally long slips (corresponding to rows) or data arranged in the shape of longitudinally long slips (corresponding to columns).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional array data access device required for realizing a high-speed, compact and economical image processing device, pattern recognition device and the like.

[0002]

2. Description of the Related Art In image processing, pattern recognition, matrix calculation, etc., it is often necessary to access not only row units but also column units for two-dimensional array data. Therefore, in order to improve the performance of a processor aiming at application to these fields, a row and column bidirectional access function, or a row for accessing a column as a row (or a row as a column),
It can be said that conversion between columns, that is, speeding up rotation of two-dimensional array data by 90 degrees is essential. Conventionally, a two-dimensional access memory has been used as a two-dimensional access mechanism (reference: Motooka et al. "Associative processing system using two-dimensional memory", IEICE Tech.
76-80) is known. Further, as a high-speed 90-degree rotation mechanism, a direct function having a function of sequentially outputting the two-dimensional array data sequentially input in the row unit in the column unit (or a function of outputting the two-dimensional data input in the column unit in the row unit) is provided. A parallel conversion type rotator (reference: Japanese Patent Application No. 57-121753) is used. These will be described below, which are closely related to the present invention.

First, the two-dimensional access memory will be described. FIG. 20 is a block diagram of the two-dimensional access memory. In this two-dimensional access memory, the arrangement of element data of each memory unit 20 is appropriately replaced by the data rearrangement network 5, and the address of each memory is appropriately converted by the address converter (ADC) 21. A column or row can be accessed in one machine cycle. The operation will be described below with reference to a two-dimensional access memory in which the address converter 21 is an addition type and the data rearrangement network 5 is a barrel shifter.
When a row or column is accessed from the two-dimensional array data (D _{00 to} D ₇₇ ) that is stored by shifting one element for each row as shown in, (element-wise skewed array [Skewed Array] method) Will be described.

As is apparent from the arrangement of the two-dimensional array data in FIG. 20, if a common address AD is given to the entire array of each memory unit (MU) 20 without conversion, (AD + 1) rows from the top in the memory unit. If the address converter 21 is operated as an adder so that the row data of the eye can be accessed and the address (AD + i) goes to the i-th memory unit 20, one of the diagonally downward-sloping rows in FIG. That is, it can be seen that the (9-AD) th column can be accessed. However, since the data accessed as it is is in a cyclically shifted form, it is necessary to restore it to a normal form in the data rearrangement network 5. Here, the 9th and subsequent columns mean the remaining columns divided by 8. It should be noted that thick chain lines in FIG. 20 indicate signal lines of a common address and individual addresses, respectively.

Next, a 90-degree rotating mechanism using a serial-parallel conversion type rotator will be described. FIG. 21 shows an example of the rotating mechanism. The memory 2, which is a storage unit for the two-dimensional array data, has an access width of W, and the size, which is a unit for converting rows and columns of the two-dimensional array data, is W × W. The serial-parallel conversion type rotator 1 and the like. The operation of rotating by 90 degrees is such that the W × W two-dimensional array data is read from the memory 2 in units of W width rows, and is sequentially input to the rotator 1 as columns from the left side. Is sequentially taken out in units of W width lines and written in the memory 2. Reference numeral 19 in the figure indicates a path between the memory and the rotator.

As is apparent from this operation, W × W 2
The required machine cycle number S _W for rotation of the dimensional array data is
In the W machine cycle for reading from the memory to the rotator and in the W machine cycle for writing from the rotator to the memory, S _W = 2W (1). However, it is assumed that the memory access for each W width row and the input / output to / from the rotator 1 can be realized in one machine cycle. As a result, when the large-scale two-dimensional array data of A × A (A is an integer multiple of W) stored in the memory 2 is realized by repeating the rotation in W × W units, the entire required machine cycle The number S _T is S _T = (A ² / W ² ) × 2W = 2A ² / W (2), and it can be seen that the processing speed of rotation is proportional to W.

[0007]

However, all of these have a drawback that the hardware scale is remarkably increased when the access width of a column or a row is widened to increase the speed. For example, in the two-dimensional access memory, as is apparent from the block configuration shown in FIG. 20, in addition to having to have the memory unit 20 and the address converter 21 corresponding to each row or column element, the data rearrangement network 5, a barrel shifter, a shuffle network, etc., whose hardware scale increases at a rate larger than that of the row or column access width, are required. Also,
As is clear from FIG. 21, the 90-degree rotation mechanism using the serial / parallel conversion type rotator 1 has an access width W of a row or a column.
The hardware scale increases significantly in proportion to the square of.

In view of the above points, the present invention has been made to solve the above problems, and an object thereof is to reduce the size and cost of an apparatus that processes two-dimensional array data such as images and patterns at high speed. In order to realize the above, it is an object of the present invention to provide a two-dimensional array data access device capable of realizing a more compact hardware scale without lowering the rotation speed.

[0009]

In order to achieve the above object, the present invention does not perform data rearrangement and memory unit address conversion in element units as in a conventional two-dimensional access memory. 90 degree rotation or horizontally long strip-shaped array data (corresponding to rows) by rearranging data and converting memory unit addresses in block units, assuming parallel execution of 90-degree rotation in block units , Vertical strip array data (corresponding to columns)
Realizes two-dimensional access in units of.

Specifically, an array of memory units that can access an address that is common to the whole and addresses that are different from each other, and array data in block units accessed from each of the memory units can be simultaneously rotated 90 degrees. A two-dimensional array data access device is configured by an array of degree rotation units and means for transferring the block-unit array data held by each rotation unit to a memory unit different from the access source.

[0011]

In the present invention, each 90-degree rotating unit is
Predetermined for each corresponding memory unit (determined by whether to rotate two-dimensional array data or to access vertically and horizontally elongated strip array data. This may be common to the entire array or may be different for each memory unit). The array data in block units is read from the address, the array data in each block unit is subsequently rotated in parallel by 90 ° in a 90 ° rotation unit array, if necessary, and the array data in each block unit is further transferred. Also, the two-dimensional array data is rotated by 90 degrees by writing to different addresses of a predetermined memory unit via
It is possible to access the horizontally long strip-shaped array data and the vertically long strip-shaped array data with respect to the dimensional array data. As a result, the hardware scale can be reduced by simplifying the data rearranging network and reducing the address translator without reducing the rotation processing speed.

[0012]

【Example】

Embodiment 1 FIG. 1 is a first embodiment of the present invention. This embodiment, as shown in FIG. 1, includes rotating units (RU _{1 to} RU ₄ ) 10,
Selector (SEL _{1 to} SEL ₄ ) 12, access width is W /
N (N = 4 in this embodiment) memory units (MU ₁ to
MU ₄ ) 20, address converter (ADC _{1 to} ADC ₄ ) 2
It is composed of a one-dimensional array such as 1 and a control unit 30.
Here, reference numeral 19 is a path between each memory unit and a rotary unit, a thick solid line is a data transfer signal line with an access width of W / 4, and a thick broken line is a common control for controlling read, write, transfer, etc. Signal lines, thin broken lines are individual control signal lines,
The thick one-dot chain line is an address signal line.

Further, FIG. 2 shows a rotary unit (RU ₁ -R).
U ₄ ) 10 of the memory circuit (MC) 13
2), an input bus 14 provided in a row unit, an output bus 15, an output bus 16 provided in a column unit, a selector (SEL) 17, and the like. The path to the memory unit array or the rotation unit array for externally accessing the two-dimensional array data access device of this embodiment is not shown for simplicity. Hereinafter, the case where the two-dimensional array data shown in FIG. 3 is rotated by 90 degrees according to the present embodiment will be described.

The two-dimensional array data to be rotated in FIG. 3 is composed of array data A to P in block units,
In the arrangement of the memory units 20, as shown in FIG.
From the first row of E, I, M to the last row of D, H, L, P, AD0- (AD0 +) of the array of the memory unit 20 is displayed.
It is assumed to be stored in the address W-1). By processing the two-dimensional array data in the following procedure, the two-dimensional array data after rotation is sequentially formed in the storage areas of the lower addresses AD1 to (AD1 + W-1), so that the 90-degree rotation can be performed. To be realized.

Step 1 The array data for each block unit of A, H, K and N is shown in FIG.
Rotating unit 1 while rotating 90 degrees as shown in
Read to array 0. This process is performed by each memory unit 2
Data is sequentially read from 0 in units of W / 4 width rows by sequentially writing data from the rightmost column to the left side in each rotary unit 10. At this time, the addresses given to the memory unit (MU) 20 are AD0 to AD0 sequentially generated by the control unit 30.
The address ADD of (AD0 + W / 4-1) is further converted by the address converter 21 into the i-th memory unit M from the left.
Address ADD _i for U _i is generated by converting so that _{ADD i = AD0 + mod ((} ADD-AD0 + W- (i-1) W / 4) / W) ····· (3). Further, the selector (SEL) 17 in the rotary unit 10 is set so that the input from the memory unit 20 is selected. Further, the writing to each rotary unit 10 sequentially activates the writing from the input bus 14 in the row direction to the memory circuit (MC) 13 of the two-dimensional array from the rightmost column to the leftmost column in column units. Do that.

Step 2 The array data in block units in the rotation unit (RU) 10 is shifted to the left by one rotation unit as shown in FIG. This is the i-th selector 12 or SEL
_i is set so that the input from the (i + 1) th rotation unit RU _{i + 1} is selected, and the selector 17 in each rotation unit 10 is set so that the input from the selector 12, that is, SEL _i is selected. The output of the memory circuit (MC) 13 in the unit 10 to the row direction bus 15 and the input from the row direction bus 14 (writing from the bus 14 to the memory circuit 13) are sequentially activated in each memory circuit 13 in units of columns. By converting.

Step 3 A, H, K, N block unit array data in each rotary unit 10 is stored in the memory unit 20 as shown in FIG.
Write to the storage area after rotation. In this process, the output of the memory circuit 13 to the column-direction bus 16 toward the memory unit 20 in the rotation unit 10 is sequentially activated row by row from the upper side to the lower side, and the data read by this is activated. It writes by sequentially writing in. At this time, the address given to the memory unit (MU) 20 is the address ADD of AD1 to (AD1 + W / 4-1) sequentially generated by the control unit 30, as in step 1.
Further the address converter 21 converts such that the address ADD _i for the i-th memory units MU _i from the left _{ADD i = AD1 + mod ((} ADD-AD1 + i × W / 4) / W) ··· (4) To generate.

In the series of cycles from step 1 to step 3 described above, the address ADD generated from the control unit 30 is increased by W / 4 each time the next cycle is entered, and the shift amount to the left in step 2 is increased. , By switching the selector setting of the selector 12 and increasing the rotation unit by one unit, and further repeating three times, {B, E, L, O}, {C, F, I, P}, {D ，
Each set of block data of G, J, M} is sequentially converted, and as shown in FIG.
A 0 degree rotation result is obtained.

Next, the two-dimensional access in units of vertically long strip-shaped array data and horizontally long strip-shaped array data according to this embodiment will be described. The two-dimensional array data to be accessed (identical to that shown in FIG. 3) is
As shown in FIG. 9, the two-dimensional array data is (W / 4) × (W
It is assumed that the data is stored in the skewed array format with the block of / 4) as a unit.

As can be easily understood from FIG. 9, the horizontally long strip-shaped array data corresponding to the rows of the conventional two-dimensional access memory is the address common to the whole generated by the control unit 30, and is directly stored in the rotary unit 10. By reading out (see FIG. 10) and then shifting by a predetermined amount between the rotating units 10, it is possible to read out on the array of the rotating units 10 (see FIG. 11). If row-wise data is required, the corresponding row of each rotary unit 10 may be activated and read out via the bus in the column direction. Writing is performed in reverse, by shifting the target horizontally long strip-shaped array data between the rotation units 10 by a predetermined amount, and then writing the same in the memory unit 20 at a common address generated by the control unit 30.

On the other hand, the reading of the vertically long strip-shaped array data corresponding to the column is performed by individually converting the common address by the address converter 21 and reading it to the rotating unit 10 while rotating. Specifically, as in the case of the above 90-degree rotation, first, the address ADD _i ADD generated by converting the common address ADD of AD0 to (AD0 + W-1) supplied from the control unit 30 by the address converter 21. _i = AD0 + mod (ADD-AD0 + W- (i-1) W / 4) / W) (5), the (W / 4) width row unit data sequentially read from each memory unit 20 is read. , Are sequentially stored as columns of the rotation unit 10 from the right side (see FIG. 12).

Subsequently, by shifting the data on the array of the rotary units 10 by a predetermined number of the rotary units 10, it is possible to obtain the desired vertically elongated strip-shaped array data on the rotary unit array (FIG. 13). reference). Writing can be realized by completely reversing the reading procedure. However, the process of writing while rotating the memory unit 20, which is required in this case, is a W / 4 read by activating the output to the row direction bus 15 of the memory circuit 13 in the rotation unit 10 in column units. The width data is transferred by transferring the data from the left side to the memory unit 20 via the path 19.

Second Embodiment Next, a second embodiment of the present invention in which the rotary unit 10 is composed of a two-dimensional shift register will be described. The configuration of the second embodiment differs from the first embodiment only in the rotating unit 11. Therefore, in FIG. 14, the second
The structure of the rotation unit 11 of the said Example is shown. The difference from the rotating unit 10 of the first embodiment is that each memory circuit (MC) 13 is adjacent to a memory circuit 13 instead of the bus.
This is to provide shift transfer paths from left to right and from bottom to top.

Regarding the operation, instead of performing the reading and writing of the rotary unit 11 by activating the memory circuits 13 in units of columns or rows, the held data or the input data is sequentially shifted between the memory circuits 13 in the upward or rightward direction. This is the only difference from the first embodiment. The advantage of configuring the rotation unit 11 in the shift register format as in the second embodiment is that the activation control in column units or in row units is not necessary and the control is simplified accordingly.

Embodiment 3 FIG. 15 shows a third embodiment of the present invention. This example
This is configured by omitting the selector 12 of the first and second embodiments and connecting the rotary unit 10 in a ring shape. The operation of this embodiment is different from that of the first and second embodiments in that the shift between the rotation units of the block-unit array data in step 2 is all performed by the right unit shift. Therefore, when the shift amount is large, it is necessary to repeat the unit shift, and there is a drawback that the total rotation time increases. However, since the selector 12 is unnecessary, the hardware scale is reduced, and the memory unit (MU _i )
When the 20, rotation unit (RU _i ) 10, address converter (ADC _i ) 21 and the like are configured as one module, the number of connection lines between the modules is reduced to 1 / N (four in this embodiment). There are advantages. This advantage is extremely effective when an LSI or a board having a severe restriction on the number of terminals is used as a module.

When the array data in block units is shifted only by unit shift, as can be easily understood,
By making the shift directions bidirectional, the total shift amount can be halved. Although not described with reference to the drawings, data can be accessed through a bidirectional path between the rotation unit 10 and the memory unit 20, which are constituent units of modules adjacent to each other, so that rotation and unit can be performed. By performing the shifts in parallel, the shift amount can be further reduced.

Embodiment 4 By the way, when the present invention is incorporated into a processor array type parallel processor, the address translator can be constructed more simply by utilizing the arithmetic function of the processing element (PE). FIG. 16 is a fourth embodiment of the present invention based on this concept. Here, the rotation unit (RU _{i to} RU ₄ ) 18 is the rotation unit 1 described above.
As shown in FIG. 17, a column unit bus is provided in the vertical direction of each storage circuit (MC) 13, and a bidirectional shift transfer is provided in the horizontal direction. There is a pass. However, as is apparent from FIG. 17, the rotation unit 18 can be omitted when the processing element has a built-in register for moving data between adjacent processing elements. This is because the function of the rotating unit can be emulated by the arrangement of the data moving registers.

The PE arrays 40 ₁ to 40 ₄ are processor arrays composed of (W / 4) processing elements. The processing element PE _j is connected to the j-th column-direction bus in the rotation unit 18, and the PE arrays 40 ₁ to 40 ₄ can access the data held in each rotation unit 18 in units of rows. Therefore, each column of the rotation unit 18 can function as a local register of the processing element PE to which it is connected via the column bus. In addition, the selectors (SEL _{1 to} SEL ₄ ) 22 are connected to the memory units (M
The address supplied to U _{1 to} MU ₄ ) 20 is set as column unit data output from the rotation unit (RU _{1 to} RU ₄ ) 18 or is an address signal output from the control unit 30 and common to all. It is a selector corresponding to an address converter for selecting either.

The operation of this embodiment is characterized by the data access to the memory unit 20 of the rotating unit 18, and the other operations are the same as those of the above-mentioned first and second embodiments, and therefore the explanation thereof is omitted. That is, this access (reading) is performed in the following procedure. PE array 40 ₁ to be held in advance by each PE
Base address ADb _i (= AD0 + mo for each 40 ₄
d ((W- (i-1) (W / 4)) / W)
Based on the in-array address j−1 of the PE previously held in each PE, ADD _ij (for example, = ADb + (j−
1)) is obtained by each PE, and the result is transferred to the column of the storage circuit (MC) 13 in the rotation unit 18 connected to each PE (see FIG. 18).

The rotation unit 18 sequentially shifts the held data from left to right, and while addressing the memory unit 20 with the output ADD _ij , the data [ADD _ij ] read from the memory unit 20 is simultaneously and sequentially rotated. Input from the left side of 18. On this occasion,
The selector 17 in the rotary unit 18 is selected so that the output ADD _ij from the rotary unit 18 is selected.
So that the input from the memory unit 20 is selected,
Set each separately.

By repeating the above process (W / 4) times, as shown in FIG. 19, the data [ADD _i0 ] to [ADD _{i ((W / 4) -1)} ] in the memory unit 20 are stored. , And is read by the rotation unit 18, and a process equivalent to step 1 of the first embodiment is realized. As described above, in this embodiment, the address translator effectively uses the arithmetic function of the processor and the shift function of the rotary unit to effectively select the selector 22.
Composed of only.

In the writing process to the memory unit 20 in step 3 of the first embodiment, the data in the middle of rotation is temporarily transferred from the rotation unit to the processing element PE, and the address is generated in the same manner as described above. ,
Data is directly transferred from the processing element PE to the memory unit via the column bus. Here, the reason why the data in the middle of rotation is once transferred from the rotation unit to the processing element PE is to free the rotation unit for generation of the address data ADD _ij for the memory unit.

Here, regarding the 90 degree rotation, the hardware scale in the general case where the number of modules of the fourth embodiment, which is the embodiment of the simplest configuration of the present invention, is N,
Evaluate the number of required machine cycles, etc. in comparison with the conventional method. First, we evaluate the hardware scale. As is apparent from the configuration of FIG. 1, the memory portion is only divided into memory units having a width of (W / N), and the address converter is also configured by only the selector. The increase in wear scale is negligible.

On the other hand, with respect to the 90-degree rotator portion, in the present invention, since N rotating units each having a size of (W / N) × (W / N) are formed, a conventional rotating unit is used. If the same one is used, the hardware scale is W ² / N, which is 1 / N as compared with the conventional method W ² . Further, when the processor is incorporated in a processor array type parallel processor as in the case of the fourth embodiment, the arrangement of the rotation units can be emulated by a data transfer register between adjacent processing elements incorporated in each processing element. It can be said that the amount of hardware scale reduction is even greater.

However, the number of machine cycles required is slightly increased. Hereinafter, the required number of machine cycles will be calculated. First, in the process of reading the array data in block units in step 1 to each rotary unit, if both reading from the memory unit and storage in the rotary unit can be executed within the same machine cycle, the required machine cycle number S ₁ Is equal to the number of constituent rows of array data in block units, and S ₁ = W / N (6)

The number S ₂ of machine cycles required for shifting the array data in block units between the rotation units in the subsequent step 2 differs depending on the access position of the array data in block units, but on average S ₂ = (N / 4) × W / N = W / 4 (7) However, this is the value when the shift amount is reduced by the bidirectional shift and the parallel execution of the rotation in step 1 and the reverse shift. Here, N is an even number, and the shift of the data in units of columns between the rotation units can be executed in one machine cycle.

Further, the number S of machine cycles required for the subsequent write processing to each memory unit in step S
₃ is the number of writing from the rotary unit to the memory is 1
If it can be executed in a machine cycle, S ₃ = W / N (8) Therefore, the required number of cycles S _T for rotating the entire two-dimensional array data of W rows × W columns by 90 degrees is: S _T = N × (S ₁ + S ₂ + S ₃ ) = 2W + (N × W / 4) (9)

The total number of required machine cycles S _T
In comparison with the conventional 90 ° rotator of W × W, the amount due to the shift of the array data in block units between the rotation units in step 2 of the second term is increased. However, in terms of the hardware scale, that is, the performance / cost of the rotor part considering the cost, the hardware scale of the rotor is 1 / N.
It is considerably improved because it is reduced to. For example, N
= 8, the performance / cost is 4 compared with
It doubles.

On the other hand, the comparison and evaluation with the conventional device as the two-dimensional access memory of the present invention is slightly deteriorated in that the two-dimensional access of the present invention is realized for strip-shaped two-dimensional array data. Since it is difficult to quantify it, I will omit it. However, when it is incorporated in a processor array type parallel processor, the address converter is effectively unnecessary, and the arrangement of the rotation unit can be configured by diverting the data movement register in the processing element. Since it is possible to realize a function close to that of the conventional two-dimensional access without increasing the hardware scale of the processor, it is considered that the parallel processor that requires the two-dimensional access can greatly contribute to the downsizing and the economical efficiency.

In the above description, the unit such as the memory access width and the size of the column / row conversion type rotation unit is not mentioned, but this is determined by the word length of the element of the two-dimensional array data. That is, if the word length of the element of the two-dimensional array data is 1 bit (binary data), the unit is bit (in this case, for example, the width W means that the width is W bits). If the word length of the element is w, the unit is w bits multiplied by w (in this case, for example, if the width is W,
The width is (W × w) bits. ). Also, when the block unit array data read from each unit is rotated by the rotation unit, the rotation direction is +90 degrees, −.
It may be any of 90 degrees, and an odd multiple of 90 degrees is possible.

[0041]

As described above, according to the present invention, an array of memory units that can access an address common to the whole and addresses different from each other and array data in block units accessed from each memory unit can be simultaneously used.
By constructing an array of 90-degree rotating units that can be rotated by 0 degree and a unit that transfers the array data in block units held by each rotating unit to a memory unit different from the access source, the conventional arrangement can be achieved. Alternatively, the hardware scale of the rotator can be greatly reduced without lowering the rotation speed of the two-dimensional data access device that is scaled up in proportion to the column access width or proportional to the square. Further, it is possible to provide a function close to that of the conventional two-dimensional access memory. Further, since the constituent units such as the memory unit and the rotating unit can be configured by the regular arrangement of the same module, there is also an advantage that the memory access width can be easily expanded to improve the speed. Therefore, if the present invention is applied to an image processing device, a pattern recognition device, or the like that frequently uses 90-degree rotation of two-dimensional array data, the speed and size are reduced.
It is possible to achieve both economic efficiency.

Further, the present invention can be easily incorporated in a processor array type parallel processor in which a processing element has a register for moving data between adjacent processing elements. This is because the two-dimensional array data access device of the present invention can be realized by adding a small amount of hardware such as a selector by diverting the arrangement of registers for moving data to the rotation unit. Therefore, the present invention is extremely useful as a technology for miniaturizing a general-purpose processor array parallel processor that executes two-dimensional access and 90-degree rotation at high speed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a rotating unit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing rotated image data.

FIG. 4 is a diagram illustrating a rotation process according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a rotation process according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a rotation process according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a rotation process according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a rotation process according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating two-dimensional access according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating two-dimensional access according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating two-dimensional access according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating two-dimensional access according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating two-dimensional access according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a rotary unit according to a second embodiment of the present invention.

FIG. 15 is a block configuration diagram of a third embodiment of the present invention.

FIG. 16 is a block configuration diagram of a fourth embodiment of the present invention incorporated in a processor array type parallel processor.

FIG. 17 is a diagram showing a configuration of a rotating unit according to a fourth embodiment of the present invention.

FIG. 18 is a diagram for explaining reading from the memory unit to the rotary unit according to the fourth embodiment of the present invention.

FIG. 19 is a diagram for explaining reading from the memory unit to the rotary unit according to the fourth embodiment of the present invention.

FIG. 20 is a configuration diagram of a conventional two-dimensional access memory.

FIG. 21 is a diagram illustrating a 90-degree rotation mechanism using a conventional serial-parallel conversion type rotator.

[Explanation of symbols]

 10, 11, 15, 18 Rotating unit (RU) 12, 17, 22 Selector (SEL) 13 Storage circuit (MC) 14 Row direction input bus 15 Row direction input bus 16 Column direction input bus 19 Memory unit, rotation unit path 20 memory unit (MU) 21 address converter (ADC) 30 control unit 40 processing element array (PE array)

Claims (4)

[Claims] 1. A plurality of memory units having both a function of accessing a common address as a whole and a function of accessing a different address for each unit, and array data in block units read from each of the memory units at 90 degrees at the same time. A two-dimensional array data access device having a rotating means and a means for transferring the array data in block units to a memory unit different from the memory unit of the access source. 2. The two-dimensional array data access device according to claim 1, wherein as means for rotating by 90 degrees, from a two-dimensional array of storage circuits that can be accessed in either column units or row units from array data in block units. A two-dimensional array data access device using a rotating unit. 3. The two-dimensional array data access device according to claim 1, wherein the individual address signal for each memory unit is read from the memory unit by the rotating means of the two-dimensional array data accessed from the memory unit. A two-dimensional array data access device, which is generated at the same time from the data output from the rotating means. 4. The two-dimensional array data access device according to claim 2, wherein the rotation data composed of a two-dimensional array of storage circuits is provided as means for transferring array data in block units to a memory unit different from the memory unit of the access source. A two-dimensional array data access device comprising units connected in a ring shape.