JPH04346262A - Compound semiconductor element - Google Patents

Abstract

PURPOSE:To reduce the heat resistance of a bipolar transistor by a method wherein a field-effect transistor is formed on the surface of a semiinsulating compound semiconductor substrate, the bipolar transistor is formed on the rear and a heat sink is connected to the rear of the substrate. CONSTITUTION:A secondary-electron gas FET which is composed of an undoped GaAs channel layer 2, an electron supply layer 3, a gate electrode 8, a source electrode 9 and a drain electrode 10 is formed on the surface of a semiinsulating GaAs substrate. An HBT which is constituted of an emitter electrode 11 composed of AuGe-Ni, a collector layer 13 composed of AuGe-Ni and a base electrode 12 composed of AlMn-Ni is formed on the rear of the substrate 1. A grounding metal 16 and the emitter electrode 11 which have been formed on the rear of the semiinsulating GaAs substrate 1 are connected to a grounding metal block 18 which is used also as a heat sink. Thereby, the operating-layer temperature of a bipolar transistor can be lowered.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to compound semiconductor devices.

0002

2. Description of the Related Art Active elements using compound semiconductors can be roughly divided into two types: field-effect transistor (FET)-based devices and bipolar transistor-based devices.

A typical example of an FET is a two-dimensional electron gas FET, and a typical example of a bipolar transistor is a heterojunction bipolar transistor (hereinafter referred to as HBT).

Generally, FET devices have low power consumption, high speed, and low RF noise characteristics, but have the drawbacks of low current drive capability and high 1/f noise.

On the other hand, bipolar devices have high speed, high current drive capability, and low 1/f noise characteristics, but have the disadvantage of high power consumption.

Therefore, research and development efforts are underway to integrate FET-based devices and bipolar-based devices on the same semiconductor chip, and to maximize the advantages of both while compensating for each other's weaknesses.

[0007] In the field of silicon LSI, Bi-CMOS
This corresponds to this, but in the field of compound semiconductor devices, FET-based devices are often used in low-noise, small-signal amplification sections, and bipolar-based devices are often used in high-output amplifiers and local oscillation sections.

AlGaAs/GaAsH according to the prior art
BT and AlGaAs/GaAs two-dimensional electron gas FE
The hybrid integrated circuit of T will be explained with reference to FIG.

A semi-insulating GaAs substrate 1 is formed by MOCVD.
N+ type G selectively epitaxially grown on the upper part
aAs sub-collector layer 4a, N-type GaAs collector layer 5
, P+ type GaAs base layer 6, N type AlGaAs emitter layer 3a, N+ type GaAs emitter cap layer 4b.
are layered. On top of that, an emitter electrode 11 made of AuGe-Ni and a base electrode 1 made of AuMn-Ni.
2 and a collector electrode 13 made of AuGe-Ni are formed to constitute an HBT.

Furthermore, a non-doped GaAs channel layer 2 and an N-type AlGaAs electron supply layer 3, which are selectively epitaxially grown on other parts of the GaAs substrate 1 by MOCVD, are laminated. A gate electrode 8 made of Al, a source electrode 9 and a drain electrode 10 made of AuGe-Ni are formed thereon.

[0011]

[Problem to be solved by the invention] In the conventional example, HBT
The power consumption of PHBT is two-dimensional electron gas FE with the same planar area.
The power consumption is approximately 5 times larger than that of a T-type PFET. H.B.
If the temperature of the operating part of T is TCH and the thermal resistance is RT, the temperature increase is ΔT = TCH - T0 = RT PHBT
(1). In equation (1), T0 is the temperature of the back surface of the chip.

On the other hand, if the temperature of the operating part of the two-dimensional electron gas FET is TCF, ΔT becomes ΔT=TCF−T0=RT PFET (2). From equations (1) and (2), the temperature difference between the back surface of the chip and the operating part is 5
It will be about twice as big. Normal T0 = 50℃, TCF = 80
℃, and TCH can be as high as 200℃.

[0013] Since the reliability of a transistor deteriorates exponentially as the temperature of the operating part increases, the conventional example had the disadvantage that the reliability of an HBT was much worse than that of a two-dimensional electron gas FET. .

[0014] The purpose of the present invention is to solve such problems,
An object of the present invention is to provide a FET/bipolar hybrid integrated circuit that maintains the reliability of HBT.

[0015]

In the compound semiconductor device of the present invention, a field effect transistor is formed on the front surface of a semi-insulating compound semiconductor substrate, and a bipolar transistor is formed on the back surface of the substrate. Further, a heat sink is connected to the back surface of the semi-insulating compound semiconductor substrate. Further, the circuit formed on the front surface of the semi-insulating compound semiconductor substrate and the circuit formed on the back surface of the substrate are electrically connected by at least one of a via hole circuit and a capacitive coupling circuit. . Further, a two-dimensional electron gas transistor is used as the field effect transistor,
A heterojunction bipolar transistor is used as the bipolar transistor.

[0016]

[Operation] A field effect transistor with low power consumption is formed on the front surface of the chip, and a bipolar transistor with high power consumption is formed on the back surface of the chip to keep the operating layer temperature of the bipolar transistor low.

As a result, the chip area can be reduced while maintaining high reliability of the bipolar transistor. The degree of integration of a hybrid integrated circuit consisting of bipolar transistors and field effect transistors can be increased.

[0018]

Embodiment A first embodiment of the present invention will be described with reference to FIG.

A layer 2 consisting of a non-doped GaAs channel layer 2, an N-type AlGaAs electron supply layer 3, a gate electrode 8 made of Al, a source electrode 9 made of AlGe-Ni, and a drain electrode 10 is formed on the surface of the semi-insulating GaAs substrate 1. A dimensional electron gas FET is formed.

[0020] On the back surface of this substrate 1, an N+ type GaAs
Sub-collector layer 4a, N-type GaAs collector layer 5, P+
A GaAs base layer 6, an N-type AlGaAs emitter layer 3a, and an N+-type GaAs emitter cap layer 4b are stacked. On top of that, an emitter electrode 11 made of AuGe-Ni, a collector electrode 13 made of AuGe-Ni,
An HBT is formed with a base electrode 12 made of AlMn-Ni. The periphery thereof is insulated by a proton ion implantation layer 7, and a ground metal 16 is further formed.

Next, regarding the implementation method of the first embodiment,
This will be explained with reference to FIG.

The ground metal 16 and emitter electrode 11 formed on the back surface of the semi-insulating GaAs substrate 1 are connected to a ground metal block 18 which also serves as a heat sink.

Next, a second embodiment of the present invention will be explained with reference to FIG.

This describes a method of electrically connecting a circuit formed on the front surface of the semi-insulating GaAs substrate 1 and a circuit formed on the back surface.

The electrode 15a formed on the front surface is connected through the via hole circuit 14 to the electrode 15b formed on the back surface. Further, the electrode 15c formed on the front surface is coupled to the electrode 15d formed on the back surface by capacitance. Further, a ground metal block 16 and an emitter electrode 11 formed on the back surface are connected to a ground metal block 1 that also serves as a heat sink.
8 is connected.

In the above embodiments, a GaAs substrate was used as the compound semiconductor substrate, but other compound semiconductor materials such as InP using an InAlAs/InGaAs heterojunction system can also be used. Further, the effects of the present invention can be obtained without limiting the degree of integration of elements to two or three elements.

[0027]

Effects of the Invention: Since the bipolar transistor, which consumes a large amount of power, is formed on the back side of the chip and brought into direct contact with the heat sink, the thermal resistance of the bipolar transistor is significantly reduced, and ΔT is significantly reduced from the conventional 150°C to the present invention's 10°C. Improved.

On the other hand, since the FET with low power consumption is formed on the chip surface, the high reliability of the bipolar transistor can be maintained and the degree of integration of the hybrid integrated circuit consisting of the bipolar transistor and the FET can be increased.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing the mounting method of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second embodiment of the invention.

FIG. 4 is a cross-sectional view showing a compound semiconductor device according to the prior art.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 Non-doped GaAs layers 3, 3a N-type AlGaAs layers 4, 4a, 4b N+-type GaAs layer 5
N-type GaAs layer 6 P+-type GaAs layer 7 Proton ion implantation layer 8 Gate electrode 9 Source electrode 10 Drain electrode 11 Emitter electrode 12 Base electrode 13 Collector electrode 14 Via hole circuit 15, 15a, 15b, 15c, 15d Electrode 1
6 Ground metal 17, 17a, 17b, 17c Electrode 18
metal block

Claims (4)

[Claims] 1. A compound semiconductor device in which a field effect transistor is formed on the front surface of a semi-insulating compound semiconductor substrate, and a bipolar transistor is formed on the back surface of the substrate. 2. The semiconductor device according to claim 1, wherein a heat sink is connected to the back surface of the semi-insulating compound semiconductor substrate. 3. A circuit formed on the front surface of a semi-insulating compound semiconductor substrate and a circuit formed on the back surface of the substrate are electrically connected by at least one of a via hole circuit and a capacitive coupling circuit. 2. The compound semiconductor device according to claim 1, wherein: 4. The compound semiconductor device according to claim 1, wherein a two-dimensional electron gas transistor is used as the field effect transistor, and a heterojunction bipolar transistor is used as the bipolar transistor.