JPH03138984A - Dual gate fet - Google Patents

Abstract

PURPOSE:To improve power gain, noise figure and cross modulation characteristic by so setting the ratio of a first resistance to a second resistance that the voltage of a connecting point for applying a fixed bias becomes equal to the threshold voltage of a second gate. CONSTITUTION:A first resistor 11 and a second resistor 12 are connected between a drain electrode 7b and a source electrode 7a, and the ratio of the resistance 11 to the resistance 12 is so set as to apply a voltage equal to a threshold value from the connecting point to a second gate 9b through a third resistor 13. Thus, a large power gain in high frequency and low noise figure are obtained. And, since it is used in a range of a good linearity, it has an excellent cross modulation characteristic, and a stable operation can be realized by a dump resistor 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a dual gate FET that is used in high frequency amplification, etc. and has excellent power gain and noise figure, and is used with the second gate voltage fixed. It is something.

[Summary of the invention]

Dual gate FE with fixed voltage of second gate
At T, a voltage equal to the threshold voltage of the second gate is extracted from a first resistor and a second resistor connected in series between the drain electrode and the source electrode, and is applied to the second gate through a dump resistor. This is a dual gate FET set to apply a fixed bias to. If the voltage of the second gate is made equal to the threshold voltage, the power gain, noise figure, and cross-modulation characteristics are excellent, and the stability of amplification etc. can be improved by using the dump resistor.

[Conventional technology]

Dual gate FETs include 4-pole MO3FETs, 4-pole junction FETs, and 4-pole shot key gate FETs. Since it is a dual gate, the mirror effect can be reduced, resulting in excellent high frequency characteristics. Four-pole Schottky gate FETs are used to obtain particularly high power gain and noise figure.

This 4-pole shot key gate FET (hereinafter referred to as 4-pole MESF)
ET), as shown in FIG. 7, an active layer 3, a source region 5a, and a drain region 5b are formed on the surface of a semi-insulating semiconductor substrate 1 made of GaAs or the like using an insulating film 2 such as a nitride film. After forming by ion implantation etc., for example, AI
A Schottky barrier is formed by a Schottky metal 8 such as, and a first gate metal 9a and a second gate metal 9b are further formed. After an ohmic metal 6 is deposited on the source and drain regions, a source electrode 7a and a drain electrode 7b are formed.

When a predetermined voltage is applied between the drain electrode and the source electrode of the dual gate FET thus formed and an input signal is applied to the first gate electrode to operate the dual gate FET, each region of the active layer 3 shown in FIG. A depletion layer 4 is generated depending on the gate voltage, and the current can be controlled. When the drain voltage is set to 0, the gate voltage when the extension of the depletion layer becomes equal to the thickness of the active layer is the threshold voltage, so if the active layer is thin, it is a depletion type, and if it is thick, it is an enhancement type. Easy to form.

On the other hand, if the second gate electrode is grounded or a fixed bias is applied, the Miller effect is small and the power gain and noise figure are excellent. It is often used in a grounded state. As shown in the circuit diagram of the conventional 4-pole MESFET shown in FIG. 8, when the source electrode 7a is grounded, the drain voltage is applied to the drain electrode 7b, and the input signal is applied to the first gate electrode 9a, when the transistor is operated,
There is a device in which an optimum operating voltage is applied to the second gate electrode 9b via a bias resistor 10 (Japanese Patent Laid-Open No. 64-4
Publication No. 9409).

[Problem to be solved by the invention]

When the second gate electrode is grounded, external components such as resistors are not required, but the high frequency characteristics are not sufficiently exhibited. In order to improve the power gain, noise figure, and cross-modulation characteristics, it is necessary to set the bias voltage of the second gate optimally. It was necessary to form it integrally with the FET.

Furthermore, when a bias voltage is applied, it is necessary to eliminate oscillation or instability due to impedance mismatch.

[Means to solve the problem]

In order to solve the above problems, the present invention connects a first resistor and a second resistor between the drain electrode and the source electrode, and connects the connection point to the second gate via the third resistor. Excellent characteristics are achieved by setting the ratio of the first resistance to the second resistance so that a voltage equal to the threshold value is applied.

[Effect]

If the bias voltage of the second gate is too small compared to the threshold voltage, the power gain will be small and the noise figure will be high, and if it is too high than the threshold voltage, the power gain will reach a saturated value. However, the noise figure is bad (and the linearity is bad because it is in the saturation region), so the cross-modulation characteristics are bad. Also, if the third resistor is used as a dump resistor, oscillation and instability can be reduced. can.

〔Example〕

As a representative example of the dual gate FET of the present invention, 4
The polar MESFET will be explained using FIGS. 1 to 6.

First, an equivalent circuit diagram of the 4-pole MESFET of the present invention is shown in FIG. A dual gate FET having a source electrode 7a and a drain electrode 7b, and a first gate electrode 9a and a second gate electrode 9b, in which a voltage equal to a threshold voltage is applied to the second gate electrode 9b. A first resistor R811 and a second resistor R212 are connected in series between the electrode 7b and the source electrode 7a. At this time, the resistance ratio R2/III+R2 makes the threshold voltage VP% and the drain voltage .

When Rt/Rx + Rx0) value is v, /vo
The ratio of R1 and R is set so that it is equal to . Normally, it is desirable to set the values of Rx and R1+ larger than the value of the channel resistance, for example, in the range of several tens of ohms to several kiloohms. A voltage substantially equal to the threshold value is applied from the connection point between the first resistor 11 and the second resistor 12 to the second gate electrode 9b via the third resistor R113.

Next, the structure of the 4-pole MESFET incorporating the above-mentioned resistor will be explained using FIGS. 2 to 4. FIG. 2 shows a plan view of the 4-pole MESFET of the present invention, FIG. 3 shows a cross-sectional view along line AA, and FIG. 4 shows a cross-sectional view along line B-B.

As shown in FIG. 2, the source electrode 7a and the drain electrode 7b are connected to the first gate electrode 9a and the second gate electrode 9.
Patterns arranged on both sides of b are formed on the surface of the semiconductor substrate 1. Figure 3 shows the A-A cross section of the fixed bias resistor part, which is the main part of the present invention, and the B-A cross section of the dump resistor part.
-B sectional view will be explained using FIG.

As shown in FIG. 3, the drain region 5b and the first resistor 1
The regions of the first and second resistors 12 are formed by ion implantation or diffusion, and the ohmic metal 6 of the drain portion and the drain electrode 7b are formed.

The first resistor 11 and the second resistor 12 can be formed at the same time as the active layer region with a lower N- concentration than the source and drain regions. A portion close to the drain is defined as a first resistor 11, and a portion close to the source is defined as a second resistor 12.

Next, as shown in FIG. 4, one end of the third resistor 13 as a dump resistor is connected at a predetermined position between the first resistor 11 and the second resistor 12, and the other end is connected to the second resistor 13. Connected to gate electrode 9b. The connection is preferably made via the ohmic electrode 6.

The high frequency characteristics of the 4-pole MESFET thus formed are shown in FIGS. 5 and 6.

FIG. 5 is a diagram showing the power gain with respect to the first gate voltage using the second gate voltage as a parameter; the higher the second gate voltage is, the larger the power gain is; In this case, the power gain becomes saturated.

FIG. 6 is a diagram showing the noise figure for the first gate voltage using the second gate voltage as a parameter, and shows that the higher the second gate voltage is, the smaller the noise figure tends to be, but when it exceeds the threshold voltage. In the vicinity of 1.5V, the noise figure also becomes saturated.

Since the linearity is not good in the saturated state, the cross modulation characteristics are also poor.

Although the embodiment of the present invention has been described using a 4-pole MESFET, it is also suitable to use a similar structure in a 4-pole MO3FET or a 4-pole junction FET. Further, instead of the diffused resistor, a resistor such as polysilicon may be used for connection.

〔Effect of the invention〕

Dual game) FE such as the 4-pole MESFET of the present invention
If T is used, a first resistor and a second resistor that set the fixed bias voltage applied to the second gate to an optimal value;
Furthermore, since the second gate voltage is fixed via the third resistor as a dump resistor, a large power gain and low noise figure can be obtained at high frequencies, and since it is used within a range with good linearity, it has excellent cross-modulation characteristics. , stable operation can be achieved by using a dump resistor.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram of the 4-pole MESFET of the present invention;
The figure is a plan view of the 4-pole MESFET of the present invention, and FIG.
FIG. 4 is a sectional view taken along line BB in FIG. 2, FIG. 5 is a diagram showing the power gain of the 4-pole MESFET of the present invention, and FIG. Figure 7 is a cross-sectional view of a conventional 4-pole MESFET, and Figure 8 is a diagram showing the noise figure.
The figure is a circuit diagram of a conventional 4-pole MESFET. 1 Semiconductor substrate 2 --- Insulating film 3 --- Active layer 4 --- Depletion layer 5a --- Source Region 5 b - Drain region 6 - Ohmic metal 7 a - Source electrode 7 b - Drain electrode 8 - Schottky gate 9 a - ...-
First gate electrode 9b--Second gate electrode IO--Bias resistor 11--1--First resistor 12--
・-Second resistor 13--Third resistor metal 7b Drain electrode 5b Drain cutout Figure 3 A-A sectional view in Figure 2 9b Second gate electrode b Figure 4 13 B-8 cross-sectional view of the third resistor No. 2 Kasumi Figure 1 Isoplanar diagram of the 4-pole MESFET of Wabiaki Honwa Figure 2 Plan view of the 4-pole MESFET of the present invention Gate-source voltage VGIS (V ) Figure 5 is a diagram showing the voltage 7':I gain of the 4-pole MESFET of the present invention.Gate-to-source voltage VGIS() 7, . Figure 6: Diagram showing the coefficient of index of Akira Kima's 4-pole MESFET.

Claims (1)

[Claims] Dual gate F with fixed voltage of the second gate
In ET, a first electrode is placed between the drain electrode and the source electrode.
and a second resistor are connected in series, and the second resistor is connected from the connection point of the first resistor and the second resistor through the third resistor.
The dual resistor is characterized in that the ratio of the first resistor to the second resistor is set so that when a fixed bias is applied to the gate, the voltage at the connection point is equal to the threshold voltage of the second gate. Gate FET.