JPH03123238A - Common buffer type switch - Google Patents

Abstract

PURPOSE:To prevent effect of address error onto other devices and hindrance of switch operation by managing circulatingly non-use and operating addresses in a common buffer between non-use and operating address management means to apply switch operation between input and output ports. CONSTITUTION:A cell C inputted from an input port 1 is stored in a non-use address of a common buffer 2 given from a non-use address management means 4 and the address in busy state is managed by an operating address management means 5. The cell C is read from the operating address of the buffer 2 given from the means 5 and the cell C is outputted from a prescribed output port 3. An address being idle by the readout of the cell C from the buffer 2 is transferred by the management of the means 4. Thus, switch operation between input and output ports 1, 3 is implemented. When a detection means 7 detects an address error in the access of the buffer 2, an abort means 8 inhibits the use of the erroneous address.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a common buffer type switch applied to a switching device or a cell multiplexing device using an asynchronous transfer mode (△rM). A common buffer that includes a port, an output port, and a common buffer, and that stores cells input from the input port? unused address management means for managing the unused addresses of the common buffer stored in the cell; and used address management means for managing the used addresses of the common buffer stored in the cell; A common buffer type that stores cells input from an input port and performs switching operations between input and output ports by reading cells from the common buffer's usage address given by usage address management means and supplying them to a predetermined output port. Regarding switches.

[Conventional technology]

A first example of a conventional common buffer type switch is shown in FIG. 9 (Citation: Jean-Pierre C0UOR
EUSEand Hichel 5ERVEL PRE
LUDE:AN ASVNCI-IRQNOUSFIN
E-01VISION S old TCH [011ETWOR
” IEEE Inter-national c
onrerence on C0IIIltlniCa
tiOn&'87: Communication
-Sound to Light, Proceedin
gspp, 769-773 vol, 2).

In this example, the number of input ports and the number of output ports are equal, each being four. Reference characters 5Sil to i4 indicate input ports 1 to 4, and cells icl to i4 are input from each input port at the same time.
ic4 is input to the block dividing section 80. A cell is divided into equal blocks of the same number as the number of input ports and processed. Therefore, in FIG. 9, it is divided into four parts. 1st, 2nd, etc. in order from the beginning of the cell. Third. We will call it the fourth block and represent it as 10+, 102.103.104 in icl, and the time of each block is 1+j (1-0, 1,
2, 3, j = 0.1.2.3.4.5°6). In the following description, the unit of time is the time for one block. In addition, unless otherwise specified, the human output ports of each part are expressed as ports 1, 2, 3, and 4 from top to bottom in the figure.

The configuration of the block front portion 80 is shown in FIG. In FIG. 10, the input ports are ports 1, 2, 3, 4, . . . from the top. The output ports are ports 4.3 and 2.1 from the top. Code 90-
Delay circuits 1 to 90-3 each provide a delay of 1.2.3 blocks, and 91 represents a barrel shifter. 1st
Figure 0 shows changes in the connection relationship between the input and output ports of the barrel shifter.

The connection relationships go through one cycle every four blocks of time, and the four connection relationships are shown in chronological order in FIG. 10(a).

Shown in (b), (C), and (d). Input cell ic2. tc3. ic4 is given a delay of 110 blocks, 2 blocks, and 3 blocks by delay circuits 90-1 to 90-3, respectively, and then the barrel shifter 91 applies the first, second, . Third. The 470th ports are output ports 1, 2, 3, . . . of the block dividing section 80, respectively.
4 is output. - Taking iC2 as an example, i
Since the first block 10+ of cl is output at time tn, 170 blocks later, the first block 20+ is output to the output port 1 of the block division unit 80 at time to, and the second block 202 is output to the output port at the same time. 2, the third block 203 is output to output port 3 at time tI3, and the fourth block 204 is output to output port 4 at time tI4. Therefore, output port 1 of block dividing section 80
4, a set ibl-ib4 of the first to fourth blocks of cells input from each input port at the same time is outputted with a time shift of one block. The common buffer 82 is composed of four RAM memories r1 to r4, which are equal to the number of blocks, and each of them stores the first to fourth blocks. The write address restoration means 83 uses the common buffer 82
It is composed of a cyclic counter that cycles through all addresses (0 to n in FIG. 9) of the RAM memory constituting the block, and counts up by 1 every block time.

The value of this counter is used as the write address to the RAM memory, and the RAM memory r1 that constitutes the common buffer 82 is
-Give to r4 at the same time. Suppose that block 40+ in ibl is input to the common buffer at a certain time τ, and address "23" is given from the write address $ controller 83 at that time.
3” has blocks 40+, 30z, and 203, respectively.
.

104 is written. Block 10 constituting icl
1 to 104, the first block 10+ of the input cell ICL is placed at address “20” of RAM memory r1 at time (τ-3), and the first block 10+ of input cell ICL is placed at address “21” of RAM memory r2 at time (τ2). 270 Tsuku 102 is the time (τ-
1), the third
Block 103 is written to address "23" of RAM memory r4 at time τ, and fourth block 104 is written to address "23" of RAM memory r4.

That is, the first block of input cells is in the RAM memory r1.
If 1 is written to the address "a" of the second . Third. The fourth block is RAM memo 'Jr2. r3
．． r4 address “a+1”, “a+2 pa-a-) 3
”. On the other hand, the R
The address of the AM memory r1 is sent to the address storage section 84, and according to the output port number read from the first block by the output port reading section 81, the address is allocated by the section 85 to the memory that operates in the corresponding north-first-in-first-out mode. (hereinafter referred to as FIFO memory) and stored. Symbols f1 to f4 are address storage FIFOs corresponding to output ports 01 to o4, respectively.
Indicates memory. Therefore, if the input cell icl is output to the output port 03, the address "20" of the RAM memory r1 into which the 110th check 10+ has been written is stored in the FIFO memory r3 of the address storage section 84.

The read address from the common buffer 82 is given from an address reading section 86. Address reading section 8
6 is a FIFO memory "1 to f4 cyclically
Read addresses one by one at block time. If the read address is “a”, first the common buffer 82
The first block is read from address "a" of RAM memory r1. One block time later, the address “a”
'' is incremented by 1 in the address adder 87-1, and the second block is read from the address ``a+1'' of the RAM memory r2.Furthermore, after that 1 block vR, the address ``a+'' is added.
1" is added by 1 in the address adder 87-2, and the third block is read from the address "a+2" of the RAM memory r3. Finally, one block time later, the address "a+2" is read out.
2" is added by 1 in the address adder 87-3, and the fourth block is read from the address "a+3" of the RAM memory r4. To explain with reference to FIG. 9, at time t21, the FIF
Assuming that the address "22" is read from the O memory r2, the address "22" of the RAM memory r1 is read out at time t21.
The first block 301 is read from address "23" of RAM memory r2 at time t22, and the third block 303 is read from address "24" of RAM memory r3 at time t23. Then, at time t24, address “25” of RAM memory r4
The data is read out from the fourth block 304. The first cell forming the cell as described above. Second. Third. The fourth block is outputted to output ports 1 to 4 of the common buffer 82 with a delay of one block time.

That is, sets ob1 to ob4 of the first to fourth blocks are output to output ports 1 to 4 of the common buffer 82, respectively. Ob1 to Ob4 are input to the block combining section 88. The configuration of the block combining section 88 is shown in FIG. In Figure 11, the input ports are ports 1, 2, 3, and 4 from the top.
．． The output ports are 4.3.2.1 from the top. It is composed of a block dividing section, a barrel shifter, and delay circuits 10-1 and 10-3 that provide delays of 3 and 2.1 blocks, respectively. Each block is connected to a corresponding output port by a barrel shifter 91, and the first to fourth blocks are combined and returned to the cell form, and the delay circuits 10-1 to 10-10
-3, the leading times of the cells that are different between the output ports are combined and output to the output ports.

Writing to and reading from the RAM memory is performed once per block time.

As described above, a switching operation from an arbitrary input port to an arbitrary output port is performed using the common buffer.

A second example of the conventional common buffer type switch is shown in Fig. 12 (References: Kai Endo, Naohiko Ozaki, Yoshito Sakurai, Shinobu Gohara "A Proposal of A1M Switching Architecture", IEICE Technical Report S
SE 88-56 01), 37-421988).

In this example, the number of input ports is 4. The case where the number of output ports is 4 is shown. Reference numeral 110 is an input selection unit that selects an input port connected to the common buffer; reference numeral 111 is an address chain storage unit that stores an address to be read next; reference numeral 1
12 is a common cell buffer section for storing cell data, and the symbol @
113 is an output selection unit that connects the cell read from the common cell buffer to the corresponding output port, 114 is a write address holding unit that holds the next write address for each output port, and wp1 to wp4 are output ports 0, respectively.
Fortune-telling address pointer corresponding to 1 to 04, code 1
15 is a read address holding unit that holds the next read address for each output port, rp1 to rf) 4 is a read address pointer corresponding to the output port Or to 04, respectively, and 116 is an empty space that holds the empty address of the common cell buffer 7 section 112. Indicates address buffer.

The output port reading section 81 reads the output light from the cell input from the input port, reads out the read address pointer "a" corresponding to the output port from the read address holding section 114, and reads out the read address pointer "a" corresponding to the output port from the read address holding section 114.
Writing 1 cell into address ``a'' of 2, and reading 1 empty address from the empty address buffer 7116 and writing that address into 1. Writing by reading the bamboo register address ``a'' of the address holding unit 114. It is stored in the address pointer and stored in the address "a" of the address chain storage section 111 to form an address chain.
If a cell connected to output port o1 is input from input port 12, write address pointer W of write address holding unit 114 corresponding to output port 01
According to DI, the cell is written to address “3” of the common cell buffer 112, and the empty address buffer 7116
Address "6" is read from address "6", "6" is written to wpl, and address "6" is written to address "3" of address chain storage section 111. The read address holding unit 115 holds the oldest address of the address chain formed for each output port, and cells are read out to the corresponding output port according to this address. Further, after reading a cell, the next address to be read is read from the address from which the cell was read in the address chain storage unit 111, and is held in the read address holding unit. Furthermore, since the address from which the cell was read becomes vacant, it is stored in the vacant address pad 77116. When a cell is read to output port 03, address “4” is read from rp3, and read from address “4” of common cell buffer section 112 to output port 0.
Output to 3. Further, address “9” to be read next time is read from address “4” of address chain storage unit 111 and stored in rp3. Address “4” is also a free address, so it is stored in free address buffer 116.

[Problem to be solved by the invention]

In the first example of the conventional common buffer wall switch described above, the write address is given periodically by the counter and the read address is given randomly by the output port, so the readout is completed before the write address goes around. There is a problem in that it is necessary to provide more memory than the required amount of memory. Alternatively, there is a problem in that the write address circulates and overwrites the data before reading is performed, causing cell discard. In addition, 10 cells of different input ports are stored in the same address in different RAM memories.
Therefore, even if there is a port without an input cell, it is necessary to write one invalid data to that address, resulting in a waste of memory. In other words, although hardware-wise the same memory is commonly used by all ports, logically the amount of memory is allocated evenly to the input ports, so it is equivalent to providing different memory for each input port. Therefore, it is not a complete common buffer.

In the second example of the conventional common buffer type switch mentioned above, it is a complete common back 7, but since the addresses are in a chain, if even one error occurs, it will spread in a chain reaction and the normal state will be affected. There is a problem that it does not return to .

Therefore, an object of the present invention is to maintain a complete common buffer while preventing the error from spreading to other addresses when an error occurs in an address, thereby preventing the overall switch operation from being affected. That's true.

[Means to solve the problem]

The present invention has a configuration as shown in FIGS. 1(a) and 1(b). Unused address management means 4 includes an input port 1, an output port 3, and a common buffer 2, and manages unused addresses of the common buffer 2 that is to store the cell C input from the input port 1; A used address management means 5 for managing the stored used addresses of the common buffer 2, and a cell C manually inputted from the input port 1 is stored at an unused address of the common buffer 2 given from the unused address management means 4. , hill C from the used address of the common buffer 2 given from the used address management means 5
This assumes a common back 7-type switch that performs switching operations between input and output ports 1 and 3 by reading data from 8 and supplying it to a predetermined output port. As shown in FIG. 1(a), the unused address management means 4 commonly manages the unused addresses of the common buffer 2 for the cell C input from the input port 1. At the same time, the used address management means 5 manages the used address of the common buffer 2 according to the output mode of the cell C stored at that address, and for each address of the common buffer 2, An identifier storage means 6 that stores an identification f indicating a means by which an address is managed, a means that actually manages the address when accessing the common buffer 2, and an identifier corresponding to the address in the identifier storage means 6. The address error detecting means 7 detects an error in the address by comparing it with the address error, and the address discarding means 8 prohibits the use of the erroneous address when the address error detecting means 7 detects an error in the address. be.

Specifically, Mr. B to whom the stored cell C should be output, which is the basis of management in the use address management means 5, refers to the output port 3 to which the output is to be made, or the priority of the predetermined output order, etc. It is determined arbitrarily depending on the purpose.

Furthermore, in order to prevent a simple decrease in the number of usable addresses and ensure more appropriate switch operation when the number of erroneous addresses increases, as shown in FIG. 1(b), in addition to the above configuration, The apparatus is equipped with an address restoration means 9 for searching for and restoring the address before the error with respect to an address that has been lost due to prohibition of use by the address discarding means 8.

[Effect]

The cell C manually entered from the input port 1 is stored in an unused address of the common bag 72 given from the unused address management means 4, and the address that is in use is managed by the used address management means 5. Become. And the common back given from the used address management means 5? The cell C is read from the used address No. 2, and the cell C is output from a predetermined output port 3. By reading the cell C from the common buffer 2, the unused address is transferred to the unused address management means 4. In this way, the common buffer 2 is managed by circulating the address of the common buffer 2 between the unused address management means 4 and the used address management means 5, thereby controlling the switching operation between the input/output ports 1 and 3. It will be done.

In the process of the above switch operation, the identifier storage means 6 stores, for each address in the common buffer 2, an identifier indicating the means by which that address is managed.

When the common buffer 2 is accessed, the address error detection means 7 includes means for actually managing the accessed address of the common buffer 2, and the above-mentioned identifier storage means 6.
When an error in the address is detected by comparison with the identifier corresponding to the address in the address, the address discarding means 8 prohibits the use of the detected error address. As a result, in the process of subsequent switch operations, the address in which the error was detected is excluded from the management of whether it is used or not. That is, the common buffer 2 is not accessed at the incorrect rear address.

Furthermore, when the address restoration means 9 is provided, the address restoration means 9 searches for a normal address before the error and restores the address whose use has been prohibited as described above.

The erroneous address is managed to be used or unused in its original state.

〔Example〕

Hereinafter, an embodiment of the present shouting will be described based on the drawings.

FIG. 2 is a diagram illustrating a common buffer type switch which is a first embodiment of the present invention.

In the embodiment, the free address of the RAM memory that constitutes the common buffer is managed by a common FIFO memory, so the size of the common buffer can be kept to the minimum necessary, and furthermore, the used address can be output. F for each port! Since it is managed by the FO memory, even if an error occurs in an address, the error will end with that address only, and the error will not spread to other addresses. In addition, a correspondence storage unit is provided to store the location where addresses are managed, and addresses can be stored in FI.
When writing to the FO memory, the identification f indicating the FIFO memory is stored in the corresponding storage section, and when reading from the FO memory, the data is stored from the same FIFO memory as the FIFO memory indicated by the identification f stored in the corresponding storage section. It has the feature that an error in an address can be detected by checking whether it has actually been read, and the use of the erroneous address can be prohibited.

The number of input ports and the number of output ports may be any number. Here, as an example, a case where the number of input ports is 4 degrees and the number of output ports is 4 is shown. The operations from the input ports 11 to i4 to the input of the common buffer 82 and the operations from the output of the common buffer 82 to the output ports 01 to 04 are the same as in the first conventional example, and will therefore be omitted.

11-1.11-2.11-3.11-4 are write address registers that provide write addresses to the RAM memories r1 to r4, respectively; 12-1.12-2.
12-3 and 12-4 are RAM memories rl-r4, respectively.
The read address register that provides the read address is shown.

In the initial state, all of the RAM memories forming the common buffer are empty, so all addresses of the RAM memory are stored in the free address buffer 710, and nothing is stored in the address storage section. . Further, the write address registers 11-1 to 11-4 and the read address registers 12-1 to 12-4 are in a state corresponding to a case where there is no input cell and a case where there is no read cell, which will be described later.

FIG. 3 is a diagram illustrating the operation of writing blocks into the common buffer. Connections, etc. that are not related to the field digging operation are omitted.

Assume that at a certain time τ (the first block 10+ of the input cell icf is written to the common buffer.
4 are output ports 03°01, o4. It is assumed that it is output to o2. Figure 3 (a), (b), (c), (
d) and <e) are times (τ-1), τ, and (τ+1), respectively.
), (τ+2), and (τ+3). Time (τ−
1) (see 3rd Fg (a)) write address registers 11-1 to 11-4 contain some address (*1
~*4) is retained. The empty address buffer 710 contains 2" from the beginning, "'23", "5", 20"
Empty addresses "27"... are stored and read out in this order. At time τ (see Figure 3(b))
Vacant? Empty address "2"' is read out from the address buffer 10, held in the write address register 11-1, and written to the write address register 11 at time (τ-1).
The addresses held in -1 to 11-3 are stored in the write address registers 11-2 to 11-4, respectively, and the addresses held in the write address register 11-4 are written to indicate that writing has ended. block 10 at address “2” of RAM memory r1.
+, r'2 to r4 have addresses “*1” to “, respectively.
At *3'', the block input to the input ports 2 to 4 of the common buffer at time τ is read by 1. Also, the output port reading unit 81 reads from block 10+ to 03 of the output port destination.
is read out, and based on this, the address "2" is sent to the address storage section 84, and the address allocation section 85 stores it in the FIFO memory f3 corresponding to the output port 03. At time (τ+1) (see FIG. 3(C)), address "23" is read from the empty address buffer 10,
Similarly to the case of time τ, block 20 is stored in RAM memories ri and r2 at address "23" and M211, respectively.
1 and 10z are written, and the address "23" is stored in the FIFO memory f1. At time (τ+2), (3rd f
(see fl(d)) Address "5"' is read from the free address buffer 10, and in the same way, the address "5"' is read out from the RAM memory r1.
．． r2. r3 has address “5H9”23” respectively.
Block 30+, 202.103 is allocated to M 2 H, and address "5H" is stored in FIFO memory "4". At time (τ+3) (see FIG. 3(e)), address "20" is read from the free address buffer 10, and the RAM memory r1. r2. Address “20” “5” “23” “2” for r3 and r4 respectively
block 40+, 302.

20g, 104 is populated, FIFO memory f2
Address "20" is stored in . As described above, all blocks of the human cell ICL are polished to the same address in the RAM memories r1 to r4. If there is no input cell,
Empty addresses are read and 1 is not written into the f1RAM memory. Alternatively, a vacant address is read f1, and a specific address is assigned to 1 reading when there is no cell, and data indicating that there is no cell is read into that address. Alternatively, an empty address is read, data indicating that there is no cell is written at that address, and the address is written into the empty address buffer i ok:s without being stored in the address storage section 84 .

FIG. 4 is a diagram illustrating the operation of reading blocks from the common buffer. Connections and the like that are unrelated to the read operation are omitted.

Assume that a cell output to the output port o1 is read out at a certain time τ. Figures 4(a) and (b).

(c), (d), and (e) are times (τ-1), respectively.

The states of τ, (τ+1), (τ+2), and (τ+3) are shown. At time (.tau.-1) (see FIG. 4(a)), some addresses (represented by *1 to *4) are held in the read address registers 12-1 to 12-4. It is assumed that the addresses "'23", "20", "2", and "5" are stored at the beginning of the FIFO memory "1" to "4" of the address storage section 84, respectively. At time τ (see FIG. 4(b)), the address reading section 86 reads out the address "23" into which 1 cell is to be output from the f-IFO memory f1 to the output port o1, and the address is read out from the read address register. 12-1, and the addresses held in read address registers 12-1 to 12-3 at time (τ-1) are read address registers 12-2 to 12-3, respectively.
12-4 and the address held in the read address register 12-4 disappears when reading is completed, and the address "
Blocks 20+ from 23'' and blocks to be output to output ports 2 to 4 of the common buffer are read from addresses ``*1'' to ``*3'' of r2 to r4, respectively.Additionally, address ``23'' is empty. Since it becomes an address, it is stored in the free address buffer 10. At time (τ+1), see FIG.
20'' is read out and stored in the RAM in the same way as at time τ.
Addresses “20” and 23 of memories ri and r2, respectively
”, blocks 40+ and 202 are read out, and the address “20H” is stored in the free address buffer 710.

At time (τ+2) (see FIG. 4(d)), address "2" is read from FIFO memory "3", and in the same way, each address "2" of RAM memory r1, r2, r3 is read out.
Block 10+ from 2", "20" and "23", 402
．． 203 is read out, and address "2" is stored in empty address pads 7-10. At time (τ+3) (see FIG. 4(e)), the address “5” is read from the FIFO memory r4.
” are read out, and the RAM memories rl, r2 .
Addresses “5”, “2”, and '2 of r3 and r4, respectively
Block 30+ from 0"23", 102.40g,
204 is read out, and address “5” is stored in the empty address buffer 10. The four blocks 20 forming the cell OC1 output to the output port 01 as described above
1 to 204 are read out. If there is a FIFO memory in which no address is stored in the address storage unit 84, reading from the RAM memory is prohibited. Alternatively, a specific address to which specific data to be read if the address does not exist is determined, and data is read from that address.

Alternatively, that FIFO memory is skipped and the address written in the next FIFO memory is read.

The switch operation is performed as described above.

If the number of input ports and the number of output ports are different, divide the block into the same number of ports as the larger number. As an example when the number of output ports is large, the number of input ports is 2. Number of output ports: 4
Let's take the case of In this case, the number of input ports mentioned above is 4. In the case of 4 output ports, this is equivalent to the case where there is always no input from any two input ports, and it can be assumed that those two input ports do not actually exist and there is no circuit related to those ports. .

As an example of a case where the number of input ports is large, the number of input ports is 4.
．． Let us consider the case where the number of output ports is 2.

In this case, the number of input ports mentioned above is 4. In the case where the number of output ports is 4, addresses are not always stored in any two FIFO memories of the FIFO memories of the address storage unit 84, and as described above, the address is This is equivalent to reading an address; in reality, there are no two FIFO memories and corresponding output ports;
It can be assumed that there is no circuit related to FO memory and output ports.

A method for detecting address errors and disabling the use of erroneous addresses will be explained below.

-For example, common banno? The case where the addresses of the RAM memory 82 are 0 to 31 is shown. In this case, since the number of addresses is 32, the address is expressed using 5 bits.

Support for storing the identification IF indicating the address storage location &! The storage section 13 contains all addresses that can be expressed in 5 bits.
Consists of AM memory. That is, here, it is constituted by a RAM memory having addresses 0 to 31. Therefore, even if an error occurs in the address and the address changes to a different address, the address is still included in the addresses in the correspondence storage section 13, so the error can be detected.

- For example, if the address is stored in the free address buffer 10, it will be "0000", and if the address is stored in FIFO memory "1 to f4", it will be "000", respectively.
01"° 0010"9 "oioo""100
0" is an identifier indicating the address storage location. During the switch operation described in rti, the RAM constituting the common buffer 82
Transfer the available address “a” to the free address buffer 1.
0 or in the FIFO memories f1 to f4, the address Emj is written to the address "a" of the correspondence storage section 13.
An identifier indicating the iA location is stored.

Free address buffer 10 or FIFO memory f1~
When a certain address "b" is read from f4, the identifier indicating the address storage location stored in the address "b II" of the correspondence storage section 13 is read out, and it is checked whether or not it was actually read from the location indicated by the identifier. It is checked by the address error checking unit 14, and if they match, it is determined to be normal.
The above-mentioned switch operation that affects that address continues. If they do not match, it is determined that there is an error in the address or in the correspondence storage section 13, and no operation is performed regarding that address. Also, does that address have a free address buffer? 10 or FIFO memories f1 to f4 and discard them without occupying them and prohibit their use.

In the error detection method described above, if the same normal address as the erroneous address is managed in the same location, error detection cannot be performed. However, the address is a different FIF
Since the probability that the error will continue to be managed by the same FIFO memory is extremely small, the probability that error detection will not be detected forever is approximately O.

When the addresses 0 to 31 of the common buffer 82 are expressed by 6 or more pits, the addresses in the correspondence storage section 13 other than those corresponding to the addresses 0 to 31 of the common buffer 82 contain an identifier other than an identifier indicating the location. It is predicted in advance that the address cannot exist using the data of .

The correspondence storage unit 13 can also be realized by one memory by providing a block storage area and a storage area for the management location identification f in the RAM memory of the common buffer 82.

The above error detection method will be explained in more detail with reference to FIG. Connections and the like that are unrelated to error detection are omitted. Fifth
Assume that the address is stored as shown in the figure, and its status is stored in the correspondence storage section 13. Is there a vacant address? If address “3” is read from 10,
“oooo” is stored at address “3” of the correspondence storage unit 13 as an identifier indicating the storage location, and since this identifier indicates the free address buffer 10, it is normal, so the operation continues and, for example, the address "3°' is stored in the FIFO memory "2 corresponding to the output, and the corresponding memory section 1
3 address “as a new storage location at position 3′°”
0(11<1”. Also, F[FO memory f3
When address “6” is read from
Address “6” of 3 is written I! “0001” as location
” is stored, and this identification f is stored in the FIFO memory f1.
Since it is different from the FIFO memory r3 that was actually read, it is determined that there is an error, and the address "
The operation regarding "6" is discontinued, and the address "6n itself is also discarded without being written anywhere. Specifically, the storage timing signal for the read out failure register 12-1 and the F
Write timing signal for IFOIO
By doing this, address "6" is read out from address register 12-1 . 'Do not store in FIFO10. Further, if the address "3" from the FIFOIO is incorrect, storage of the address in the old address register 11-1 and address allocation section 85 is prohibited under the control of the timing signal as described above.

In the above switch, priority control can be easily added to the output order of cells to the same output port. In other words, priority!
FIFO memories corresponding to the output ports that perform 1Jtlll are individually provided according to the priority, and when writing an address, address allocation is performed in the section 85 by writing 1 into the FIFO memory for both the destination output port and the priority, and writing the address. Reading can be accomplished by reading the address from the FIFO memory with the highest priority in which the address has been written for a certain output port.

Further, in the above-mentioned switch, a broadcast type switch that outputs one cell to all output ports can be easily realized.

That is, when reading the address of a cell to be output to all output ports, the read pointer of the FIFO memory is fixed at the position where that address is written, and the address reading section 86 also reads the FIFO memory so that the address is written. By fixing the data that originally circulates in the FIFO memory contained in the memory, cells are read from the same address for all output ports, so a broadcast-type switch can be easily realized.

FIG. 6 is a diagram illustrating a common buffer type switch which is a second embodiment of the present invention.

The number of input ports and the number of output ports may be any number. Here, as an example, a case where the number of input ports is 2 degrees and the number of output ports is 2 is shown. The input cells are divided into blocks equal to the sum of the number of input ports and the number of output ports. Therefore, it is divided into four here. Reference numerals 50-1 to 50-4 indicate address registers that provide addresses to the RAM memories r1-r4.

In the block dividing unit 80, i
C2 is given a delay of 1, 2 or 3 blocks, and the first . Second. The third and fourth blocks are output to output ports 1.2 and 3.4 of the block dividing section 80, respectively. The amount of delay only needs to be such that the first block of cells input from all input ports at the same time is within one cell time range.

Here, the delay port is set to two blocks.

Taking iC2, the first block of icl 10+
Since it is output at $Ii time tu, the first block 201 is output to the output port 1 of the block dividing unit 80 at time IjJ t +t, and the second block 202 is output two blocks later than that.
is connected to output port 2 at time to, the third block 203 is connected to output port 3 at time tH, and the fourth block 204 is connected to output port 3 at time Mt.
It is output to output port 4 at h.

FIG. 7 is a diagram illustrating operations for writing blocks into the common buffer and reading blocks from the common buffer. Connections, etc. not related to operation are omitted.

Assume that the first block 101 of the input cell ic1 is written to the common buffer at a certain time τ. Also, icl, ic
2 shall be output to the output port o2°01, respectively. Figure 7(a).

(b), (c), (d), (e), and (f') are times (τ-1), τ9 (τ+1), and (τ]2), respectively.

The states of (τ+3) and (τ+4) are shown. In the free address buffer 10, empty addresses 2", 23, 5, etc. from the beginning are stored. Also, the FIFO memory f1. Addresses "20" and "1" are stored at the beginning of f2, respectively, and blocks 111 to 114 and 211 to 214 are stored at addresses "20" and "1" of RAM memories r1 to r4, respectively. At the time IJ(τ-1), some address (see Figure 7 Ca) is stored in the address registers 50-1 to 50-4.
*1 to *4) are retained. At time τ (see seventh ffl(b)), empty address “2” is read out from the empty address buffer 10, and the address register 50 is read out.
-1, and the address register 5 at time (τ-1)
The addresses held in 0-1 to 50-3 are shifted to and held in address registers 50-2 to 50-4, respectively, and the addresses held in address register 50-4 disappear and are transferred to RAM memory r1. Block 10+ at address “2”, address “*2” of RAM memory r3
”, the block input to the input port 3 of the common buffer at time τ is written. Further, the output port reading unit 81 reads out the output port destination 02 from the block 101, and based on this, the block is written to the input port 3 of the common buffer. Address "2" sent to is stored in FIFO memory f2 corresponding to output port o2 by address distribution W2B5.Additionally, address "*1""*3" of RAM memory r2.r4 is stored in FIFO memory f2 corresponding to output port o2 by address distribution W2B5.
”, the block output to the output ports 2 and 4 of the common buffer is read out. At time τ11) (Fig. 7 (
See C)) FIFO memory “1 to address “20” where cells output to output port 01 are old is read address “i”! The address "2" read out by $86 and held in the address register 501, and held in the address registers 50-1 to 50-3 at time τ
*1" and '*2"' are address registers 50-
The address "*3" that was shifted from 2 to 50-4 and held in the address register 50-4 disappears, and the address "*1" of block 11+ and r3 is shifted from address "20" of RAM memory r1 to address "*1" of block 11+ and r3. ”, the block to be output to output port 3 of the common buffer is read. Furthermore, since address “20” is a free address, it is stored in the free address buffer 10. Also, RAM memory r
2's address "2" is BU0 '/ri102. The block manually inputted to the manual port 4 of the common buffer at time (τ+1) is stale at the address "*2" of r4. Time (τ
+2), empty address "23" is read out from the empty address buffer 10, held in the address register 50-1, and at time (τ11), the empty address "23" is read out from the empty address buffer 10.
The addresses held in address register 50-3 are shifted and held in address registers 5o-2 to 50-4, respectively, and the address held in address register 50-4 disappears, and the address " Block 20+ is written to address "23" and block 103 is written to address "2" of RAM memory r3. Further, the output port reading unit 81 reads out the output port destination 01 from the block 201, and based on this, the address “23” sent to the address storage unit 84 is assigned to the output port 01 by the address allocation unit 85. It is stored in the corresponding FIFO memory f1. Also, the block to be output from the address "20" of the RAM memory r2 to the output port 4 of the common buffer is read from the address "*1" of the RAM memory r4. Address " where the cell output from memory f2 to output port 02 is occupied"
1'' is read by the address reading unit 86 and held in the address register 50-1, and the address “23” “20pa2” held in the address registers 50-1 to 50-3 at time (τ+2) is The address “*1” that was shifted and held in each of the address registers 50-2 to 50-4 and held in the address register 504
disappears, block 21+ from address "1" of RAM memory r1, block 11 from address "20" of r3
3 is read out. Further, since address "1" is a vacant address, it is stored in the vacant address buffer 710.

Further, the block 20z is written to the address "23" of the RAM memory r2, and the block 104 is written to the address "2"' of the RAM memory r4. At time 1 (τ+4), empty address "5n" is read out from the empty address buffer 10 and held in address register 50-1, and at time (τ+3), the addresses held in address registers 50-1 to 50-3 are The addresses held in the address registers 50-2 to 50-4 are shifted and held respectively, and the address held in the address register 50-4 disappears, and the address "5" of the RAM memory r1 is stored in the common buffer 784 at time (τ+4). The block 203 is occupied by the address "23" of the plotter RAM memory r3 input to the input port 1. Also, the output port destination is read from the block written to rl by the output port reading unit 81, and this is The address “5” originally sent to the address storage unit 84 is stored in the FIFO memory corresponding to the output port by the address distribution unit 85. Also, the address “5” of the RAM memory r2 is stored in the FIFO memory corresponding to the output port.
Block 212 is read from address "20" of r4, and block 114 is read from address "20" of r4. As described above, blocks 101 to 104 forming the input cell ICL are read by 1, and blocks 111 to 114 forming the output cell are read. 114 is read out.In this way, a write address is given for 2 of the 4 block times, and a read address is given for the 2nd block time to write and read from the common buffer.Here, the input hill Since ic2 was delayed by 2 blocks with respect to icl, the write and read addresses were given alternately, but depending on how the delay was given, the write or read address could be given twice within 4 blocks. The order can be arbitrary.

If the number of manual ports and the number of output ports are different, it can be realized in the same manner as described in the first embodiment.

The method for detecting address errors and disabling addresses is to set the number of FIFO memories to fl in the first embodiment.
This is similar to the case where there are two, f2 and f2.

In the second embodiment as well, the priority tUa and broadcast format switch can be easily realized in the same manner as in the first embodiment.

The third embodiment of the present invention is the same as the first and second embodiments, with the addition of a function for restoring addresses that are missing because a certain address is disabled and discarded due to error detection. Since the parts for performing switch operation and error detection are the same as those in FIG. 2, FIG. 5, and FIG. 6, only the part related to the address repair section is shown in FIG. −
As an example, a case where the addresses of the RAM memory constituting the common buffer 82 are 0 to 31 (n=31 in FIG. 8) is shown. 70 is an address check storage unit that checks whether an address exists; 71 is an error counter unit that counts the number of erroneous addresses; and 72 is an address repair unit that checks the address check storage unit 70 and restores missing addresses. shows. R constituting the common buffer 82
Since the addresses of the AM memory are 0 to 31, the address check storage section 70 is a RAM having addresses 0 to 31.
Configure with memory.

The error counter 71 is “0” if there is no error address.
It is. Each time an error occurs, it counts up by 1. When the value of the error score section 71 becomes 1 or more, the data at all addresses in the RAM memory of the address check storage section 70 is set to "OH." After that, the address is set from the free address buffer 10 or the FIFO memory "1 to f4." When it is read out, Mill is used as a sign that an address exists at that address in the RAM memory of the address check storage section 70. After a predetermined time has elapsed, the address restoration section 72 reads the address from the address check storage section 70. Check the data at all addresses in the RAM memory, and check the number of "O"s and the addresses where 0s were stored.As a result, if the number of "0s" is equal to the value of the error counter 71, , the address in which "0" was stored is disconnected from the missing address by pI, and the address is filled into the free address buffer 10, thereby restoring the address and setting the value of the error count t571 to 0. If the number is smaller than the value of the error counter 71, then the address that ended the address buffer is incorrect, so the address where 0'' was stored is stored in the free address buffer 10 to restore the address. Then, the number of repaired addresses is subtracted from the value of the error body number section 71, and the data of all addresses in the address check storage section 70 are set to "OH" again, and the above-mentioned processing is performed to recover the remaining missing addresses. If the number of "0"s is greater than the value of the error count unit 71, all existing addresses have not been checked yet, so the check is continued and the same process is performed after a certain period of time has elapsed.

If the number of 'O's is larger than the value of the error counting section 71, the number of "0"s will remain forever due to an error in the counter, etc.
If the value is greater than 1, address repair may not be performed. Therefore, even after a sufficiently long time has elapsed compared to the above-mentioned address check time, if the number of "0"s is greater than the value of the error 51 number section 71, all addresses in which "0"s have been stored are temporarily deleted. Vacant? dress buffer 10
It is also possible to provide a function to write to the error-free state and make the state the same as the error-free state. In this case, there is a possibility that an erroneous address is included in the repaired address, but that error is detected by the method described above, so there is no problem.

In the above embodiment, in particular, the phase of the cell is shifted between input ports, the cell is divided into blocks, and each block has a different RA.
Since the data is stored in the M memory, the operating speed of the common buffer memory can be made lower than the speed of the manual port.

〔Effect of the invention〕

As described above, according to the present invention, unused addresses and used addresses of the common buffer are managed by cycling through the unused address management means and the 1st stage of used address management, respectively. Is the buffer maintained and the minimum common banno required? The switch can be implemented using a bottle, and even if an error occurs in the address, it is only one error and does not spread. Since an error in the address is detected and the use of the erroneous address is prohibited, it is possible to prevent an error from occurring.

Also, the cells themselves are stored in a common buffer, and their 1N1
1 is performed based on the address storing the cell, so a broadcast format switch, etc. can be easily realized.

Furthermore, since erroneous addresses are repaired, it is possible to prevent the number of usable addresses from decreasing due to prohibition of use.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing a first embodiment of the present invention, FIG. 3 is a diagram explaining a cell write operation in the first embodiment of the present invention, and FIG. 5 is a diagram illustrating a cell read operation in the first embodiment of the present invention, FIG. 5 is a diagram illustrating a method for detecting address errors in the first embodiment of the present invention, and FIG. A diagram showing a second embodiment of the present invention, FIG. 7 is a diagram illustrating cell aging and readout operations in a second embodiment of the present invention, and FIG. 8 is a diagram showing a third embodiment of the present invention. FIG. 9 is a diagram showing a first example of a conventional common buffer type switch, FIG. 10 is a diagram showing a block dividing section in a first example of a conventional common buffer type switch, and FIG. 11 is a diagram showing a conventional common buffer type switch. FIG. 12 is a diagram showing a second example of the conventional common buffer type switch. 1... Input port, 2... Output port, 3... Common buffer, 4... Unused address management means, 5...
・Used address management means, 6...Identifier storage means, 7
...Address error detection means, 8.Address disposal means, 9.Address repair means, 70.Empty address pants? , 11-1 to 11-4... Fortune-telling address register, 12-1 to 12-4... Read address register, 13... Correspondence storage section, 14... Address error checking section, 50- 1 to 50-4...address register, 70...address check storage section, 71...
Error field number part, 72... Address repair part, 80... Block division part, 81... Output port reading part, 82
...Common buffer, 83...Write address control unit, 84...Address storage unit, 85...Address allocation unit, 86...Address reading unit, 87-1~
87-3...Address addition section, 88...Block coupling section, 90-1 to 90-3...Delay circuit, 91...
Barrel shifter, 10-1 to 10-3...delay circuit, 1
DESCRIPTION OF SYMBOLS 10... Input selection product, 111... Address chain storage section, 112... Common cell buffer, 113...
・Output selection product, 114...deep address holding section,
115...Read address holding unit, 116...Empty address buffer, 11-i4...Input port 1-
4.01~04...Output ports 1~4, icl~ic
4... Cells to be input at the same time from input ports d to 4, tb1 to ib4... 1st to 4th cells constituting input cells
Set of blocks, OC1~oc4...output port 1~
4, cells output at the same time, obl to ob4... a set of the first to fourth blocks constituting the output cell, r1 to r
4...RAM memory forming a common buffer, f 1
-f 4... FIFO memory forming the address storage section, wpl to wp4... Write address pointer,
rpl to rp4...Read address pointer. Fig. 1(a) A diagram showing the circuit configuration for error detection and repair Fig. 8 Fig. 91 showing the operating state of the barrel shifter Fig. 11 showing the configuration of the block coupling part Fig. 1b Common to the conventional technology Diagram 1 showing another example of a buffer type switch
Figure 2

Claims (2)

[Claims] (1) An unused address management means that includes an input port, an output port, and a common buffer, and manages unused addresses of the common buffer in which cells input from the input port are to be stored, and a common buffer in which the cells are stored. used address management means for managing the used addresses of the common buffer given by the unused address management means, and stores cells inputted from the input port at unused addresses of the common buffer given from the used address management means; In a common buffer type switch that performs a switching operation between input and output ports by reading a cell from a used address and supplying it to a predetermined output port, the unused address management means is configured to read a cell from a used address and supply it to a predetermined output port. The unused addresses of the common buffer are managed in common, and the used address management means manages the used addresses of the common buffer according to the manner in which the cells stored at the addresses are to be output. , an identifier storage means for storing, for each address of the common buffer, an identifier indicating the means by which that address is managed; a means for actually managing the address and the address in the identifier storage means when the common buffer is accessed; address error detection means for detecting an error in the address by comparison with an identifier corresponding to the address; and address discard means for prohibiting the use of the erroneous address when the address error detection means detects an error in the address. A common buffer type switch characterized by: (2) The common buffer type switch according to claim 1, further comprising address restoration means for searching and restoring a normal address before an error for an address that has been lost due to prohibition of use by the address discarding means. Buffer type switch.