JPH02185113A - Signal selecting circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of signal transmission to prevent dullness of a waveform by providing floating preventing flip flops between a selecting circuit in each preceding stage and that in the succeeding stage and between the selecting circuit in the succeeding stage and an output terminal. CONSTITUTION:Floating preventing flip flops 2A, 2B, and 4 are provided between selecting circuit 1A and 1B in respective preceding stages and a selecting circuit 3 in the succeeding stage and between the selecting circuit 3 in the succeeding stage and an output terminal To. Since its is sufficient if each of driver circuits AA1 to AAm and AB1 to ABn drives the diffused capacity of transfer gates TGA1 to TGAm or TGB1 to TGBn of the selecting circuit 1A or 1B, to which this driver circuit is directly connected, in the preceding stage and the input capacity of one flip flop 2A or 2B, the transistor size is miniaturized. Thus, the delay time of signal transmission is shortened and dullness of the waveform is suppressed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal selection circuit, and particularly to a signal selection circuit that selects among a plurality of input signals for internally controlling functions based on a control signal input from the outside. The present invention relates to signal selection circuits such as integrated circuits.

[Conventional technology]

Conventionally, this type of signal selection circuit is activated by an activation signal generated internally based on a control signal input from outside the integrated circuit, and transmits a signal from the previous stage to the next stage at high speed and stably. I'm expecting.

FIG. 3 is a circuit diagram showing an example of the basic configuration of a signal selection circuit used in a MO8O8 type diami RAM, which is a 5.1 single power supply integrated circuit.

This signal selection circuit connects the previous driver circuit AA to the input terminal.
The input signals INAl to INAm and INBI to INB6 from I to AAm and Ast to ABfi are respectively inputted and the first control signals Φ1 to Φdecoration,
Input signals lNA1 to INA according to ΦB1 to Φlb+
A plurality of transfer gates TGm1 to TGA, respectively transmitting signals M, INBI to INan to commonly connected output terminals TA and TB.

One multiple pre-stage selection circuit with TGBI~'I' GBn.

It is equipped with two inverters 11゜work 2 of IB and CMO8ffi whose input end is connected to the output end and output end is connected to the input end, one pre-stage selection circuit for each, and one pre-stage selection circuit connected to the output end of 1m. , 1B, the levels of these output signals are held according to the output signals of the transfer gate T.
GAI ~T GAm, T GBI ~ T G B
A plurality of floating prevention circuits 5m maintain the level of the immediately previous output signal even if all of the pre-stage selection circuits IA and IB are in a floating state.

5B, the input terminals are connected to the output terminals TA, T, of the preceding stage selection circuits IA, IB, respectively, and the output terminals are commonly connected to the output terminal ToK, and the second control signal Φ3! .

According to Φ3, the front stage selection circuit 1a, 1! A post-stage selection circuit 3 equipped with a plurality of transfer gates (T G31 and T Gss) each transmitting an output signal of + to an output terminal To, and an 0MO8 type 0MO8 type circuit in which the input terminal is connected to the output terminal and the output terminal to the input terminal are connected to each other. It is equipped with two inverters 1 and 2, which are connected to the output end of the second stage selection circuit 3, and maintain the level of this output signal according to the output signal of this second stage selection circuit 3, so that the second stage selection circuit 3 becomes a flow control circuit. ing.

[Problem to be solved by the invention]

The conventional signal selection circuit described above has each pre-stage selection circuit LA+
lB transfer gate TGA, ~T G Am +
The output terminals of 'reB, ~TG,, are connected in common, and the output terminals of these front-stage selection circuits LA+IB are connected to the output terminal T through the transfer gates TGH and TGsz of the rear-stage selection circuit 3.
Since the configuration is such that the driver circuit (e.g. AAI) is commonly connected to the connected pre-stage selection circuit (
All transfer gates (TGA1 to TGA
In) diffusion capacitance, all transfer gates of the subsequent stage selection circuit 3) TGst*TG, floating prevention circuit (5A), 60 input capacitance, next stage input capacitance connected to output terminal To, and these wirings It is necessary to drive the capacitance, etc., and the driver circuit Am1~AAm*ABI~AB
The dimensions of the transistor forming the n are increased, and the fourth
As shown in the figure, there is a drawback that the evening waveform with a long signal transmission delay time becomes dull.

An object of the present invention is to provide a signal selection circuit that can reduce the area occupied by a driver circuit, shorten signal transmission delay time, and prevent waveform distortion. Ru.

[Means to solve the problem]

The signal selection circuit of the present invention includes a plurality of front stages each including a plurality of signal transmission elements each inputting a corresponding input signal to an input terminal and respectively transmitting the input signal to a commonly connected output terminal according to a first control signal. and a plurality of selector circuits whose input terminals are connected in correspondence with the output terminals of each of these preceding-stage selection circuits, and which maintain the level of the output signal of these selection circuits in accordance with the output signal of each of these preceding-stage selection circuits. The input ends of the flip-flops 70 at the front stage are connected to the output ends of the seven flip-flops at the front stage, respectively, and the output signals of the flip-flops at the front stage are connected in common according to the second control signal. a subsequent selection circuit comprising a plurality of signal transmission elements for transmitting signals to the subsequent selection circuit; an input terminal connected to the output terminal of the subsequent selection circuit; and an output terminal connected to the output terminal to respond to the output signal of the subsequent selection circuit; It has seven lip-flops at the rear stage that hold the level of the output signal of the selection circuit at the rear stage of the lever.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The pre-stage selection circuit LA+IB is shown in FIG. 3 and has the same configuration and operation as the conventional signal selection circuit.

Each of the flip-flops 2 + 2B is equipped with two 0MO8 type inverters I, , I, whose input terminals are connected to the output terminals and whose output terminals are connected to the input terminals, and the input terminals are connected to one pre-stage selection circuit and the output terminal of 1B. A floating prevention circuit that is connected correspondingly to and holds the level of these output signals according to the output signal of the previous stage selection signal lAylB, and also maintains the level of the immediately previous output signal even if the previous stage selection circuit LA+lB is in a floating state. It becomes.

The latter stage selection circuit 3 has an input terminal that is floating, and a block flop 2A+2.
A plurality of transformers 7 agate TG31. 're32 and one control signal Φ31. According to Φ32, Furi, Puflo,
The output signal of the pull-up 2A1211 is transmitted to the output end.

Furi, Buflo, and Pu4 are two 0MO8 type inverters I, whose input end is connected to the output end, and the output end is connected to the input end.
. This is a floating prevention circuit that maintains the level of the immediately previous output signal even if the selection circuit 3 enters the 70-setting state.

In this way, two flip-flops + 2B for floating prevention are installed between each front-stage selection circuit lAt1B and the rear-stage selection circuit 3, and between the rear-stage selection circuit 3 and the output terminal To.
, 4, the driver circuits AAI to AAm
+ ABl to ABa are each directly connected to one previous stage selection circuit (IA.

1B) transfer gate (TGAS-TG
AITl+TGB,~TGBn) diffusion capacitance and one 7
Since it is sufficient to drive the input capacitance of the lip-flop (2A12B), the transistor size can be reduced.

In addition, the two flip-flops, 2B, may drive the diffusion capacitance of the transfer gates TGAl and TGAm of the subsequent stage selection circuit 3 and the input capacitance of the flip-flop 40, and the flip-flop 4 may drive the input capacitance of the next stage connected to the output terminal To, respectively. Therefore, the diffusion capacitance, input capacitance, etc. of each part are distributed and driven, and as shown in Figure 2, the delay time of signal transmission is shortened, and waveform distortion is also suppressed. It will be done.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which flip-flops for preventing 70-bit switching are provided between each preceding-stage selection circuit and subsequent-stage selection circuit, and between each subsequent-stage selection circuit and the output terminal. Since the load on the driver circuit is reduced, the transistor size can be reduced, and the area occupied by the driver circuit can therefore be reduced.Also, since the diffusion capacitance, input capacitance, etc. of each part are distributed and driven, the signal This has the effect of shortening the transmission delay time and preventing waveform distortion.

FIG. 4 is a signal waveform diagram for explaining the problem of the signal selection circuit shown in FIG. 3.

lA, 1! L-・Pa front stage selection circuit, 2 people, 2B...
...Flip-flop, 3...Late stage selection circuit, 4...Flip-flop, 5A, 511.6
...Floating prevention circuit, A person 1 ~ AAI
! 1. Ani-ABII...driver circuit mL*I! ... Inverter, TGAI~T
GAm', T GB t ~T Gin l TG
ss t TG 32 ”” ”・)Transfergate.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
A signal waveform diagram for explaining the effects of the embodiment shown in the figure, FIG. 3 is a conventional signal selection circuit. Hei A 4 Hei

Claims (1)

[Claims] a plurality of pre-stage selection circuits each having a plurality of signal transmission elements each inputting a corresponding input signal to an input terminal and transmitting the input signal to a commonly connected output terminal according to a first control signal; A plurality of pre-stage flip-flops are connected to the output terminals of the respective pre-stage selection circuits and hold the levels of the output signals of these selection circuits according to the output signals of these pre-stage selection circuits, and the input terminals are A rear stage comprising a plurality of signal transmission elements connected to the output terminals of the respective preceding flip-flops in correspondence with each other and transmitting the output signals of the respective preceding flip-flops to the commonly connected output terminals in accordance with a second control signal. a selection circuit, the input terminal is connected to the output terminal of the selection circuit in the subsequent stage, the output terminal is connected to the output terminal, and the level of the output signal of the selection circuit in the subsequent stage is adjusted according to the output signal of the selection circuit in the subsequent stage. 1. A signal selection circuit comprising a rear-stage flip-flop that holds data.