JPH02170250A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the overhead of an operating system OS by detecting an error out of the input data with use of an error detection code produced by an input/output controller and also detecting an error out of the output data with use of an error detection code produced by an input/output processor. CONSTITUTION:An error is detected out of the input data with use of an error detection code produced by an input/output controller 104. When the input data is outputted to a main storage 101 via a data buffer contained in an input/ output processor 102, an error is detected out the output data with use of an error detection code produced by the processor 102. Thus the error is detected at a data fetching port of an input/output channel for the data received from a peripheral device having an optical interface. Thus it is possible to eliminate such overhead where an operating system OS detects an error out of the data sent to the storage 101.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device that transfers data between a main storage device and an input/output control device via an input/output channel,
In particular, the present invention relates to an information processing device equipped with error detection and correction functions for transferred data in an input/output channel such as an optical channel that transfers a large amount of data at high speed.

[Conventional technology]

When data is transferred between the main storage device and the input/output side@device via the input/output channel, there are the following reasons why errors may occur in the pig. As the first cause,
There is a failure in the cable connecting the input/output control device and the input/output channel, and a hardware failure in the connection part on the input/output control device side.

The second cause is a hardware failure within the input/output channel.

The following is a conventional technique for detecting errors in transferred data caused by the above-mentioned causes. 1st
As a means for detecting data errors caused by data errors, errors in the bits constituting one byte are detected by checking the parity bit added to each byte of data on the input/output channel. For the second cause ~ C) (When there is an error in the bits that make up the data such as ECK SUM, add an error detection code to the data that is made up of rules that can detect it.) ], 2, and the receiving side checks whether there is an error in the data using an error detection code.

[Problem to be solved by the invention]

The conventional transfer data error detection method described above has the following problems.

The method of transferring data while checking parity one byte at a time in the first input/output channel cannot be applied to error detection of data that is transferred in large quantities at high speed in units of bits, such as in optical channels.

Furthermore, when transferring a large amount of data at high speed, it is necessary to increase the size of the data buffer possessed by the input/output channel, so there is a tendency to use more memory elements for the data buffer, and memory failures such as soft errors cannot be ignored. Since soft errors may cause errors in multiple bits, data errors cannot be detected only by checking parity.

Second, the normality of the data transferred to the main storage device is
Since O8 checks, there is a large amount of lost time for the CPU.

Third, when O8 finds an error in the data transferred onto main memory, the transfer of said data on the input/output channel has finally been completed. Ninth, if the error in the above data occurs due to a memory failure such as a software error, the state of the hardware will not remain the next time the error occurs, so analyze which part of the hardware is broken. Can not.

Fourth, when an error is detected in the transferred data, the Ilo must be retried from before or from the beginning of the data in which the error was detected. If the amount of data to be transferred is small, this is not a big problem, but if a large amount of data is to be transferred, the loss time due to retrying Ilo will increase, so there is no point in increasing the speed.

[Means to solve the problem]

The information processing device of the present invention comprises means for detecting an error in the data set using an error detection code accompanying the data set received from the input/output control device, and the data set received from the input/output control device. means for generating a first error detection code configured to detect when an error occurs in the bits; and a data buffer in which the input/output channel receives the data set from the input/output controller. means for detecting errors in the data set using the first error detection code when sending the data set to the main storage via the input/output channel, and between the main storage and the input/output control device. data transfer is performed via the input/output channel, and the input/output control device divides the data to be transferred toward the main storage device into a data set of a certain length, and then divides the data of the bits constituting the data set. A second error detection code configured to detect v4b when it is present in the data set is added to each data set, and data transfer is performed.

In addition, an information processing device according to another aspect of the present invention includes means for detecting an error in a data set using an error detection code accompanying the data set received from the input/output control device; Data Sera)
means for generating an error correction code configured to detect and correct an error when an error occurs in the bits constituting the data set; When sending data to the main memory via the data buffer, use the above error correction code to check whether there are any errors in the data set, and if there are too many errors, send the data set output from the data buffer to the main memory. The input/output channel is provided with means for sending a corrected data set to the main storage device when an error is detected, and the input/output control device controls the data transfer between the main storage device and the input/output control device. When there is an error in the bits constituting the data set i for the data set obtained by dividing the data transferred to the main memory Mfl direction by the input/output control device through a channel into a certain length. An error detection code configured to detect this error is added to each data set, and the data is transferred.

Further, an information processing device according to still another invention of the present invention includes:
The error correction code accompanying the data set received from the input/output control device is used to check whether there is an error in the data set, and if there is no error, the data set is stored in the data buffer of the input/output channel, and if there is an error, the data set is stored in the data buffer of the input/output channel. means for correcting the data set using a corresponding error correction code and storing the data set in the data buffer when the data set is received from the input/output control device; When sending data to the main memory, the above error correction code is used to check whether there is an error in the data set, and if there is no error, the data set output from the data buffer is sent to the main memory, and if there is no error, the data set is sent to the main memory. The input/output channel is provided with means for sending a corrected data set to the main storage device when the data is detected, and the input/output channel is used to transfer data between the main storage device and the input/output control device. The input/output control device transfers the data to the main storage device by dividing the data into the data set into a certain length.
An error correction code configured to detect and correct an error in the constituent bits is added to each data set to perform data transfer.

[Effect]

In the present invention, an error detection code created by the input/output control device is used to detect errors in input data, and the input data is output toward the main storage device via a data buffer inside the input/output processing device. An error detection code created within the input/output processing device is then used to detect errors in the output data.

In another aspect of the present invention, an error detection code created by the input/output control device is used to detect errors in input data, and the input data is transferred to the main unit via a data buffer inside the input/output processing device. When the data is output to the storage device, the error detection and correction code created within the input/output processing device is used to check whether or not there are any errors in the output data, and if there are any errors, they are corrected and the main Transfer to storage device.

Still another aspect of the present invention is to detect and correct errors in input data using an error correction code created by the input/output control device, and to transmit the input data to the main unit via a data buffer inside the input/output processing device. When the output data is output to the storage device, the above error correction code is used to check whether or not there is an error in the output data, and if there is an error, it is corrected and transferred to the main storage device.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing an outline of the entire system when the present invention is implemented. In order to facilitate understanding of the present invention, this will be explained first.

In the figure, 101 is a CPU, 102 is an input/output processing unit (IOP), and 103 is a service processor (SVP).
, 104 is an input/output control unit (PCU). and 1
05 is an optical interface, 106 is a data error detection signal, 107 is a data bus between the CPU 101 and 10P 102, 108 is an I10 request, 109 is a channel error detection signal, and 110 is a channel error release signal.

Next, the operation of the system shown in FIG. 1 will be explained.

First, a method for detecting errors in transferred data will be explained.

The input/output processing unit (IOP) 102 is an input/output control unit (P
When a certain length of data and an accompanying error detection code are received from the CU 104 via the optical interface 105, the error detection code is used to check whether there is an error in the data. At this time, when the signal 2- is detected, the input/output processing unit (IOP) 102 sends a data error detection signal 106 to the input/output control unit (PCU) 104, and then the input/output control unit (PCU) 104 sends out the data error detection signal 106. Receive the completion status (data error),
Notify the CPU 101. When the CPU 101 receives a report that there is a data error, it retries the Ilo 9 request 108 that was involved in the data transfer. Additionally, if there is no error in the data received from the input/output control unit (pcU) 104, the input/output processing unit (IOP) 102
is sent to C via the data buffer inside the data 1IOP.
Send to PU101. At this time, an error detection code (hereinafter referred to as EDC) configured to be able to detect when an error occurs in the above data is created inside the entire input/output processing unit (IOP) 102, and the above code is sent to the CPU 101. Before sending data, the data is checked using an error detection code EDC, and if there is no error, data transfer continues. When an error is detected in the data, the input/output processing unit (IOP) 102 interrupts data transfer in the input/output channel, determines that a memory failure has occurred in the data buffer inside the input/output channel,
A channel error detection signal and log information of its input/output channel are sent to the service processor (SVP) 103.

After that, initialize the input/output channels.

and service processor (svp) 103 It
When the s channel error detection signal is received, the input/output processing device determines how many times a channel error occurs on the same channel within a unit time, for example, 8 hours and determines whether the channel error is a friend, and if it is within a certain number of times, the input/output processing device sends communication 110 to cancel the channel error. (IOP)102
Issued on. Furthermore, if a channel error occurs more than a certain number of times, a communication to disconnect the channel is issued.

Next, a method for detecting and correcting errors in transferred data will be explained.

An error detection and correction code (hereinafter referred to as an EDAC) is configured to be able to detect and correct errors when they occur in data received from the input/output control unit (PCU) 104.
) is created inside the input/output processing unit (IOP) 102, and the ED is created before sending the above data to the CPU101.
The AC checks the data, and if there is no error, data transfer continues.

When an error is detected in the data, the input/output processing unit (IOP) 102 corrects the error in the data using EDAC, sends it to the CPU 101, and at the same time stores it in the data buffer inside the input/output processing unit (IOP) 102. The service processor (SVP) determines that a memory failure has occurred.
103 to send a channel error detection signal. Meanwhile, data transfer continues.

Next, the internal circuit configuration and operation of one of the nine channels connected to the input/output processing unit (IOP) 102 will be described with reference to FIGS. 2 and 3.

FIG. 2 is a block diagram showing an embodiment of the present invention, and shows an example of a circuit configuration of an input/output channel for realizing the present invention.

In the figure, 201 is an input data buffer that receives data divided into fixed lengths by the input/output control device and a processing code added thereto through an input/output channel, and holds it; 202 is this input data buffer 201; An error detection circuit 202 detects an error 91 in data held by the input/output control device, and this error detection circuit 202 has means for detecting an error in the data set using an error detection code associated with the data set received from the input/output control device. It consists of 203 is a data error detection signal sent to the input/output control device when the error detection circuit 202 detects that there is an error in the data in the input data buffer 201; 204 is a data buffer; 205 is a signal in the input data buffer 201; This error detection code generation circuit 205 generates an error detection code EDC based on the data of the input/output control device. means for generating an error detection code configured to detect it.

206 is an error detection code buffer that stores the error detection code generated by the error detection code generation circuit 205;
207 is an output data buffer that has the same capacity as the input data buffer 201 and buffers the output data from the data buffer 204; 208 the error detection code EDCi from the vanilla detection code buffer 20B is used to transfer the data buffer 204 to the output data buffer 207; This is an error detection circuit that detects errors in transmitted data, and when an error is detected, it interrupts data transfer of the input/output channel and at the same time interrupts the service processor (s) shown in Figure 1.
vp) 103 to send out a channel error detection signal 209. The error detection circuit 20B and the error detection code buffer 206 use the error detection code when sending the data set received from the input/output control device to the main storage device via the data buffer of the input/output channel. It constitutes means for detecting error Th.

The above two means are provided in the input/output channel, data is transferred between the main storage device and the input/output control device via the input/output channel, and data transferred by the input/output control device toward the main storage device is provided. An error detection code configured to detect errors in the bits that make up the data set is added to each data set by dividing the data set into a certain length. Configured to perform data transfer.

Next, the operation of the input/output channel in the embodiment shown in FIG. 2 will be explained.

First, the input/output channel inputs data divided into fixed lengths by the input/output control device, an error detection code added thereto, and the input data buffer 201 . When the error detection circuit 202 detects an error in the data in the input data buffer 201, the error detection circuit 202 sends a data error detection signal 203 to the input/output control device. The I/O controller then returns Ilo where the data error was detected.
terminate.

When the error detection circuit 202 does not detect an error, the data in the input data box 7a 201 is taken into the data buffer 204, and the error detection code IDC corresponding to the data is generated by the error detection code generation circuit 205. At the same time, the error detection code is added to the error detection code buffer 20B. When the above data is output from the data buffer 204 to the output data buffer 207, the error detection code EDC4 corresponding to the data is also taken out from the error detection code buffer 206.

Next, the error detection circuit 208 takes in all of the data and the error detection code EDC, and checks whether an error has occurred in the data due to a failure in the data buffer 204. At this time, if there is no error, the data buffer 20
4 is sent to the main storage device via the output data buffer 207t, and when an error is detected, the data transfer of the input/output channel is interrupted. and,#
After collecting the log information of the input/output channel, the input/output processing unit (IOP) 102 in FIG. 209 as the service processor (SVP) 10 in FIG.
Report to 3.

FIG. 3 is a block diagram showing another embodiment of the present invention, and is an example of the circuit configuration of input/output channels for realizing the present invention.
It shows.

In FIG. 3, the same reference numerals as in FIG. 2 indicate corresponding parts, and 210 is an error detection and correction code generation circuit that generates an error detection and correction code (EDAC) based on the data in the input data buffer 201. and constitutes means for generating an error correction code configured to be able to detect and correct an error when it occurs in the bits constituting the data set received from the input/output control device.

211 is an error detection and correction code buffer that stores an nine-digit error detection and correction code (EDAC) generated by the error detection and correction code generation circuit 210; 212 is an error detection and correction code (EDAC) from the error detection and correction code buffer 211; This is an error detection and correction circuit that detects and corrects errors in data sent from the data buffer 204 to the output data buffer 207 using the EDAC), and when there is no error, the selector 213 selects the output data buffer 207. When an error is detected, the data from the data buffer 204 is corrected and the selector 213 is set to select the data, and at the same time, the service processor (SvP) 103 in FIG. A channel error detection signal 209 is sent. This error detection and correction circuit 212 is connected to the output data buffer 20.
7 and the selector 213, when sending the data set received from the input/output control device to the main storage device via the data buffer of the input/output channel, the error correction code is used to check for errors in the data set, and the error is detected. When there is no error, the data set outputted from the data buffer is sent to the main storage device, and when an error is detected, the corrected data set is sent to the main storage device.

The input/output channel is equipped with means for detecting errors in the data set using the above two means and an error detection code associated with the data set received from the input/output control device, and the input/output channel is equipped with means for detecting errors in the data set received from the input/output control device. Data transfer between the two is performed via an input/output channel, and the input/output control unit divides the data transferred toward the main memory into a data set of a certain length, and detects an error in the bits that make up the data set. The data transfer is performed by adding an error detection code to each data set, which is configured to detect when an error occurs.

Next, the operation of the input/output channels in the embodiment shown in FIG. 3 will be explained.

First, since the operations of the portions corresponding to the same reference numerals as those in FIG. 2 are completely the same, their explanations will be omitted here.

Next, when the error detection circuit 202 does not detect an error, the data in the input data buffer 201 is taken into the data buffer 204, and the error detection and correction code (EDAC) corresponding to the data is converted into an error detection and correction code. It is generated by the generation circuit 210 and taken into the error detection and correction code buffer 211. Then, when the data is output from the data buffer 204 to the output data cross 77207, the error detection and correction code (EDAC) corresponding to the data is also retrieved from the error detection and correction code buffer 211.

Then, the error detection and correction circuit 212 takes in the data and the error detection and correction code (gDAc) t', and checks whether or not an error has occurred in the data due to a failure in the data buffer 204. At this time, if there is no error, the output data from the data buffer 204 is sent to the main storage device via the output data puffer 207t, and if an error is detected, the error detection and correction circuit 212 performs step 2-detection and correction. Code (EDAC
) to correct the error in the data and send the data to the main memory, and at the same time, the data buffer 204
The fault is reported to the service processor (8VP) 103 in FIG. 1 as a channel error.

FIG. 4 is a system configuration diagram showing another example of the overall outline of the system when the present invention is implemented.

In FIG. 1, the same reference numerals as in FIG. 1 indicate corresponding parts, and 111 is a channel error and optical interface error detection signal.

Next, the operation of the system shown in FIG. 4 will be explained.

First, when the input/output processing unit (IOP) 102 receives a certain length of data and an accompanying error correction code from the input/output control unit (PCU) 104 via the optical interface 105, it determines whether or not there is an error in the data. Check the error using the error correction code. At this time, when an error is detected, the input/output processing unit (IOP) 102 corrects the fixed length data using the corresponding error correction code, and then sends the data via the data buffer inside the input/output processing unit (l0P) 102. At the same time as sending to the CPU 101, a channel error and optical interface error signal 111 is sent to the service processor (SvP) 103.

Additionally, if there is no error in the data received from the input/output control unit (PCU) 104, the input/output processing unit (IO
P) 102 transfers the data to input/output processing unit (IOP) 1
02 Send to CPU 101 via internal data buffer. At this time, in order to check whether an error has occurred in the data due to the data being passed through the data processor, before sending the data to the CPU 101, the data is checked with an error correction code corresponding to the data, and the data is If not, data transfer continues.

And is there a mistake in that data? ) is detected, the input/output processing unit fi (IOP) 102 corrects the error in the data using an error correction code, sends it to the CPU 101, and at the same time detects a memory error in the data buffer inside the input/output processing unit (IOP) 102. It is determined that this has occurred, and sends a channel error and optical interface error detection signal 111 to the service processor (SVP) 203. Meanwhile, data transfer continues.

Chibis Procera? When the (SVP) 203 receives the channel error and optical interface detection signal 111, it determines how many times a channel error has occurred on the same channel within a unit time, for example, 8 hours, and if it is within a certain number of times, it will cancel the channel error. The communication 110 is connected to an input/output processing device (r
OP) Issue to 102. Furthermore, if a channel error occurs more than a certain number of times, a communication is issued to disconnect the channel.

Next, the circuit configuration and operation inside one of the plurality of channels connected to the input/output processing device (IOP) 102 will be explained with reference to FIG.

FIG. 5 is a block diagram showing still another embodiment of the present invention, and shows an example of the circuit configuration of input/output channels for realizing the present invention.

In FIG. 5, the same reference numerals as those in FIG. 3 indicate corresponding parts, and 214 is an error detection and correction circuit that captures the same data at the same time as the input data buffer 201, and corrects errors accompanying the data. A code is used to detect and correct errors in that data. Here, this error detection and correction circuit 214, together with the data buffer 204, uses an error correction code accompanying the data set received from the input/output control device to check whether or not there is an error in the data set, and if there is no error, the data set is is stored in a data buffer of an input/output channel, and when an error occurs, the data set is corrected using a corresponding error correction code and then stored in the data buffer. Also, a data buffer 204, an error detection and correction code buffer 211, and an error detection and correction circuit 212
In addition, when the selector 213 sends the data set received from the input/output control device to the main storage device via the data buffer of the input/output channel, the selector 213 uses an error correction code to check whether or not there is an error in the data set. When there is no error, the data set output from the data buffer is sent to the main storage device, and when an error is detected, the corrected data set is sent to the main storage device.

215 is a selector that receives data from the input data buffer 201 and the error detection and correction circuit 214; when the error detection and correction circuit 214 detects an error in the data received from the input/output control device, an error is detected. and the correction circuit 214 side, and when there is no error, the input data buffer 201 side is selected and sent to the data buffer 204. 216 is a data error detection signal.

The above two means are provided in the input/output channel, data is transferred between the main storage device and the input/output control device via the input/output channel, and all data transferred by the input/output control device toward the main storage device is transferred. An error correction code configured to detect and correct an error in the bits that make up the data set is added to each data set, and the data is divided into data sets of a certain length. Configured to perform the transfer.

Next, the operation of the input/output channels in the embodiment shown in FIG. 5 will be explained.

First, the input/output channel inputs data divided into fixed lengths by the input/output control device and an error correction code added thereto to the entire input data buffer 201 and error detection and correction circuit 214. When the error detection and correction circuit 214 uses the error correction code to detect an error in the data taken in from the input/output control device, the error detection and correction circuit 214 sends the error to the service processor (SVP) 103 in FIG. A data error detection signal 216 is sent out. Then, the selector 215 sends out all select signals to select the error detection and correction circuit 214, and the error detection and correction circuit 214 corrects one error and stores it in the data buffer 204.

When the error detection and correction circuit 214 does not detect an error, the data in the input data buffer 201 is stored in the data buffer 204.

Further, the error correction code loaded by the error detection and correction circuit 214 is always loaded into the error detection and correction code buffer 211 regardless of whether there is an error in the data.

Then, when the data in data buffer 204 is output to output data buffer 207, the error correction code corresponding to that data is also retrieved from error detection and correction code buffer 211. The error detection and correction circuit 212 then takes in the data and the error correction code and checks whether an error has occurred in the data due to a failure in the data buffer 204. At this time, if there is no error, the output data from the data buffer 204 is sent to the main storage device via the output data buffer 20, and if an error is detected, the error detection and correction circuit 212 uses the error correction code. At the same time, the error in the data is corrected and the data is sent to the main storage device, and the service processor (SVP) 103 in FIG.
Report to.

〔Effect of the invention〕

As explained above, the present invention detects all errors in input data using the error detection code created by the input/output control device, and the input data is transferred to the main storage device via the data buffer inside the input/output processing device. By detecting errors in the output data using an error detection code created within the input/output processing device when the data is output, the following effects can be obtained.

That is, first of all, an error in the data from a peripheral device with an optical interface is detected at the data input port of the input/output channel, so there is an overhead of the O8 detecting an error in the data transferred to the main memory. can be omitted. Second, in order to perform high-speed transfer, it is necessary to use a large-capacity data buffer that uses many memory elements, which makes it impossible to ignore memory failures such as transfer errors, but it is necessary to detect data errors that occur through the data buffer. Since it is detected using code, it is possible to prevent data corruption due to memory failure.

When a memory failure occurs in the data buffer inside the third input/output processing unit, the error is detected using the error detection code, data transfer in that input/output channel is interrupted, and then the log information of the seventh channel is collected. and reports it to the service grosser, so data that is useful for analyzing the cause of data errors can be left behind.

Furthermore, the present invention uses an error detection code created by the input/output control device to detect errors in input data, and outputs the input data to the main storage device via a data buffer inside the input/output processing device. The error detection and correction code created within the input/output processing device is then used to check whether there are any errors in the output data, and if there are any errors, they are corrected and transferred to the main memory. , has the following effects. That is, first of all, data from a peripheral device with an optical interface is detected at the data input port of the input/output channel, and errors in the data are detected, so there is no overhead for the O8 to detect errors in the data transferred to the main memory. can be omitted. Second, in order to perform high-speed transfer, it is necessary to use a large-capacity data buffer that uses many memory elements, which makes it impossible to ignore memory failures such as transfer errors. Since the error detection and correction code is used for correction, it is possible to prevent data corruption due to memory failure. Thirdly, even if a memory failure occurs as described above, the error is corrected using the error detection and correction code, so it is possible to eliminate the loss time that is conventionally spent in Ilo connection attempts due to channel errors.

In addition, the present invention detects and corrects all errors in input data using an error correction code created by the input/output control device, and transfers the input data to the main memory via a data buffer inside the input/output processing device. When the output data is output to the main memory, the above error correction code is used to check whether there is an error in the output data, and if there is an error, it is corrected and transferred to the main memory. There is an effect. That is, first of all, when data is transferred from a peripheral device to an input/output channel through an optical interface, errors that occur on the optical interface are detected and corrected at the data input section of the input/output channel. This saves the overhead of O8 retrying its l10t-retries for errors that occurred. Second, in order to perform high-speed transfer, it is necessary to use a large-capacity data buffer using a memory element, which makes it impossible to ignore memory failures caused by transfer errors. Since the error is corrected using an error correction code, it is possible to prevent data corruption due to memory failure. Thirdly, as mentioned above, even if a memory failure occurs, the error is corrected using an error correction code.
Lost time spent trying out glue can be saved.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing an example of the overall system when the present invention is implemented, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 4 is a system configuration diagram showing another example of the overall system when the present invention is implemented, and FIG. 5 is a block diagram showing still another embodiment of the present invention. 101... CPU, 102... Input/output processing device 103... Service processor, 104-...
...Input/output control device, 201...Input data buffer, 202...Error detection circuit, 204...Hot data buffer, 205--e error detection code generation circuit, 206-φ...Error detection code buffer, 207
... Output data buffer, 208 error detection circuit, 210 ... Error detection and correction code generation circuit, 211 ... Error detection and correction code buffer, 212, 2j4 ... - error Detection and correction circuit.

Claims (3)

[Claims] (1) means for detecting an error in a data set using an error detection code associated with the data set received from the input/output control device, and an error in the bits constituting the data set received from the input/output control device; means for generating a first error detection code configured to detect when an error occurs; and a means for generating a first error detection code configured to detect when an error occurs; means for detecting an error in the data set using the first error detection code when sending the data set to the input/output control device; If there is an error in the bits constituting the data set, which is obtained by dividing the data transferred by the input/output control device toward the main storage device through an output channel into a certain length, a second device configured to detect when
An information processing apparatus characterized in that data transfer is performed by adding an error detection code to each data set. (2) means for detecting an error in a data set using an error detection code associated with the data set received from the input/output control device, and an error in the bits constituting the data set received from the input/output control device; When this occurs,
means for generating an error correction code configured to detect and correct the error; The error correction code is used to check whether there is an error in the data set, and if there is no error, the data set output from the data buffer is sent to the main storage device, and if an error is detected, it is corrected. an input/output channel is provided with means for sending a data set to the main storage device, data transfer between the main storage device and the input/output control device is performed via the input/output channel, and the input/output control device An error configured to detect an error in the bits constituting the data set in the data set obtained by dividing the data transferred toward the main storage device by a certain length. An information processing device characterized in that data transfer is performed by adding a detection code to each data set. (3) Using an error correction code accompanying the data set received from the input/output control device, check whether there is an error in the data set, and if there is no error, store the data set in a data buffer possessed by the input/output channel; means for correcting the data set using a corresponding error correction code when an error occurs and storing it in the data buffer; and a data buffer in which the input/output channel holds the data set received from the input/output control device. When sending the data set to the main storage device via the data buffer, the error correction code is used to check whether or not there is an error in the data set, and if there is no error, the data set output from the data buffer is sent to the main storage device; The input/output channel is provided with means for sending a corrected data set to the main storage device when an error is detected, and the input/output control device controls the data transfer between the main storage device and the input/output control device. If there is an error in the bits constituting the data set, which is obtained by dividing the data transferred by the input/output control device toward the main storage device through a channel into a certain length, An information processing apparatus characterized in that an error correction code configured to detect and correct errors is added to each data set before data transfer is performed.