JPH01272149A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce capacitive and inductive coupling and to increase working speed by conducting a layout so that a signal wiring channel is crossed at right angles with a signal conductor just under the signal wiring channel when the signal wiring channel is formed onto a memory section. CONSTITUTION:An input/output circuit section 102 and a logic section 104 are connected by signal wirings 105. A signal wiring channel SC is shaped onto a memory section 103, and these signal wirings 105 are formed onto the signal wiring channel SC. A wiring group 16 represents signal conductors for memory composed of Al wiring layers just under the signal wiring channel SC, data lines or word lines. When the memory section 103 has N-1-Al constitution, the signal bypass wiring channel SC or a memory upper logic signal conductor is composed of Al(N). When a layout is performed so that the word lines and the bypass wirings 105 are crossed at right angles, a cross-talk can be inhibited minimally. When Al(N-1) represents the data lines, a layout is conducted so that Al(N-1) and the bypass wirings 105 consisting of Al(N) are crossed at right angles.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to an ultrahigh-speed LSI having a memory section and a logic section.

[Conventional technology]

For example, common gate array techniques include Takahashi et al.'s British patent GBP 2.104.284 and Yojima's 1986 patent.
U.S. patent application NQ946.6 filed on December 29, 2017
08 issue and magazine “Electronic Materials J July 1986 issue 1
Article by Takahashi from 04-109jj.

This is disclosed in an article by Art Materials et al. on pages 110 to 115 of the same issue of the same magazine.

In recent years, memory LSIs that also have peripheral logic functions (hereinafter referred to as memory LSIs with logic) have been used as LSIs for large-scale calculations, due to the demand for faster computers.

These are introduced in the article by Mano Shimizu in 66-71 and in the article by Unadon et al. in 86-91 Sada in the same issue of the magazine mentioned above.

Furthermore, in the article by Unadon et al., it is stated that the IMa layer A/collar allows the IMa layer A/collar arrangement to pass over the memory section and connect the I10 section and Logic.
A gate array IC connecting the sections is shown.

[Problem a that the invention seeks to solve]

The inventor studied this memory with logic LsI.

However, it has been found that the configuration of a gate array mainly composed of five complementary MOSFET circuits is not sufficient for high-speed applications.

Historically, even at medium speeds, in a configuration where the top layer of memory is randomly bypassed, bypass 11! It has been found that the signal line and the memory signal line (data line or word line) directly below it couple, causing crosstalk.

Furthermore, if the lengths of the signal lines between the input/output circuit and the logic section are set randomly, there is a problem in that delay times differ between multiple signals, resulting in gaps. became clear.

An object of the present invention is to provide a technique that can reduce signal delay time.

Another object of the present invention is to provide a technique that can prevent the occurrence of + and -.

One object of the present invention is to provide a gate array configuration technique with a high degree of freedom.

One object of the present invention is to provide a high-speed gate array with memory.

One object of the present invention is to provide a logic LSI with memory that is suitable for the logic section of a combination machine in a high-speed mainframe.

One object of the present invention is to provide a gate array integrated circuit (IC) having a random access memory (RAM) with low power consumption.

One object of the present invention is to provide a layout method that can reduce cross-dose between a memory section and a signal line passing thereover.

One object of the present invention is to provide a gate array configuration method that can effectively utilize each arrangement layer.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, when providing a signal wiring channel above the memory section, which is used to form signal wiring connecting multiple circuits provided across the memory section, the channel is laid out so that it intersects orthogonally with the signal line directly below. This reduces bulk and inductive coupling.

[For production]

According to the above-mentioned means, it is possible to minimize the length of the No. 1g wiring and to maintain the same length ratio, so that it is possible to reduce the length of the signal. It is possible to reduce the court time and prevent the occurrence of skinny cases.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

In this case, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted in principle. Therefore, unless otherwise specified, parts with the same reference numerals are constructed in the same manner as in the embodiment described.

Furthermore, parts with the same last two digits will be treated the same unless otherwise specified.

(1) Embodiment 1 FIG. 1A is a plan view showing a memory LSI with logic according to Embodiment 1 of the present invention.

As shown in FIG. 1A, in the memory LSI with logic according to the first embodiment, an input/output circuit section 102 is provided around a semiconductor chip 1010 such as a silicon chip. Reference numeral 103 denotes a memory section such as a RAM, which is composed of a memory cell play made up of a large number of memory cells, and in this embodiment, four are provided. Further, in the center of the semiconductor chip 101, a logic section 104 consisting of a large number of gates is provided.

The input/output circuit section 102 and the logic section 103 are connected by an offset channel SC. , these signal distributions 105 are provided on this signal distribution channel SC.

In the memory LSI with logic according to this embodiment, the memory cell array constituting the memory 8103 is arranged, for example, by (total number of wiring layers - 1) layers, and the remaining layer is used as the signal arrangement 105.

In FIG. 1A, the wiring group 106 is a memory signal made of an Al distribution layer directly below the signal wiring channel SC;
That is, in a RAM (Random Access Memory), it is a data block or word.

In other words, the Al wiring layers are arranged in order from the bottom layer to the one closest to the surface of t-def 1: Al(1), , 1(2), Al(3).
) #...AJ(N-1), Al weak, and the process consisting of N layers of Al arrangement is the N-Aσ process.

If it is displayed as an N-Al memory or an N-Al logic circuit, it will be as follows.

Assuming that the memory section 3 has an N-1-AJ configuration.

The signal bypass combination channel SC or the logic signal line above the memory is made of Al(N).

In this case, the word line of this memory mat 3 is A
J(N-1), the word - and the pi-bus wiring m105 are laid out so that they are orthogonal to each other. By doing so, cross talk can be kept to a minimum.

Furthermore, if Al (N-1) is data, it and A
Bypass wiring 8105 consisting of l (to) is laid out in a manner such that they intersect at right angles.

In the above figure, the signal bypass edge 105 and the memory signal edge 106 are shown only on one memory mat, but it goes without saying that these wirings exist on other memory mats as well.

As described above, the signal distribution channel S is provided on the memory section 103.
C is provided, the input/output circuit section 102 and the logic section 104 can be routed without bypassing the memory section 103.
5, it becomes possible to connect the signal wiring 105 to the shortest possible length. Thereby, it is possible to reduce the signal delay time, so that the LSI can operate at high speed. In addition, since the signal wiring 1050 connected to all terminals of the input/output circuit @102 can be made to have the same length, the delay time of the signals of these signal wiring &105 can be made the same, and therefore Occurrence can be prevented. Furthermore, this makes it possible to treat all input and output pins of the LSI equally, so the LSI
The timing design of I becomes easy.

Furthermore, even when the memory LSI with logic according to this embodiment is configured by, for example, a gate array type LSI, the signal wiring channel SC can be defined on the memory section 103 and automatic wiring by automatic design (DA) can be performed. , the same effects as described above can be obtained. Also, in this case,
Signal distribution channel 5C11r, Hakugou! Since it can be used only for wiring 5!105, it is possible to improve the degree of freedom in automatic wiring. Furthermore, since the degree of freedom in setting the positions of the terminals of the input/output circuit section 102 is increased,
It is possible to prevent terminals from being concentrated locally, and as a result, automatic wiring becomes easy.

In this case, each terminal (L
(connected to each input/output pin of the SI package) has one or more wires connected to each input/output pin of the SI package.
05 can be adopted. In that case, D
When performing automatic wiring of signal distribution #105 using A, use D
If the bins on A are proposed to be the end points of the signal distribution Jljl 105 corresponding to the terminals of the input/output circuit section 102, then
It is also possible to adopt a system in which the connection is automatically made to the input/output circuit section.

FIG. 1B is a memo with logic according to the first embodiment of the present invention. FIG. 2 is a plan view showing JLSI.

As shown in FIG. 111B, in the memory LSI with logic according to part (2) of the first embodiment, a memory section 103 is provided in the center of the semiconductor chip 101, and this memory section 103
Also in this embodiment, in which the logic section 104 is provided to surround the memory $
Above 103 a signal distribution channel SC is provided. Then, a logic section 104 is provided on this signal wiring channel SC.
A signal wiring #105 is provided to connect between the two. Therefore, not only the signal wiring 105 between the input/output circuit $102 and the logic section 104, but also the signal wiring 105 between the logic sections 104 can be minimized and the length ratio can be minimized, and therefore the signal delay time can be reduced and It is possible to prevent the occurrence of skimping.

In this case as well, crosstalk can be avoided by orthogonally laying out the memory signal of the memory mat 103, that is, the word line or bit line (data), and the bypass signal port 105, as in the case (2) of the first embodiment. can be minimized.

The present invention has been specifically explained above based on examples, but
The present invention is not limited to the above-described embodiments, and may be modified from time to time without departing from the spirit thereof.

For example, the shape, arrangement, etc. of the memory section 103 and the logic section 104 in the semiconductor chip 101 are different from those in the above-mentioned embodiment I.
The shape, power distribution, etc. can be different from II. Also,
The present invention can be applied to various semiconductor integrated circuit devices having a memory section and a logic section.

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it is possible to reduce the signal delay time and prevent the occurrence of skid &-.

(2) Example 2 This example describes a more fraudulent design method that can be applied to each specific layout in Example 1 regarding the layout on the front rainbow chip.

In the following, the drawings of the above embodiment 1 will not necessarily be referred to, but the present embodiment 2 constitutes an improvement over the above embodiment 1 or a part thereof.

The MZA diagram is a layout on the main surface of the chip corresponding to the mlA diagram. In the same figure, 201 is S1 of 15 dragon angles.
Semiconductor chips 202a to 202d made of single crystal substrates each have an input-only I1 of about 20 to 100 a in the input/output circuit section.
0 cell, output-only I10 cell, input/output dual-purpose I10 cell, or input/output dual-purpose I10 cell (hereinafter, these are collectively referred to as
203+a
and 203b is SRAM (static random
A memory area 204 consisting of an access memory) and its peripheral circuits is a logic area 20 constituting a gate array.
5 is a false signal line connecting the input/output circuit area 202 and the logic area 204, 206a is a memory signal line, that is, a word line, and 207c is another memory signal line, that is, a bit line (data). Each of these 100 issues 8205
, 206 and 207 are present in each memory mat or other wiring channel region as needed or as a matter of course, but are omitted here for drawing reasons.

Further, 208&~208h are SRAM memory cell mats, 209a~209h are sense circuits consisting of differential amplifiers for reading information in these memory mats, and 210a~210h are memory cell mats for each memory mat. data decoder circuit.

212a to 212h are word drivers, 2131 to 212h are word drivers;
213h is a word decoder or other word 4 control circuit, and 214& and b are macro cell areas for configuring peripheral circuits such as buffers of the respective memories.

FIG. 2B is an explanatory diagram showing an enlarged main part of the circuit system shown in FIG. 2A, and is a schematic layout diagram showing more specific points of improvement. In the same figure, DLa, DLa, D
Lb, DLb, ==DLd, DLd are complementary data pairs, 201 is a chip, 204 is a logic circuit area (gate array area), and 205a to 205d are logic circuit wirings running above the memory. , ZO6 is a word line, 211a to 211d are differential sense amplifiers for comparing the complementary data pairs and detecting data stored in the memory cell, CD, CD is common data@, 230 is the main amplifier.

231 is a column switch group, 215 is a buffer circuit provided in the macro cell 214, and 216a to 216
d is an I10 cell for exchanging signals with the logic section 204 and the outside, and is formed within the input/output circuit area.

Here, peripheral circuits such as a memory mat, a decoder, and macro cells are composed of AJ(1) to 1(N-1), so the gate array part 204 and I10 cells 216a to
Line 18, such as 216d, can be configured freely using Al (Nl), so it is designed to pass over the memory in an almost straight line over the entire area on the memory area 203a or 203b, so as to minimize the signal gap. It can be done.

(3) Embodiment 3 This embodiment applies Embodiments 1 to 2 regarding the layout to a device process related to a logic module, which applies Examples 1 to 2 regarding the layout to a logic control operation section of a main 7-frame combination. First, regarding this module, the chip of the present invention, other chips, and a mother chip on which they are mounted will be explained.

As shown in FIG. 1!3A, the semiconductor device 11301 includes a mother chip (mounting substrate) 304 on which a plurality of semiconductor chips 302 and 303 are mounted, and a base substrate 305. It is sealed with a crushed body 307 and a sealing cap 306.

Each of the semiconductor chips 302 and 303 has a protruding electrode 308
It is installed on the mother chip 304 with the intervening. That is, each of the semiconductor chips 302 and 303 is mounted on the mother chip 304 by a face-down bonding method (or CCB method). mother chip 30
4 includes a semiconductor chip (logic L) having one logic function, as shown in FIG. 3B (plan view of the mother chip).
SI) 302 and a semiconductor chip (memory LSI) 303 having eight memory functions. Since the semiconductor element forming circuit of each of the semiconductor chips 302 and 303 is configured to face the mounting surface of the mother chip 304, each of the semiconductor chips 302 and 303 shown in FIG. 3B faces the semiconductor element forming surface. The back side is visible.

As shown in FIG. 3B, the semiconductor chip (logic LSI) 302 has a logic circuit section Log in the center.

lc is located. Logic circuit @Logic part is 1
Basic cells each made up of one or more semiconductor elements are regularly arranged in a matrix. The basic cell and the semiconductor elements of the basic cell are connected by multiple layers of wiring to form a predetermined logic circuit. In other words, the semiconductor chip 302 uses a so-called gate array method to construct a predetermined logic search function.
The semiconductor chip 302 of this embodiment is composed of three wiring layers, with the first and second layer wiring mainly forming a predetermined logic circuit, and the third layer wiring mainly forming a predetermined logic circuit. Used as power wiring. The semiconductor elements constituting the basic cells of the logic circuit section LOglc are bipolar transistors.

In the peripheral portion of the semiconductor chip 3020, an input circuit Dins
A peripheral circuit consisting of an output circuit Dout and a source circuit VC is arranged. Input circuit D in s Output circuit D
The semiconductor elements constituting each of the source circuits VC are:
Similar to the logic circuit section Log1c, it is mainly connected by the first layer and the second layer wiring.

The semiconductor elements that make up the peripheral circuit are the logic circuit section Logic.
Similarly, it is a bipolar transistor.

a logic circuit section Logic of the semiconductor chip 302;

The specific structure of the bipolar transistors constituting each of the peripheral circuits is shown in FIG. 3C (a sectional view of the main part).

As shown in FIG. 3C, the bipolar transistor is formed on the main surface of a p'' type semiconductor substrate 302A made of single crystal silicon. The bipolar transistor is electrically isolated from other regions by an isolation region made up of a semiconductor substrate 302A, a p-type semiconductor region 302D, and an element isolation insulating film 302E. A semiconductor region 302D is formed between a semiconductor substrate 302A and an n-W epitaxial layer 302B grown on its narrow surface. In other words, the semiconductor region 302D is a buried semiconductor region. The element isolation insulating film 302E is formed on the main surface of the epitaxial layer 302B so as to reach the semiconductor region 302D. The element isolation barrier @g302g is formed of a silicon oxide film obtained by oxidizing the main surface of the epitaxial layer 302B.

The bipolar transistor has an n-type; rectifier region Ca
np which also serves as the P type base region B and the n type emitter region E
It is n-type and has one layer.

The collector region C is an n+ type semiconductor region 302C.

It is composed of epitaxial In 302B and a potential raising n-type semiconductor region 302F. Semiconductor area 30
2C is the semiconductor substrate 302 similar to the semiconductor region 302D.
This is a buried semiconductor region provided between the person and the epitaxial layer 302B. The semiconductor region 302F is provided on the main surface of the epitaxial layer 302B so as to reach the semiconductor region 30'2C. The semiconductor region 302F of the collector area C is connected to the IJ (1/Ith wiring 302N) through the connection hole 302M formed in the layer terminal @J4302L.
It is made of aluminum group to which u or and silicon is added. Cu reduces stress migration.

Sl reduces the occurrence of alloy spikes.

The base region B is a p-type semiconductor region 3 provided on the main surface of the epitaxial layer 302B constituting the collector region C.
It is composed of 02G. A wiring 302N is connected to the semiconductor region 302G, which is the base region B.

The emitter region E is provided on the main surface of the semiconductor region 302G constituting the space region B.
It is composed of 02H. An ivy electrode 302K is connected to a semiconductor region 302H, which is an iP3 edge film 302I, through a connection hole 302J formed in an iP3 edge film 302I. The emitter Kameken 302 contains n-type impurities (P or Am).
) is formed of a polycrystalline silicon 1c film into which is introduced. The semiconductor region 302H has the emitter %i, ta, 302K
Although not shown, the emitter voltage iH! is formed by the n-type impurity introduced into the semiconductor region 302G being diffused into the semiconductor region 302G. The polycrystalline silicon film forming the 302K layer is used to form wiring and resistor elements in other areas. Similarly, a wiring 302N is connected to the vine electrode 302K.

The upper layer of the m1th layer 302N is a glabellar insulation film 30.
A second layer wiring 302Q is provided with 20 interposed therebetween. Furthermore, the glabella insulation m302R is interposed on the upper layer of the second layer wiring 302Q, and the third layer arrangement 15302
A T is provided.

Like both speeds, the semiconductor chip 302 has a three-layer structure. Wiring 302N and layout! 302Q is connected through a connection hole 302P formed in the interlayer insulating film 3020. What is layout@302Q and layout IIaozr?
The connection is made through a connection hole 302S formed in an interlayer insulating film 302H.

The wirings 302Q and 302T are interlayer insulation M302L and 3020 formed of the same material as the wiring 302N, respectively.
．． Each of 302H is formed mainly of a silicon oxide film.

The upper layer of the 3rd layer - 302T is Pudgebage Adventure 1
1i302U is provided. Adventures in Pudgebage [3
02U is formed of, for example, a silicon nitride film deposited by plasma CVD.

The third layer wiring 302T is a logic circuit WLogic drawn out from each circuit of the peripheral circuit and from each circuit of the peripheral circuit.
An external terminal (ponding pad) BP is formed on the top. ! As shown in the I3C diagram, an opening 302v is formed in the badge base film 302U on the wiring 302T which becomes the external terminal BP. Arrangement 1 which is the outer S terminal BP
A barrier metal layer 302W is provided on 302T through opening 302V. The barrier metal layer 302W is composed of a composite film in which Cr, Cu, and Au are sequentially laminated. Cr is formed with a thickness of about 1200 to 1500 (A). Cu is formed to have a thickness of about 5000 to 7000 (A). Au is formed to a thickness of about 700 to 1100 (A). The wiring 302T, which is the external terminal BP, is connected to the mother chip 302 with a barrier metal layer 302W interposed therebetween.
It is configured such that one end portion of the protruding electrode 30g formed on the side is connected.

The semiconductor chip (memory LSI) 303 is composed of an SRAM. The semiconductor chip 303 is.

As shown in FIG. 3B, the memory cell array M is located in the central part.
ARY is placed. The memory cell array MARY has '4I memory cells arranged in rows and columns. The memory cell, as shown in FIG. 3D (equivalent circuit diagram of the memory cell), is a shut-key barrier type composed of bipolar transistors. This memory cell is
Extending in the column direction - Word control WL and data control line HL
, complementary digits) &DL, and DL. That is, the memory cell consists of two parasitic npn bipolar transistors Tr1, two reverse npnW bipolar transistors Tr@ski, a fixed key barrier diode SBD, and two memory cell resistors RM(,2 It is composed of low resistance RL.

As shown in FIG. 3B, peripheral circuits including an input circuit D 1 n , an output circuit Douts, an address buffer circuit AB, an X driver circuit XD, and a Y driver circuit YD are arranged around the semiconductor chip 3030, as shown in FIG. 3B. has been done. The semiconductor elements constituting each circuit of this peripheral circuit are bipolar transistors (not shown).
Bipolar transistor and semiconductor chip (logic LSI) 3 forming the semiconductor chip (memory LSI) 303
It has substantially the same structure as the bipolar transistor constituting 02.

The semiconductor chip 303 has a two-layer I#1 structure (two aluminum wirings). External terminal BP is 211
Consists of eye wiring. External terminal BP is configured on each peripheral circuit.

External terminal BP connects memory cell array M
Memory cells that are not configured on RY and are made of bipolar transistors are more resistant to α-ray soft errors than memory cells that are configured with MISFETs, but in order to improve the margin against soft errors, the external terminal BP is connected to the memory cell playback. Do not configure on MARY.

The mother chip 304 is configured as shown in FIGS. 3B and 3E (cross-sectional views of main parts of the mother chip). ! For example, the day chip 304 has a first-layer arrangement on the surface of a silicon substrate 304A with a glabella insulating film 304B interposed therebetween.
304C is provided. The silicon substrate 304A has the characteristics that there is no difference in coefficient of thermal expansion between the semiconductor chips (single crystal silicon substrate 302A) 302 and 303 and good thermal conductivity.The one-layer insulating film 304B is the silicon substrate 304A. The main surface is made of an oxidized silicon oxide film. The groove 304c is made of an aluminum film doped with aluminum or Si.

On the first layer arrangement 5I304c is an interlayer insulating film 304D.
and 304B, the second layer arrangement 1lIj304
G is provided. The wiring 304G is made of substantially the same material as the wiring 304C. Wiring 304G and wiring #
304C is an interlayer disconnection, which is *a through the connection hole 304F formed in fi 304D and 304E. j-
Kunno1t'i#! The layer 304D is mainly used as an etching stopper layer, and is made of, for example, silicon nitride deposited by plasma CVD. The interlayer insulating film 304E is mainly configured to electrically isolate the wiring #1+304C and the wiring 304G, and is formed of, for example, a silicon oxide film deposited by sputtering. ! ! The via hole 304F is formed by performing isotropic wet etching on the interlayer insulation fit 304E and performing anisotropic dry etching on the interlayer insulation film 304D.

Pudge page seals fi 304H and 304 are provided on the 21st wiring 304Cx. Pudgebage 304H is made of silicon nitride, for example. Badge page board 4304I is formed of, for example, a silicon oxide film.

2nd N! The i-th wiring 304G constitutes an internal terminal P1 in a predetermined area in the center of the mother chip 304, as shown in FIG. 3E. Internal terminal P
- is the external terminal BP of each of the semiconductor chips 302 and 303
It is configured to connect with the protrusion electrode 308 interposed therebetween. A barrier metal 4304K is provided on the wiring 5304G constituting the internal terminal Pl through the opening 304J formed in the base plate 304H and 304I.The barrier metal layer 304 has the semiconductor chips 302, 303 ' has substantially the same structure as the barrier metal layer 302W provided on the surface of each external terminal BP (
It is composed of A u / Cu / Cr).

The opening 304J is formed by isotropic wet etching. A protrusion pole 308 is provided on the barrier metal layer 304 .

The second layer wiring 304G constitutes an external terminal P in a predetermined area around the mother chip 304. An opening $304L formed in the badge page stamps 114304H and 304I is provided on the arrangement 304G constituting the external terminal P. Opening 11 (3
04L is configured to connect a bonding wire 312 to a wiring 304G forming an external terminal P.

The opening 304L is formed by subjecting the badge page carbon film 304 to isotropic wet etching.

As will be described in detail later, the protruding electrodes 308 are formed using a lift-off technique by interposing a barrier metal layer 304K on the arrangement 41304G that constitutes the 114th child P of the mother chip 304. In other words, there is a protrusion 1 on the internal terminal Pl.
The other end of the pole 308 is connected. The protruding electrode 308 is formed of solder (solder protruding electrode).

The mother chip 304 is mounted on the paste substrate 305 with an adhesive metal layer 309 interposed therebetween, as shown in FIG. 3A. The pace substrate 305 is made of, for example, a silicon carbide substrate, and has the characteristics of having a small coefficient of thermal expansion with respect to the mother chip 304 and good heat conduction. The adhesive metal layer 309 is made of, for example, an Au-8n alloy.

A lead 310 is provided at the periphery of the pace substrate 305 and between the pace substrate 305 and the frame 307.

The lead 310 is fixed to each of the pace substrate 305 and the frame 307 with a low melting point glass l311. The lead 310 is made of, for example, F.--Ni alloy (42 alloy).

The inner lead part of the lead 310 has bonding wire 3!2 interposed! External terminal P of Zerchig 304,
It is connected to the wiring 304G.

The bonding wire 312 is made of aluminum. The bonding wire 312 is connected to each of the wirings 304G constituting the inner lead portion of the lead 310 and the external terminal P of the mother chip 304 by ultrasonic bonding.

Equipped with semiconductor chips 302 and 303! Boo tip 304. The inner lead portion of the lead 310 and the bonding wire 312 are hermetically sealed with a sealing material 314. For example, silicone gel is used as the sealing material 314. Silicone gel is formed by the botting method.

The pace substrate 305 and the frame body 307 are made of low melting point glass 311
The frame body 307 and the sealing cap 306 are fixed with an adhesive 313. For example, silicone rubber is used as the adhesive 313.

The frame body 307 is made of, for example, mullite.

The sealing cap 306 is made of ceramic material, for example.

A radiation fin 316 is provided on the back surface of the base substrate 305 (the back surface facing the mounting surface of the mother chip 304) with an adhesive 315 interposed therebetween. The radiation fins 316 are attached to radiate heat generated in each of the semiconductor chips 302 and 303 to the outside. For example, silicone rubber is used as the adhesive 315.

The outer lead portion of the lead 310 is formed into an L-shape. Although not shown, a solder layer is provided on the surface of this actor lead portion. The outer lead portion is connected to a wiring board (baby board) 317.

Next, the mother chip 304 of the semiconductor device fiW301
A method for forming the protruding electrode 308 will be briefly explained using FIGS. 3F to 30 (cross-sectional views of main parts shown for each manufacturing process).

First, a silicon substrate 304A is prepared. Thereafter, an interlayer insulation film 304D forming an interlayer insulation 111304B on the entire surface of the silicon substrate 304 is an interlayer insulation film 304D formed of a silicon oxide film formed by oxidizing the surface of the silicon substrate 304.
04B is formed to have a thickness of, for example, about 1.1 to 1.3 [μm].

Next, as shown in FIG. 3F, a first layer wiring 304C is formed on the interlayer insulating film 304B. The wiring 304C is formed of an aluminum (A/-8l) film deposited by sputtering, and has a thickness of about t,s to 2.2 (am). Patterning of 304C is performed by isotropic wet etching. In other words, the wiring 304C is 11
11 is formed so that the stepped shape of the wall can be relaxed and the step coverage of the upper layer wiring can be improved.

Next, an interlayer insulating film 3 is formed over the entire surface of the substrate including the top of the wiring 304C.
04D and 304E are laminated in a j-th order.

Since the interlayer insulating film 304D is used as an etching stopper layer, the interlayer insulating film 304D is formed to have an etching rate different from that of the layer Q, @304B.
For example, the interlayer insulation 5304g, which is formed of a silicon nitride film deposited by plasma CVD and has a film thickness of about 0.4 to 0.6 [μm], sufficiently electrically connects the wiring 304C and the upper layer wiring. Designed to be separable. The NI interlayer 304E is formed of a silicon oxide film deposited by sputtering, for example, and has a thickness of about 3.4 to 3.6 [μml].

Next, as shown in Fig. 3G, the layer height kN304°D and
04E is removed to form a connection hole 304F. Connection hole 3
04F can be formed by performing isotropic wet etching on the first interlayer insulation film 1304E and performing anisotropic dry etching on the interlayer insulation film 304D. When forming this connection hole 304F, the interlayer insulating film 304F
Since it is used as an etching stopper layer for D7,
Etching control of the layer I unitary film 304E with a sufficiently uniform film thickness can be easily achieved. Further, since the connection hole 304F is formed by etching the interlayer insulating film 304E by isotropic wet etching, the step shape can be relaxed and the step coverage of the upper layer wiring can be improved.

Next, as shown in FIG. 3H, the interlayer insulating film 304E is connected to the arrangement 1304c through the connection hole 304F.
A second layer wiring 304G is formed thereon. Wiring 304G
is not only the wiring that transmits signals, but also the mother chip 304.
An internal terminal Pi and an external terminal P are formed respectively. The wiring 304G is similar to the wiring 3040,
Jll: Laminated aluminum (Al-8t) by sputtering
) is formed with a film thickness of about 2.4 to 2.6 [μm].

Delivery @! 304G is patterned by isotropic wet etching.

Next, a badge page mark m304H is formed on the entire surface of the board including on the wiring 304G. Pudgebage attack film 304H
is formed, for example, from a silicon nitride film deposited by Goodsma CVD, and has a thickness of about 0.4 to 0.6 [μm].

Next, on the wiring 304G and on the pad page binding film 304H.
Padge page coating film 304 I 1 on the entire surface of the substrate including the top
r formationf. The padge base 304I is formed of, for example, a silicon oxide film deposited by sputtering, and is formed from 3.4 to 3.
It is formed with a film thickness of about 6 [μm]. Thereafter, as shown in FIG. 3I, the pad page etchant film 304I on the internal terminal P1 formation region of the wiring 304G is removed, and the opening 304 is removed.
Form J.

The opening 304J is formed by performing isotropic wet etching on the Padgepage etching film 304.

Next, it is opened by padge page w 7) M 304 Ht'' trial etching.

Next, as shown in FIG. 3J, a barrier metal layer 304K is formed inside the opening 304J on the internal terminal Pl formation region of the interconnection 8304G.

The barrier metal layer 304 is formed by forming a j-order layer of Cr, Cu, and Au. Cr is formed by vapor deposition or sputtering, and is formed to have a film thickness of about 1200 to 1500 (A). C
u is formed by vapor deposition or sputtering, and is 5000 to 7000
4u is formed by vapor deposition or sputtering, and is formed to a thickness of about 700 to 1100[λ].For barrier metal/11304, for example, isotropic wet etching and Patterning is performed in combination with anisotropic dry etching.

Next, thirdly, as shown in the figure, the external terminal P of the wiring 304G and the padding film 304I on the formation area are removed to form an opening 304L.

The opening 304L has substantially the same structure as the opening 304J. That is, the opening 304L is formed by performing isotropic wet etching on the padding layer 304I.

Next, although not shown, a back grinding process is performed on the back surface of the silicon substrate 304, and a barrier metal layer is formed on the surface that has been subjected to this process. This barrier metal layer has substantially the same structure as the barrier metal layer 304. After that, Au is vapor-deposited on the surface of the barrier metal layer on the back side of the silicon substrate 304A. This Auj- is mother chip 3
Adhesive metal layer 30 when fixing 04 to the base substrate 305
It becomes part of 9.

Next, a lift-off is performed to form the protruding electrodes 308. That is, first, as shown in FIG.
04 protruding electrode (conductor 1) 308 is not formed on the pad page conductor M304I. It is formed in the area shown in FIG. That is, in the area where the semiconductor chip (logic LSI) 302 is mounted, the protruding electrodes 308 are formed in the logic circuit area Loglc and the peripheral circuit area, so those areas are excluded and the padding area between the two areas is removed. Membrane 304I
An Ijl resist layer 318 is formed thereon. In the region where the semiconductor chip (memory LSI) 303 is mounted, a protruding electrode 308 is formed in the peripheral circuit region, so excluding that region, a second resist film 318 is formed on the padding base plate 304I in the memory cell array MARY region. is formed. Since the protruding electrodes 308 are not formed in areas where the semiconductor chips 302 and 303 are not mounted,
A second resist film 318 is formed on the entire area of the padding film 304.

The WXl resist waist 318 is formed of a photosensitive resist film, for example, polymethyl methacrylate (monomer type), and has a resistance of 1.0
Formed with a film thickness of ~6.0 [μm].

After applying 114318 to the entire surface of the substrate,
By baking at a temperature of approximately 120 T, exposing a predetermined portion to light, and developing, only the region where the protruding electrode 308 is not formed remains.

Next, as shown in FIG. 3M, a second resist is applied to the entire surface of the substrate including the badge page sealing film 304I, which is the area where the protrusions t&308 are to be formed, and the second resist layer 318, which is the area where the protrusion electrodes 308 are not to be formed. [Form 319. 1!319 is formed with a two-layer structure in which a film resist film 319B is laminated on the surface of a base resist film 319A.

Base resist) Ii & 419A is a step shape formed by wiring 304C and wiring 304G, connection hole 304F and opening 3
Even if there is a step shape at the end of 1!318, the film resist 11g
319B is formed so as to be brought into close contact with the base. In other words, the underlying resist group 319A is the film resist i
l! 5 to prevent 319B from peeling off from the base. The base resist 1319A is formed of a photosensitive resist film made of the same material as the first resist film 318, such as polymethyl methacrylate, and has a thickness of 3.4 to 3.6 [μm].
Form the film with a thickness of approximately The base resist (M319A) can be formed by coating the entire surface of the substrate and then baking it at a temperature of approximately 120° C.).

film ratio) ff1319 B is protrusion-pole 308
The film is thick to obtain the required height.

The film resist film 319B is made of resist 1i318.
．． A photosensitive resist film made of the same material as each of the base resist films 319A, for example, polymethyl methacrylate;
Although not shown, a cover film (not shown) is formed on the surface of the film resist film 319B after exposure of the film resist film 319B and before development. The film resist film 319B has a film thickness of about 20 (μm).
It is formed by thermocompression bonding on the surface of the base resist [319A].

Next, as shown in the IE3N diagram, the conduit 2 resist film 319
A first opening 320A is formed in the part where the protruding electrode 308 is formed (internal terminal P, upper), and a w42 resist)
A second opening 320B for forming a dummy protruding electrode 308A is formed in a region of M319 where the protruding electrode 308 is not formed (on the Ml resist film 318). First opening 32
0 A, each of the second opening 320B is 2 registers) 1
It can be formed by exposing 1319 to light and then developing it. 1st rIJA opening 320A, for example 20
They are formed at intervals of about 0 to 300 [μm]. The Ml openings 320A forming the protruding electrodes 308 are formed at a high density in order to provide multiple terminals. On the other hand, the second opening 3
20B are formed at intervals equal to or larger than the first openings 320A. The 8g2 openings 320B do not need to be formed at a higher density than the first openings 320A, and are preferably formed at slightly larger intervals in order to improve manufacturing yield. However, the second resist cost $318. In order to ensure that each of the second resist films 319 is peeled off and that peeling defects do not occur, at least one first opening 320A or one second opening 3 must be formed within a range of approximately 1 (tj).
20B is provided.

Next, as shown in FIG. 30, the entire surface of the substrate on the second resist y319 is covered with gold! A film (conductor film) 308B is formed. Metal i308B uses solder deposited by vapor deposition. The solder is, for example, 95 [wt%] PB and 5 [1%]
It is formed with Sn. For example, metal M308 B is 15~
The second resist [31
In the first opening 320A of 9, a protruding electrode Ji308 can be formed on the surface of the barrier metal layer 304 on the wiring WiJ304G, which is the internal terminal P1. mark (partially omitted)
(indicated by the symbol). In addition, in the second opening 320B of the second resistor [319] (the protruding electrode 3
A dummy protruding electrode 308A can be formed on the area where 08 is not formed) and 318. The dummy protrusion % and the pole 308A are marked with * (partially omitted) in Figure 3P.
(indicated by the symbol).

Next, the second regime), [319, first resist film 318
Remove each. This removal is performed using a stripping solution such as methylene chloride.If necessary, ultrasonic treatment may be performed during the removal.The underlying resist film 31 of the second resist film 319
9A, the film resist ff1319B, and the first resist film 318 are each formed of the same photosensitive resist) M, so that they can be peeled off in a second peeling process. Since the first openings 320A are densely formed in the area where the protruding electrodes 308 are to be formed, the stripping liquid is sufficiently applied to the second resist film 3 as shown by the arrow A in FIG.
19 can be infiltrated. In addition, the protruding electrode 308
In the region where the dummy protruding electrode 308A is not formed, the 'r$2 opening 320B is the first opening 320A.
Since the second resist film 319 and the first resist film 318 are formed as densely as or close to it, the stripping liquid can sufficiently penetrate into the second resist film 319 and the first resist film 318, as shown by the arrow A in FIG.

This second resist film 319. By removing each of the first resist films 318, the wiring 830, which is the internal terminal P,
4. With the protrusion electrode 308 formed on the barrier metal N304K remaining on the first resist film 318, the dummy protrusion-1 pole 308A and the second
The metal film 308B on the resist layer 319 can be removed.

After forming the protruding electrodes 308, the completed mother chip 304 is shown in FIG. 3E, with the protruding electrodes 308 subjected to reflow. The reflow is performed at a temperature of about 340 to 350 (°C).

In this way, one protruding electrode (
A method for manufacturing a semiconductor device 301 in which the mother chip 3040 is formed using a 7-to-7 technique.
A second resist film 318 is formed on the surface where the protruding electrodes 308 are not formed, and a second resist film 319 is formed on the entire surface of the mother chip 304 including on this IL resist film 318 and on the region where the protruding electrodes 308 are formed. This second resist! The protruding electrode 30 is formed in the formation area of the protruding electrode 308 of 319.
8, and a second opening 320B for forming a dummy protruding electrode (dummy conductor M) 308A in a region where the protruding electrode 308 of the second resist 319 is not formed; Said first opening 320A
On the surface of the mother chip 304 inside, the second opening 32
On the first resist film 318 in 0B and on the second regime) XI
Including on i319! A gold J4 film 308B is deposited on the entire surface of the boot chip 304, and the second resist film 319. Each of the second resist films 318 is removed, the protrusion 11L pole 308 inside the first opening 320 remains, and the metal film 308B and the third resist film 308B on the second resist film 319 and the third resist film 318 are removed.
By removing the dummy protruding electrode 308A on 8, a second opening 320B for forming the dummy protruding electrode 308A is formed in the region where the protruding electrode 308 is not formed, and this second opening 320B is formed in the area where the protruding electrode 308 is not formed. Since the stripping liquid was actively infiltrated into the second resist film 319 through 320B, it is possible to improve the stripping property of the region of the w12 resist m319 where the protruding electrode 308 is not formed.

Further, in addition to the above means, the first Lujist film 318,
2nd regime) Each of the yi319 is formed of the same material, and after the metal film 308B is deposited, the Wlugist "M318,1
By peeling and removing each of the No. 12 resist films 319 in the same process, in addition to the above-mentioned effects, the second resist film 318 can be removed in the process of removing the second resist film 319. The manufacturing process of the semiconductor device 301 can be reduced by the amount equivalent to the peeling process of peeling off.

In addition, by forming the base resist with excellent fluidity and the second resist with a two-layer structure in which a film resist 9319B is formed on 319A) fi319, the step shape etc. caused by the formation of the resist resist m318 can be alleviated. , since it is possible to improve the adhesion between the base and film resin [319B], before and after vapor deposition of metal lm308B,
Alternatively, the second resist film 319 and the second resist film 319 can be removed by film resistance before the step of removing the second resist film 319, thereby preventing peeling defects such as peeling of the second resist film 319 and improving manufacturing yield.

Next, the assembly process of the semiconductor device 301 will be briefly explained using Figures MaQ to 3T (schematic cross-sectional views of the semiconductor device shown for each assembly process).

First, as shown in FIG. 3Q, the semiconductor chip 302.3
03 on the mother chip 304 (chip mount) with the protrusions interposed between the poles 308.
are formed on the mother chip 304 side as described above, and by subjecting the protruding electrodes 308 to reflow, each of the semiconductor chips 302 and 303 can be connected and fixed to the mother chip 304. Reflow is 3 as mentioned above.
It is carried out at a temperature of about 40 to 350°C (l).

Next, the mother chip 304 is mounted on the pace board 305. With pace board 305! It is fixed to the boot chip 304 by an adhesive metal layer 309.

The adhesive metal layer 309 uses Au-3n alloy as described above.

Next, as shown in FIG. 3R, a frame 307 is attached to the periphery of the base substrate 305. When attaching the frame 307, the leads 310 are attached between the base substrate 305 and the frame 307 at the same time. The frame 307 and leads 310 are attached to the base substrate 305 using low-melting glass 311.

Next, the external terminal P8 of the mother chip 304 and the lead 31
The bonding wire 312 is connected to the inner lead portion of No. 0 through a bonding wire 312. Bonding is performed using an ultrasonic bonding method.

Next, as shown in FIG. 35, the mother tip 304 within the area defined by the frame 307. Semiconductor chip 302, 3
03. The bonding wire 312 is hermetically sealed with a sealing material 314. The sealant 314 uses silicone gel.

The silicone gel is applied by a botting method and then cured by baking.

Next, an adhesive 313 is applied to the frame 307.

Attach the sealing cap 306. When attaching the sealing cap 306, the inside of the cavity formed by the pace substrate 305, the frame 307, and the sealing cap 306 is kept in a vacuum state.

Next, a solder layer is formed on the surface of the outer lead portion of the lead 310. This solder layer is formed by dipping it in a solder bath.

Next, as shown in FIG. 3T, the outer lead portion of the lead 310 is cut from the frame of the lead frame, and
Mold into a predetermined shape.

Next, the heat dissipation fins 316 are attached to the base surface of the base substrate 3050 with the ffW agent 315 interposed therebetween. By attaching the heat radiation fins 316, the semiconductor device 301 is completed.

Next, the semiconductor device 301 is mounted on the wiring board 317 as shown in FIG. 3A.

The semiconductor device of the present invention is manufactured by the above-described chip manufacturing process and electrode formation process, and is used by being mounted on the above-described mother chip.

In other words, in the previous example, the logic LSI and the memory LSI used by it were mounted on a common mother chip, but in fields where ffI information is exchanged at higher speeds, this arrangement is disadvantageous. It may happen.

Therefore, in the example below, instead of this, the logic circuit is divided and the memory L, which exchanges a lot of data, is
An example will be described in which they are each mixed on the SI, mounted on the same mother chip as before, and packaged in the same manner.

This embodiment uses bipolar transistors and complementary MIS.
Mixed type semiconductor chip (B
This is an embodiment of the present invention in which the present invention is applied to a semiconductor chip having memory capacity.

The structure of a semiconductor chip of a semiconductor device according to a third embodiment of the present invention is shown in FIG. 3U (semiconductor chip layout diagram).

5, as shown in FIG. 3U, the mixed semiconductor chip 321 is
A logic circuit section Logics is disposed in the center, and a memory circuit section RAM is disposed above and below, respectively.

An input circuit D in , an output circuit Dout, and a power supply circuit VC are distributed to the left and right peripheral portions of the semiconductor chip 321, respectively.

The logic circuit section Logtc of the semiconductor chip 321 is composed of semiconductor elements mainly consisting of complementary MISFETs. The memory circuit RAM is composed of SRAM,
The 0 peripheral circuit, which is composed of semiconductor elements mainly composed of MISFETs, is composed of semiconductor elements mainly composed of Pipo2 transistors. In addition, as for the peripheral circuits, the output circuit Dout, which particularly requires driving power, is composed of a bipolar transistor, and the input circuit Din is composed of a complementary mMIsFET.
It may be composed of

The specific structure of each semiconductor element constituting the semiconductor chip 321 is shown in FIG. 3V (cross-sectional view of main parts). On the left side of FIG. 3V is a bipolar transistor, in the center is a p-channel MISFET, and on the right side is an n-channel MISFET. Each channel MISFET is shown.

As shown in FIG. 3V, the semiconductor chip 321 is formed on the main surface of the p'' type semiconductor substrate 321A made of single crystal silicon.
It is constructed by growing a type epitaxial layer 321B.

The bipolar transistor Tr includes a semiconductor substrate 321A,
Buried p-temperature semiconductor region 321D.

P-type semiconductor region 321G and element isolation insulating film 321H
It is electrically isolated from other regions by an isolation region consisting of. The semiconductor region 321D is formed between the semiconductor substrate 321A and the epitaxial layer 321B. The bipolar transistor Tr is of an npn type and includes an n-type collector region, a p-type backspace region B, and an n-type emitter region E.

The collector region C is a buried n+ type semiconductor region 321C.
, an n-shaped L region 321E, and an h-type semiconductor region 3211 for raising the potential.

In the semiconductor region 3211 of the collector region C, there is an interlayer disconnection &3.
The first layer wiring 321U is connected through the current connection hole 321T formed in 21P and 321S. Placement fM
321U is formed of an aluminum film added with Cu or Sl.

The base region B is composed of a p-type semiconductor region 321J provided on the main surface of the well region 321g. A wiring 321U is connected to the semiconductor region 321J, which is the base region B.

The emitter region E is an n+ type semiconductor region 3 provided on the main surface of the semiconductor region 321J constituting the base region B.
It consists of 21. Emitters liL&321M are connected to the semiconductor region 321K, which is the emitter region E. The emitters iiL&321M are formed of the first layer of polycrystalline silicon*M into which n-type impurities are introduced. An emitter electrode 321MK is introduced into the semiconductor region 321.
It is formed by diffusing type impurities into the semiconductor region 321J. The emitter electrode 321M has a wiring 32
1U is connected.

The complementary MISFET p-channel MISFETQp is
It is formed on the main surface of the well region 321E in a region surrounded by the element isolation insulating film 321H. MISFE
TQp includes well region 321E, gate insulation 111j3
21L, Gate Hiro-, 1321M.

It is composed of a pair of p-type semiconductor regions 3210, which are a source region and a drain region.

The gate insulation j1321L is formed of a silicon oxide film formed by oxidizing the main surface of the well region 321E.

The gate electrode 321M is formed of a polycrystalline silicon film doped with n-type impurities.

The semiconductor region 3210 is formed by introducing a p-type impurity (eg, B) by ion implantation. Since the channel forming region side of the semiconductor region 3210 is configured with a low impurity concentration, the MISFETQp has L D D (
It is composed of a (Lightly Doped Drain) structure. A wiring 321U is connected to the semiconductor region 3210.

Complementary MISFET n-channel MISFETQn is
In the region surrounded by the element isolation insulating film 321H, p
It is formed on the main surface of the "" type well region 321F. M
ISFETQn is composed of a well region 321F, a gate insulating film 321L, a gate electrode 321M, and a pair of n-type semiconductor regions 321N, which are a source region and a drain region.

MISFETQn is LDD like MI 5FETQP
It consists of a structure.

A wiring 321U is connected to one semiconductor region 321N of the MI 5FETQn. The other semiconductor region 321
N has a connection hole 321 formed in the glabella insulating film 321P.
Through Q, the size is 321R.

Each of the high resistance load elements 321R*s wiring 321R4 is connected in sequence. Placement, +321 Rt, wiring 3
Each of 21R and 21R is formed by introducing an n-type impurity into the second layer polycrystalline silicon film. In the memory circuit RAM, the wiring 321R is used as a power source for supplying voltage (for example, circuit operating voltage 5 [V]) Vcc to the memory cell 11. The high resistance load element 321R is formed by introducing no impurities into a polycrystalline silicon film or by introducing some n-type or p-type impurities into the polycrystalline silicon film.

An interlayer insulating film 321■ is interposed on the wiring 321U, and the W
A second layer wiring 321X is provided.

The wiring 321X is connected to the arrangement 11321U through a connection hole 321W formed in the interlayer insulation vII 321V. A third layer arrangement 1j321AA is provided on the wiring 321U with a glabella insulating film 321Y interposed therebetween. ing. The second layer arrangement [321X, the third layer arrangement II
Each of J321 AA is, for example, #321 of the first layer.
Made of the same material as U.

In this way, the semiconductor chip 321 has a three-layer wiring structure.

A badge page carbon film 321AB is provided on the third layer wiring 321AA. The padding film 321AB is formed of, for example, a silicon nitride film deposited by sputtering.

In the area of the memory circuit RAM of the semiconductor chip 321 or the area of the circuit composed of complementary MI 5FETs (for example, the logic circuit unit Logle or the input circuit Din), an α-ray shielding film is provided on the PADGE PAGE AB. 322 is provided. The α-plate 11g322 is not shown in FIG.
Radioactive elements (U and Th) contained in trace amounts in 1308
) is constructed to shield alpha rays originating from The α-ray shielding film 322 is formed of a polyimide resin, for example, a polyimide-iso-indolo-quinazoline-dione film. The αwj chain shielding film 322 is, for example, 10 to 30° [μ
It is formed with a film thickness of about 1.0 m.

The memory circuit RAM of the semiconductor chip 321 is composed of an SRAM as described above, and the memory cells of this SRAM 17) are constructed as shown in FIG. 3W (equivalent circuit diagram of a memory cell).

As shown in Figure IE3W, the memory cells of the SRAM are arranged at the intersections of complementary data lines DL, DL extending in the row direction and words MWL extending in the column direction. This memory cell is constructed of a high resistance load type.

The memory cell is composed of a flip-flop circuit used as an information storage section and two transfer MISFETs Qt whose semiconductor regions are connected to a pair of input/output terminals. The other semiconductor region of the transfer MISFETQt is connected to complementary data 1fiDL. Transfer M
I 5FETQt gate 1! The pole is connected to Word &WL. This transfer MISFETQt is the third v
It is composed of n-channel MI 5FETQn shown in the figure.

The flip-flop circuit is composed of two high resistance load elements R and two driving MISFETs Qd. The high resistance load element R is the high resistance load element 3 shown in the maV diagram above.
21R, (polycrystalline silicon film). Drive M
ISFETQd is an n-channel MI shown in FIG.
It is formed of 5FETQn. A voltage VCC is applied to one end of the high resistance load element R (wiring 321
A reference voltage (for example, circuit reference potential 0 (V)) V811 is applied to the semiconductor region 321N used as the source region of the drive MI 5FETQd.

The mixed semiconductor chip 321 configured in this way is @
As shown in Figure 3X (reproduction cross-sectional view of the semiconductor chip), a protruding electrode 308 is provided on the external terminal BP. That is, the protruding electrode 308 is piped in a region on the peripheral circuit composed of the bipolar transistor Tr. Protruding electrode 308
is not formed on the mounting substrate side on which the semiconductor chip 321 is mounted, but is formed on the external terminal BP side of the semiconductor chip 321 in this embodiment.

The α spin whose generation source is the protruding electrode 308 is the semiconductor substrate 321
When incident on A, minority carriers are generated, and these minority carriers change the t-position of the information storage area (node) of the memory cell of the SRAM and induce a soft error. The protruding electrode 308 is not provided, and the minority carrier is MI 5FETQn,
Each gate insulation 1i 321L of MI 5FETQp, gate insulation film 321L and well region 321E or 321
Since the protruding electrode 308 is easily trapped at the interface with F and fluctuates the threshold voltage, the protruding electrode 308 is not provided on the circuit mainly composed of complementary MISFETs.
Above, logic circuit section Lo consisting of complementary MI 5FETs
On the GLC, the protruding electrode 308 is not formed on the circuit formed by the complementary MISFET among the peripheral circuits.
21 AB is provided with the α-ray shielding film 322. The bipolar transistor Tr is MISFETQn.

The α-ray shielding film 322 is not provided on the region of the bipolar transistor Tr because it is more resistant to α-ray soft errors than each of Qp.

Further, the α-ray shielding film 322 is provided in a region other than the region where the protruding electrode 308 is formed. Since the αha shielding film 322 has a different coefficient of thermal expansion from the semiconductor chip 3210 and the semiconductor substrate 321A, if the αM shield #322 and the protruding electrode 308 come into contact, the protruding electrode 308 may be damaged or In order to destroy the α-ray shielding film 322 and the protruding electrode 308, the α-ray shielding film 322 is not brought into contact with the protruding electrode 308.

The protruding electrode 308 is formed by a lift-off method substantially similar to that shown in FIG. 3C. Since the α-ray aMi 322 is provided on the padgage carbon film 321 AB,
The first resist film 3SS of the lift-off method is formed on the α# cover film 322 as shown by the dotted line in FIG. 3X. The first resist film 318 is formed on an area where the protruding electrode 308 is not formed, that is, an area of the memory circuit RAM, and on the logic circuit area Log.
It is formed on the i c region and on the peripheral circuit region composed of complementary MISFETs. A film 319 (not shown) is formed in the region where the protruding electrode 308 is formed and on the resist film 318. In the region of the second resist film 319 where the protruding electrode 308 is formed, the first
An opening 320A is formed, and a 210th portion 320B is formed on the second resist film 319 of the second resist film 319. There is a protrusion in the 1st R+ mouth part 320A'#JLl)
3308 is formed, and a dummy protrusion electrode 308A is also formed in the second opening 320B. And the first
While leaving the protruding electrode 308 in the opening 320A, the second resist) [319, the second resist [318 and the second resist]
By removing the dummy protruding electrode 308A in the opening 320B, the semiconductor device of this example is completed.

3rd v[i6, 3Nth Al wiring 321 AA
is the logic bypass wiring #32 on the memory.
5 (Fig. 3U), and is laid out so as to be perpendicular to the data of the memory.

In this way, bipolar transistor Tr and complementary type M
A method for manufacturing a semiconductor device in which a protruding electrode 308 is formed on the surface of the bipolar transistor Tr forming region of a mixed semiconductor chip 321 having ISFgT by a seven-off technique, the method comprising: a complementary MISF of the semiconductor chip 321;
An α-ray shielding film 322 is formed on the surface of the ET formation region, and a second resist film 318 is formed on the α-ray shielding film 322, including over this second resist 7318 and the bipolar transistor Tr formation region. A second resist film 319 is formed on the entire surface of the semiconductor chip 321, and an opening 320A for forming the protrusion 1; Complementary MISFET of membrane 319
A second opening 320B for forming a dummy protruding electrode 308A is formed in the formation region, and a second opening 320B is formed on the surface of the semiconductor chip 3210 in the first opening 320A, a first regime in the second opening 320B [318 and 2 resist) A gold F4 film 308B for forming protruding electrodes 308 is deposited on the entire surface of the semiconductor chip 321 including on the film 319, and the second resist film 3
1.9. The metal film 308Bt in the first opening 320A is left to form the protruding electrode 308, and the gold fi4308B on the second resist) 1319 and the metal film 308B on the second resist 11318 are removed. By removing the tI4 film 308B (dummy protruding electrode 308A), a second opening 320B for forming the dummy protruding electrode 308A is formed in the complementary MISFET formation region, and a second resist is passed through the second opening 320B. Since the stripping liquid is actively infiltrated into the film 319, the stripping properties of the second resist 319 in the complementary MISFBT formation region where the protrusion-pole 308 is not formed can be improved.

In addition, by forming the α-ray shielding film 322 on the complementary MISFET formation region of the semiconductor chip 321, the α-ray shielding limbs 322 shield α-rays from the protruding electrode 308, and the threshold voltage of the complementary MISFET is Since it is possible to reduce fluctuations in , it is possible to reduce deterioration of the characteristics of the complementary MISFET over time.

Further, by separating the α-ray shielding film 322 and the protruding electrode 308, damage or destruction of the protruding electrode 308 due to the difference in thermal expansion coefficient between the α-ray shielding film 322 and the half-quad chip 321 can be avoided. Since this can be prevented, the electrical reliability of the semiconductor device can be improved.

In addition, by not forming the α-ray shielding plate 322 made of polyimide fat in the region where the protruding electrode 308 is formed, α
Since the protruding electrodes 308 can be independently processed without being affected by the poor processability of the W shielding film 322, the protruding electrodes 308 can be formed at a higher density.

Further, there is provided a method for manufacturing a semiconductor device in which a protruding electrode 308 is formed by a lift-off technique on a surface of the peripheral circuit formation region of a semiconductor chip 321 having a memory function configured of a memory circuit portion RAM and a peripheral circuit, the method comprising: chip 3
21, an α-ray shielding film 322 is formed on the surface of the area, and a 318th Lugis) i 318 is formed on the upper part of this α-fi shielding 322.
the semiconductor chip 32 including the top and the top of the peripheral circuit formation region;
2nd resist on the entire surface of 1:,! 319, and a protruding electrode 30 is formed in the peripheral circuit formation region of this second resist H319.
At the same time, a first opening 320A for forming a dummy protrusion FM and a pole 308 is formed in the formation region of the memory circuit RAM of the second resist 7320B. A metal film 308B for forming protruding electrodes 308 on the entire surface of the semiconductor chip 321, including on the surface of the semiconductor chip 3210 in the first opening 320A, on the second resist 7318 in the second opening 320B, and on the second resist 7319) [319] and deposit the second resist layer 319.
, IiE Lugis)! 318 and leave the metal film 308B in the first opening 320A to form the protruding IL pole 308, and remove the metal film 308B on the v2 resist 319 and the metal film 308B on the v2 resist 19318. By removing the metal film 308B (dummy protruding electrode 308A), a second opening 320B for forming the dummy protruding electrode 308A is formed in the formation area of the memory circuit RAM, and a second resist is passed through the second opening 320B. Since the stripping liquid was actively infiltrated into the film 319, the protrusion IkL pole 308
It is possible to improve the removability of the second resist (M319) in the formation region of the memory circuit portion RAM where the second resist (M319) is not formed.

Furthermore, by forming the α-ray shielding film 322 in the formation region of the memory circuit RAM of the semi-integrated chip 321, the α-ray shielding film 322 can shield α-rays from the protruding electrodes 308. It is possible to reduce soft errors caused by

(4) Example 4 5ICO8 (SideWal
l Ba5e Contract 5structure
4B (chip layout diagram) shows a semiconductor integrated circuit device manufactured by i# and having <Ibo-2 transistors.

As shown in FIG. 4B, the semiconductor integrated circuit device LSI is
- It is composed of a rectangular chip with sides of about 10. Input/output circuits I10..I10.

l10s and an X source circuit VC are arranged.

A logic section (logic section) Logic is arranged in the central part of the semiconductor integrated circuit device LSI. A memory section (storage section) Mem is provided on each of the left and right sides of this logic section Logic.
ory' is arranged.

There are 8 memories on the left side and 8 memories on the right side.

It is composed of a total of 16 memory cell arrays MA.

The peripheral portion of each memory cell array MA includes an X decoder circuit XDe6N and an X address buffer circuit XAn.
, write circuit WC are arranged.

Further, in the peripheral part of each memory cell array MA, Y decoder circuit YDec% Y address buffer circuit YAB, Y
Driver circuits YD are arranged respectively.

Although not shown in the drawings, the memory cell array MA has memory cells arranged at intersections between digit h and information holding lines and word lines. SBD), a forward bipolar transistor, a reverse bipolar transistor, and a flip-flop having high resistance and low resistance. In other words, the memory cell is a resistance switching type memory cell with SBD.

The specific configuration of the main parts of the semiconductor integrated circuit device LSI configured in this way is shown in FIG. 4C (an enlarged plan view of the main parts in FIG. 4B) and FIG. 4D (an enlarged plan view of the main parts in FIG. 4C). show.

As shown in Figure 1i44c, the aforementioned logic section Logl
e. Each of the memory parts Memor7 has a plurality of active regions (
An active area (Act) is provided.

As shown in FIG. 14D, a pibo-2 transistor Tr, a resistance element R, etc. that constitute each circuit are arranged in the active region Act. The bipolar transistor Tr is mainly composed of a collector region C, a space region B, and an emitter region E.

As shown in FIG. 4C, between each active region Act,
An isolation region (Iso) is provided. This isolation region Iso is used as a wiring formation region (wiring channel region) as shown in FIG. 4D. That is, the isolation region Iso is configured such that wiring (426°, 428, etc.) connecting circuits formed in the active region Act or between circuits formed in different active regions Act can be extended.

The semiconductor integrated circuit device LSI currently being developed by the present inventor has a four-layer distribution structure, although it is not limited thereto. The distance between the two bibolar transistors Tr in the active region Act is 1.4.
As shown in Figure D, the wires are connected by wiring #1426 on the first layer. The distance between circuits formed in the active region Act or between the circuits formed in different active regions Aat is 1rJ.
426 and the second layer wiring 1IN428. The wiring 1m426 and the wiring @42B are configured to extend the isolation region 1mo.The wiring 426 of the first layer extending the isolation region Iio extends in the vertical direction in FIG. It is formed. 2nd layer wiring 428
is configured to extend laterally. 8J 3rd layer wiring (430) lI 4th layer wiring (432) other than the above
) are mainly composed of signal wiring and power supply wiring.

Next, the specific structure of the memory cells arranged in the active region Act, particularly the memory cell array MA of the memory section Memor7, will be briefly described using FIG. 4A (a sectional view of the main part).

As shown in FIG. 4A, the semiconductor integrated circuit device LSI is mainly composed of a p'''' type semiconductor substrate 401 which may be a single crystal silica. On the main surface of this semiconductor substrate 401, an n-type epitaxial layer 403 is formed. In the active region Act, the main surface of the semiconductor substrate 401 includes a forward bipolar transistor Try, a reverse bipolar transistor T r H, and a shuttling barrier diode SBD.

A high resistance RH and a low resistance RL are each configured.

These semiconductor elements constitute a flip-flop and constitute a resistance switching type memory cell with SBD of a static RAM.

Between each semiconductor element, especially the forward direction bipolar transistor Tr
y, reverse bipolar transistor Trl, high resistance R
Each H is electrically isolated by an element isolation region. The element isolation region is mainly composed of a semiconductor substrate 401, an element isolation insulating film 405, and a p+ type semiconductor region 406. The element isolation insulation M405 is the semiconductor substrate 40
1. It is formed of a silicon oxide film formed by selectively performing thermal oxidation treatment on the main surface of (or epitaxial ~403). The element isolation insulating film 405 has a protruding island region 4
Semiconductor substrate 401 and epitaxial layer 1@ at the corner of 04
3000-5 to avoid causing condensation defects in 403
The film thickness is approximately 000 (A). The element isolation insulating film 405 is formed with a thin film thickness as an inter-element isolation insulating film. A p-type semiconductor region 406 is provided on the main surface of the semiconductor substrate 401 under the element isolation layer 405.

The forward bipolar transistor Trl includes an n-type collector region, a p-type base region, and an n-type emitter region. That is, the forward bipolar transistor Tr1 is composed of npnffi.

The collector region is composed of a buried n+ type semiconductor region 402 and an n+ type semiconductor region for raising the collector potential (not shown). An n-type semiconductor region 402 is provided between the semiconductor substrate 1 and the epitaxial layer 403. This n+ type semiconductor region 402 is provided to reduce collector resistance.

The base region is composed of a p+ type semiconductor region 409 and a p type semiconductor region 416. p! The semiconductor region 416 is formed in the epitaxial layer 4 in the protruding (convex) island region 404 formed in the epitaxial layer 403 of the active region Act.
It is provided on the main surface of 03. p+ type semiconductor region 40
Reference numeral 9 is provided on the main surface of the epitaxial layer 403 at the side wall of the protruding island region 404, specifically at the shoulder portion.

The emitter region is composed of an n-type semiconductor region 417 and an n+-type semiconductor region 420. The n-type semiconductor region 417 is a space region (provided on the main surface of the p-type semiconductor region 416) formed in the protruding island region 404. The n+-type semiconductor region 420 is provided on the main surface of the n-type conductor region 417. It is being

One end of the p-type semiconductor region 409 of the base region is connected to the base extraction electrode 408 through a connection hole 407 formed in the element isolation insulating film 405 on the side wall of the protruding island region 404 . 'wIL pole 408 for base drawer
The other end of A is drawn out onto the element isolation insulating film 405 in the element isolation region.

That is, forward bipolar transistor Tr! is 5I
It is composed of CO8 structure. Pace extraction electrode 408
A is formed of a first layer polycrystalline silicon film into which p-type impurities are introduced. p-type semiconductor region 4 of the base region
09, the 9th generation impurity introduced into the base extraction electrode 408A is transferred to the epitaxial layer 403 at the connection hole 407 portion.
It is formed by diffusing into the main surface of. In other words, the p+ pear semiconductor region 409 is connected to the base extraction electrode 408.
It is formed in self-alignment with respect to A. src.

The S-structure forward bipolar transistor Trl can eliminate the connection area between the base extraction electrode 408A and the p+ semiconductor region 409 serving as the base region in the planar direction, thereby reducing the area occupied by the base region and increasing the degree of integration. can be improved.

1i for pace drawer! As shown in FIG. 4D, the pole 408A is connected to the first layer metallization 426 through a connection hole 425 formed in the interlayer insulating film 424 or the like. Wiring 4
26 is an aluminum film 4 on a platinum silicide film 426A.
26 Bf, made of laminated composite membranes. The platinum silicide pad 426A is mainly composed of a silicon silicide barrier diode 5BDt. aluminum! 426B is added with Sl to prevent alloy spikes and Cu to prevent stress migration.

In the nff1 semiconductor region 420 of the emitter region, there is a layer 1
An emitter extraction electrode 419 is connected through a connection hole (emitter mouth) 418 formed by m413. The emitter lead-out electrode 419 is a second electrode into which n-type impurities are introduced.
It is formed of a multi-layered polycrystalline silicon film. The interlayer interlayer film 413 is formed of a silicon oxide film formed by thermally oxidizing the surface of the base lead-out electrode 408A. Connection hole 418 whose opening size is defined by this interlayer insulation 1% 413
is formed in self alignment with the base extraction electrode 408A. In other words, the ivy extraction electrode 41 that will be constructed in the end
9 is connected to the n-type semiconductor region 420, which is an entrant region, in self-alignment with respect to the base lead-out portion 1408A. This n-type semiconductor region 420 is formed by introducing an n-type impurity into the main surface of the n-type semiconductor region 417 through the emitter extraction electrode 419 within the region defined by the connection hole 418. In other words, the n''W semiconductor region 420 is formed by self-binding with respect to the emitter extraction electrode 419.

The emitter lead-out electrode 419 has a base lead-out electrode 408.
Arrangement M426 is connected as in A.

Although not shown, an n++ semiconductor region for raising the collector position of the collector region is provided on the main surface of the epitaxial layer 403 of the protruding island region 404. This n++ semiconductor region for raising the collector position is provided with a collector lead-out electrode (41
9) is connected to distribution ft1426.

The reverse bipolar transistor Try is composed of an n-type collector region, a p-type base region, and a nu emitter region. That is, the reverse bipolar transistor Tr1 is constructed of an npn type.

The emitter region is composed of a buried n type semiconductor region 402 and an n + type semiconductor region on the emitter potential side (not shown).

The base region consists of a p++ semiconductor region 409 and a pm semiconductor region 414. The p semiconductor region 414 is provided on the main surface of the epitaxial layer 403 in the protruding island region 404 . The p++ semiconductor region 409 is formed in the epitaxial layer 40 at the shoulder portion of the protruding island region 404.
It is provided on the main surface of No. 3.

The collector region is composed of an n-type semiconductor region 415 and an n++ semiconductor region 420. The n-type semiconductor region 415 is a base region (p) formed in the protruding island region 404.
It is provided on the main surface of the type semiconductor region 414). n+
The positive semiconductor region 420 is provided on the main surface of the n-type semiconductor region 415.

A wiring 426 is connected to the p++ semiconductor region 409 of the base region with a base extraction electrode 408A interposed therebetween, similarly to the forward bipolar transistor Tr. In other words, the reverse bipolar transistor Trl has a SIC'O3 structure. An n+ type semiconductor region (not shown) in the emitter region for raising the emitter potential is connected to a wire &426 with an emitter extraction electrode (419) interposed therebetween. N++ semiconductor region 42 in the collector region
0 with a collector extraction electrode 419 interposed therebetween! 42
6 is connected.

This reverse bipolar transistor Try has a collector terminal that serves as an information storage section (storage node section) of the memory cell on the surface side of the epitaxial layer 403. In other words, the reverse bipolar transistor Try has the feature that soft errors can be prevented because the base region (p-type semiconductor region 414) can block minority carriers generated by α rays incident into the semiconductor substrate 1. There is.

The above-mentioned shut keeper diode SBD is.

It is composed of an n-type semiconductor region 417 integrally formed with the emitter region of the forward bipolar transistor Trl and platinum silicide [426A of the wiring 426]. This shielded barrier diode SBD has a shield structure. In other words, the nm semiconductor region 417 of the Schottky barrier diode SBD is the p-type semiconductor region 4 which is the base region of the forward bibolar transistor Trl.
16 and a p+ type semiconductor region 409. The switchgear barrier diode SBD is connected to the collector terminal (information # horizontal portion) of the reverse bipolar transistor Tr1 through a low resistance RL. That is, the shield structure is configured to trace the minority carriers generated by the incidence of α rays into the semiconductor substrate 401 as described above.

The low resistance RL of the memory cell resistance is the n-type semiconductor region 4 which is the emitter region of the +1 direction bipolar transistor Tr1.
It consists of 17.

The high resistance RH of the memory cell resistance is the p-type semiconductor region 410.
It consists of The p-type semiconductor region 410 is provided on the main surface of the epitaxial layer 403 of the protruding island region 404.

Further, a cap element Ca is configured in the memory cell.

This capacity is the lower layer electrode 419° and the electrically shielding film 423. It has a stacked structure in which the upper 11t layers 423 are sequentially laminated. The lower electrode 419 is made of polycrystalline silicon, which is the same layer as the emitter extractor 11L and others 419. The dielectric film 423 is formed of, for example, a tantalum oxide (Tasks) film. The upper electrode 423 is formed of, for example, a high-melting MoSit film. The dielectric film 423 has the same pattern as the upper layer-pole 423.

An interlayer insulating film 427 is provided above the first layer wiring 426.
A second layer wiring 428 extends with the two layers interposed therebetween. A third layer wiring 430 extends above the second layer wiring 41428 with a glabella insulating film 429 interposed therebetween. A fourth layer wiring 432 extends above the third layer wiring 430 with an interlayer insulation layer 1431 interposed therebetween. 2nd layer wiring 428° 3rd R4 wiring @430. Each of the fourth layer arrangement IB432 is made of aluminum film, Sl or Cu.
It is made of an aluminum film doped with. A padding carbon film 433 is provided on the upper layer of the fourth layer a432.

In the active region Act, between the protruding island regions 404, that is, on the inter-element isolation insulating film 405 which is the inter-element isolation region,
As shown in FIG. 4D, a dummy protrusion 408C is provided. This die protrusion 408C is Lffi 408A for leading out the base of the forward bipolar transistor Trl.
, and y@4osx for leading out the base of the reverse direction bipolar transistor Try. The dummy protrusion 408C is spaced apart from each pace withdrawal electric current 44osA at a predetermined interval and electrically isolated.For example, if the minimum processing dimension is 1 [μm],
The distance between C and the pace extraction electrode 408A is 1 [μm].
] degree. Further, in the region where the base extraction electrode 408A is not present, the dummy protrusions 408C are spaced apart by the same distance as the protruding island region 404.

This dummy protrusion 408C mainly consists of the protruding island region 404
．． 'Electrode 408A for base extraction, -electrode 419 for emitter extraction. The collector drawer is configured to alleviate the step shape caused by the protruding shape of each pole 419. In other words, the dummy protrusion 408C is mainly used for the first layer wiring 4.
1# is formed so as to flatten the surface of the interlayer insulating film 424 serving as the base of the interlayer insulating film 424.

The wiring a426 in the first layer extending within the active region Act is formed with a short wiring length long enough to connect adjacent semiconductor elements, so the wiring length is short enough to connect adjacent semiconductor elements. i! The parasitic capacitance added to 426 can be virtually ignored. In addition, the active region Act
Inside, there are a plurality of protruding island regions 404 and a plurality of pace extraction electrodes 408A, so the stepped shape is significant. Therefore, the dummy protrusions 408C are spread over substantially the entire surface of the active region Act.

In this way, the semiconductor element (
A semiconductor integrated circuit device [L
In SI, the semiconductor substrate 401 of the active region Act
By filling substantially the entire surface of the element isolation region between the semiconductor elements between the dummy protrusions 408C and the 11-layer insulating film, the step shape that occurs at the semiconductor element or the '-pole is reduced. Since the surface of the interlayer insulation 1K (424) can be flattened by doing this, the step coverage of the front wiring 426 can be improved, and the electrical reliability of the wiring 426 can be improved. Particularly, since the Piborad 2 transistor with the 5ICO8 structure has a protruding island region 404 in the active region Act, the step shape is significant, and the present invention is effective.

Furthermore, in the isolation region Iso, as shown in FIGS. 4A and 4D, dummy protrusions 408B are arranged on the inter-element isolation insulating film 405. This dummy protrusion 408
Similar to the dummy protrusion 408C, B is a t5408 for leading out the base of the forward bipolar transistor Trl.
A: It is composed of the same conductive layer as the base lead-out electrode 408A of the reverse direction bipolar transistor Trl. The dummy protruding portion 408B is aligned (synchronized) with the layout pattern (turn) of the first layer wiring 426 in the upper layer. In other words, the dummy protruding portion 408B is substantially the same as the wiring width of the M1th layer wiring 41d426. The first layer wiring 42
For example, if the minimum processing dimension is 1 [μm], the dimension of the dummy protrusion 408B is 4 [μm] in the width direction of the wiring 426, and the dummy protrusion The distance between the parts 408B is l [μm
] Consists of. In addition, the dummy protrusion 408B is connected to the wiring 4.
In the extending direction of the wiring 426, the wiring 426 has the same dimensions and separation dimensions as the width direction of the wiring 426. In other words, the dummy protrusions 408B have a square planar shape, and are regularly arranged in plural in the row direction and the column direction. That is,
The dummy protrusion 408B is arranged in a mesh shape (valve shape) as shown in FIG. 4D. In addition, the dowel protrusion 40
8B is not limited to this square shape, and the planar shape may be any one of a rectangular shape, a circular shape, an elliptical shape, and a polygonal shape.

Further, the center position ti of the dummy protrusion 408B is substantially the same as the center position of the upper first layer wiring 426.

Configured to match. ! Figures 4E and 4F (reproduction diagrams modeling the board and the interconnection part) show a model of the creation and development of the parasitic capacitance performed by the present inventor. Although not shown, the isolation region I is similar to the dummy protrusion 408C of the active region Act.
When the dummy protrusions 4088't- are spread over the entire surface of so, the dummy protrusions 4 are magnetically spread over the entire surface.
By 08B, the parasitic capacitance below it is placed 4I! 426
(the parasitic capacitance formed between the dummy protrusion 408B and the semiconductor substrate 401 becomes infinite).

Therefore, the parasitic capacitance added to &426 is
! 11426 and dummy protrusions 40 spread over the entire surface
Since the parasitic capacitance formed between 8B and 8B becomes dominant,
The 0 isolation region Iso, which becomes quite large, is basically used between circuits formed in the active region Act or between different active regions Act-.
Since the wiring #426 connecting between the circuits formed in Based on such a result, at least the dummy protrusions 408B of the isolation region Iso are arranged in the shape of MEC 2 and formed between the wiring 426 and the semiconductor substrate 401. Parasitic capacitance with a small capacitance value is actively formed.

FIG. 4E shows how the wiring 426 is added when the arrangement pattern of the first-layer arrangement ai 1426 and the mesh-like arrangement pattern of the dummy protrusion 408B are made to match, and the center positions of both are made to match. Indicates parasitic capacitance. In the diagram of the circuit 4E, the parasitic capacitance C1 is the parasitic capacitance formed between the wiring 426 and the dummy protrusion 408B located directly below it. The parasitic capacitance C3 is a parasitic capacitance formed between the wiring 426 and the semiconductor substrate 401 (actually, the p+ type semiconductor region 406). The livestock owner kCs is wired 426
The symbol DA located near the dummy protrusion 408B located directly below the dummy protrusion 408B is a parasitic capacitance formed between the protrusion 408B and the dummy protrusion 408B. The value of each eccentric capacitance cle C, #c is an example, and its unit is (PF/Ryu).As shown in FIG.
A relatively large wire is formed between the wire 426 and the wire 426 through the protrusion 408B.
Since the semiconductor substrate 401 is visible from above, a very small parasitic capacitance C1 is formed between the wiring 426 and the semiconductor substrate 401. Furthermore, since the wiring 426 and the dummy protrusion 408B located directly below the dummy protrusion 408B are separated by the maximum dimension that is the distance between the dummy protrusions 408B, the parasitic capacitance Cs is very large. becomes smaller.

Therefore, the parasitic capacitance added to the wiring 426 is
Parasitic capacitance C formed between 26 and the semiconductor substrate 401
1 is dominant, so the minimum number of hosts i is added to the wiring 426.According to the simulation conducted by the present inventor, the arrangement pattern of the wiring 426 and the dummy protrusion 40
When the mesh-like arrangement I and turn of 8B are made to coincide with each other and their center positions are made to be the same, the wiring 426
We were able to obtain a result in which the parasitic capacitance added to the structure was reduced by approximately 20%.

On the other hand, FIG. 4F shows a case where the arrangement pattern of the first-layer edging 426 and the island-like arrangement pattern of the dummy protrusion 408B are shifted by half an interval (the end of the edging 426 (Aligned with the end of the dummy protrusion 408B)
, distribution 4! It shows the parasitic capacitance added to +426.

In FIG. 4F, a parasitic capacitance C4 is a parasitic capacitance formed between the wiring 426 and the semiconductor substrate 401. Parasitic capacitance C
The wiring 426 and the dummy protrusion 40 located near the wiring 426
This is a parasitic capacitance formed between 8B and 8B. Parasitic capacitance C1
is a parasitic capacitance formed at the threshold between the wiring 426 and the dummy protrusion 408B placed farthest away from the wiring 426. As shown in FIG. 4F, a very small host J[C4 is formed between the wiring Nh426 and the semiconductor substrate 401 through the dummy protrusion 408B.
426 and two dummy protrusions 408 located near it.
The host customer tCs formed with B is added and its value becomes larger. Also, distribution! i+! The host iC formed between 426 and the dummy protrusion 408B located farthest away from it becomes smaller. therefore.

Since the parasitic load added to the wiring 426 is dominated by the parasitic capacitance formed between the wiring 426 and the dummy protrusion 408B in the vicinity thereof, the wiring 426 has the above-mentioned 17E4.
A larger parasitic capacitance is added compared to the case shown in Figure E.

Note that the host and customer t added to the wiring 426 is smaller than when the dummy protrusions 408B are spread over the entire surface.

゛In this way, the active region Ac on the main surface of the semiconductor substrate 401
An electrode (408A
or 419) is connected, and an interlayer insulating film (
419, 421, 424) in which a wiring 426 extends, a dummy protrusion is provided in an isolation region Iso between the semiconductor elements between the semiconductor substrate 401 and the interlayer insulating film. By arranging 408B in a mesh shape, it is possible to reduce the step shape that occurs in the semiconductor elements and electrodes and to make the surface of the interlayer insulating film (424) even, thereby improving the step coverage of the wiring 426. In addition, it is possible to improve the reliability of the wiring 426, and also improve the
The parasitic capacitance formed between the semiconductor substrate 401 and the wiring 426 whose capacitance value is smaller than the main capacitance formed between the wiring 426 and the dummy protrusion 408B is actively formed.
Since the parasitic capacitance added to 6 can be reduced,
By increasing the signal transmission speed of the wiring 426, the operating speed of the semiconductor integrated circuit device ffff1LsI can be increased.

In particular, in a bipolar transistor with a 5ICO8 structure, it is not possible to form a thick inter-element isolation insulating film 405 in the isolation region I8o because crystal defects are likely to occur at the corner portions of the protruding island region 404 in the active region Act. The present invention is effective in reducing the parasitic capacitance added to the first layer wiring 426.

In addition, the second layer is 9428. The upper layer wiring 430.
432 are each interlayer insulating film 427°429.431
Since each of them is thick, for example, about 8,000 to 12,000 (A), the added parasitic capacitance is small.

Further, in the semiconductor integrated circuit device LSI, the upper layer of the dummy protrusion 408B is made to substantially coincide with the mesh-shaped arrangement of the dummy protrusion % 408B, and substantially coincide with the center position of the dummy protrusion 408B. By adding the configuration in which the first layer wiring 426 is arranged in a manner that coincides with each other, in addition to the above-mentioned effect, as shown in FIG. 4E, the wiring 426
Since the parasitic capacitance formed between the wiring 426 and the semiconductor substrate 401 is dominant, and the parasitic capacitance formed between the wiring 426 and the dummy protrusion 408B can be reduced to a minimum, the signal transmission of the wiring 426 is The speed can be increased, and the operating speed of the semiconductor integrated circuit device LSI can be further increased.

Furthermore, the dummy protrusion 408B and the 17th wiring 4
Interlayer separation fi, which is formed at the same time as 26! (411゜42
1 and 424) are formed with a film thickness that is half or thicker than the distance between the dummy protrusions 408B arranged in a mesh shape. For example, the dummy protrusions 408B
If the separation dimension between the two
0 (A) or more.The interlayer AN formed in this back town reliably fills the recesses between the dummy protrusions 408B arranged in a mesh shape, and fills the glabella insulating film (4
24) can be flattened. In addition, the interlayer insulating film is basically a single layer film (411) that electrically isolates the dummy protrusion 408B and the wiring 426, and also electrically isolates the dummy protrusions 408B that come into contact with each other. can. Note that, as shown in FIG. 4D, the intervals between the square dummy protrusions 408C arranged in a mesh shape are inclined at 45 degrees with respect to the width direction and the extending direction of the wiring 426. Dummy protrusion 408 arranged
The distance C is the maximum separation dimension. Therefore, it is preferable for flattening that the interlayer insulating film is formed to have a thickness that is one-eighth of the distance between the dummy protrusions 408B in the width direction and the extension direction of the wiring 4260, or thicker than that. .

In this way, in the semiconductor integrated circuit device LSI,
In addition to the above effects, by adding an N layer in which the interlayer insulating film (basically the interlayer insulating film 411) has a thickness that is half the dimension between the dummy protrusions 408B or thicker than that, the above effect can be obtained. , as shown in FIG.
Embed 1-Kanine Desert (411) between 8B, interlayer desert,
Since the surface of birth (4.24) can be flattened,
The step coverage of the wiring 426 is improved, and the wiring 426 is improved.
It is possible to further improve the mechanical reliability of the dummy protrusion 408B.
- The apparent film thickness of the interlayer insulating film (41, 1) is determined to be less than
Furthermore, since the capacitance formed between the wiring 426 and the semiconductor substrate 401 can be further reduced and the parasitic capacitance attached to the wiring 426 can be reduced,
The signal transmission speed of the semiconductor integrated circuit device LSI can be increased, and the operating speed of the semiconductor integrated circuit device LSI can be further increased.

Next, a specific method of manufacturing the semi-integrated circuit device fLsI will be briefly described using FIGS. 4G to 4V (cross-sectional views of main parts shown for each manufacturing process).

First, a p-type semiconductor substrate 401 having a rounded single crystal structure is prepared.

Next, between the half-body elements of the active region Act and the isolation region Is
In step o, an impurity introduction mask 435 is formed on the main surface of the semiconductor substrate 401. The impurity introduction mask 435 is formed of a silicon oxide film formed by selectively performing thermal oxidation treatment on the main surface of the semiconductor substrate 401.

Next, using the impurity introduction mask 435, an nff1 impurity such as Sb (or P
By introducing As or As), a buried n+ type semiconductor region 402 is formed as shown in FIG. 4G. The n-type impurity is introduced, for example, by thermal diffusion.

Next, the impurity introduction mask 435 and other silicon oxide films on the main surface of the semiconductor substrate 401 are removed. Then, as shown in FIG. 4H, an n-W epitaxial layer 403 is grown all over the main surface of the semiconductor substrate 401. The epitaxial layer 403 is formed to have a thickness of, for example, about 0.6 to 0.8 [μm].

Next, in the semicircular element formation region of the active region Act,
Masks 436, 437, and 438 are sequentially formed on the main surface of the epitaxial layer M 403, respectively. The i-layer 436 is formed of, for example, a silicon oxide film formed by subjecting the surface of the epitaxial layer 403 to thermal oxidation treatment. mask 4
37 is formed on the mask 436 and is mainly used as an oxidation-resistant mask. The mask 437 is formed of, for example, a silicon nitride film deposited by CVD or sputtering, and has a thickness of 800 to 1
It is formed with a film thickness of about 200 (A). The mask 436
are formed to relieve stress generated between the semiconductor substrate 401 and the mask 437, and are formed, for example, from 400 to
It is formed to a thickness of about 600 (A). The mask 438 is
It is formed on the mask 437 and is mainly used as an etching mask. The mask 483 is formed of a silicon oxide group deposited by the CVD method, for example, and has a thickness of 7000 to 5ooo ("λ
] to a film thickness of approximately These masks 436°43
7.438 is a sequential pattern Jung (overlapping cutting) from the top layer
and are formed with the same pattern.

Next, as shown in the fourth construction drawing, the mask 436°43
Form a mask 439 on each sidewall of 7.438. Mask 439 is mainly used as an etching and oxidation-resistant mask. The mask 439 can be formed, for example, by sequentially laminating silicon nitride and polycrystalline silicon, and then performing anisotropic etching such as RIE. A silicon nitride film is mainly used for heat-resistant oxidation processing, and a polycrystalline silicon film is used to improve step coverage of silicon nitride.

Next 1. Mainly using masks 438 and 439, the surface of the epitaxial layer 4030 between the semiconductor elements in the active region Act and in the isolation region Iso is removed by etching to form a protruding island region 404 in which the epitaxial layer 403 is protruded. The etching is mainly performed by anisotropic etching in order to improve the processing accuracy, and in the final stage, the etching is performed by isotropic etching in order to soften the steep shape of the corner portion of the protruding island region 404.

Next, as shown in FIG. 4J, a silicon oxide group 440 is formed on the surface of the epitaxial layer 403 to be exposed using a mask 439. The silicon oxide film 440 is formed by thermally oxidizing the surface of the epitaxial layer 4030. This silicon oxide group 440 is formed to remove damage from etching performed to form the above-mentioned protruding island region 404 from the surface of the epitaxial layer 403.

Next, the silicon oxide group 440. Each mask 430 is removed in sequence.

Next, 11 of each of the masks 436, 437, 438
A mask 441 is formed on the Ill wall and the side wall of the protruding M region 404 (the surface of the epitaxial layer 14403). The mask 441 is mainly used for heat-resistant oxidation processing. Like the mask 439, the mask 441 is made by sequentially laminating, for example, silicon oxide and polycrystalline silica, and then RIE.
It can be formed by anisotropic etching such as.

Next, between the semiconductor elements in the active region Act and the isolation region Is
In step o, a p-type solid material is introduced into the main (8) portion of the semiconductor substrate 401. The p-type impurity is, for example, 10101s (a
B is introduced using an ion implantation method with an energy of about 60 to 8 degrees [KeV]. Then, by stretching and diffusing this p-type impurity, a p + -type semiconductor region 406 is formed. p+ type semiconductor region 406
is designed to form an @ region corresponding to the amount of elements.

Next, as shown in the figure, an element isolation insulating film 405 is formed on the surface of the epitaxial layer 4030 on the side wall of the protruding island region 404 and on the other surface of the epitaxial layer 4o3 (or the semiconductor substrate 401). Form. The element isolation insulating film 405 can be formed by thermally oxidizing the surface of the epitaxial layer 1403 (or the semiconductor substrate 4o1) using the mask 441. Element 1
0] The isolation insulating film 405 is formed of silicon oxide group as a result, and the element amount #!
The 48 edge film is formed with a relatively thin film thickness. After forming the element isolation insulating film 405, the mask 441 is selectively removed.

Next, as shown in FIG. 4L, in the formation region of the base region of the bipolar transistor Tr, the protruding island region 4
The mask 436 or the element isolation insulating film 405 at the corner part, that is, the shoulder part, of the side wall of 04 is removed.

to form a connection hole 407. This connection hole 407 is connected to the base area (409) and the 'IJL pole (408) for pace extraction.
A).

Next, a first & electrode forming layer is deposited over the entire surface of the substrate including on the element isolation insulating film 405 and on the i-layer 438. This electrode forming layer is formed using, for example, a polycrystalline silicon film deposited by the CVD method, and has a thickness of about 6000 to 8αOO [λ]. A portion of this electrode forming layer is configured to come into contact with the surface of the shrimp densified layer 4030 at the shoulder portion of the protruding island region 404 through the connection hole 407 .

Next, after forming a thin silicon oxide film on the surface of the electrode formation 1-, a p-type impurity is introduced into the electrode formation layer through the silicon oxide layer. The silicon oxide film is formed to prevent heavy metal contamination caused by the introduction of impurities and to reduce damage to the surface of the electrode formation r-. The p-type impurity is 1
Using B of about 0" (atoms/cd), 30 to 5
It is introduced by an ion implantation method with 0 (KeV) @ degree energy. This p-type impurity is introduced to reduce the resistance value of the electrode formation layer. The p-type impurity introduced into the electrode forming layer.

In the connection hole 407 portion, it is diffused from the electrode formation layer to the main surface of the epitaxial layer 403 to form a p + -type semiconductor region 409 . The p + type semiconductor region 409 is connected to the connection hole 4
It is formed in self-alignment with respect to 07. This p+ type semiconductor region 409 forms part of the base region.

Next, although not shown, a silicon oxide film and a photoresist film are sequentially laminated on the entire surface of the electrode forming layer. Then, using anisotropic etching, the uppermost photoresist film, silicon oxide film, and electrode forming layer are sequentially etched (back-etched) and flattened, that is, the protruding island regions 404
The electrode forming layer buried in the recessed portion between is removed, and the electrode forming layer deposited on the convex portion on the protruding island region 404 is removed to flatten the surface. Thereafter, the uppermost mask 438 on the protruding island region 404 is removed by isotropic etching.Next, as shown in FIG. 4M, an electrode formation layer of the active region Aat and an electrode formation of the isolation region Iio are A predetermined pattern is formed on the layer, and a base extraction electrode 408A and a dummy protrusion 408C are formed in the active region Act, and a dummy protrusion 408B is formed in the isolation region Iso. The pace extraction electrode 408A, the dummy protrusion 11408C, and the dummy protrusion 408B are each formed by the same manufacturing process. The electrode forming layer is patterned, for example, by anisotropic etching.

In this way, the electrode (408A) is connected to the semiconductor element (T'r, etc.) provided in the active region Act on the main surface of the semiconductor substrate 401.
In the method for manufacturing a semiconductor integrated circuit device LSI, in which the first layer wiring 426 extends with Hatoma insulation extensions (411, 421, 424) interposed in the upper layer of the electrode (408A), the semiconductor element The electrode (408
A) and the step of forming the dummy protrusions 408B arranged in a mesh shape are performed in the same manufacturing process, thereby forming the electrode 408A connected to the semiconductor element.
Since the die protrusion 408B can be formed in the step of forming the dummy protrusion 408B, the number of manufacturing steps of the semiconductor integrated circuit device ff1LsI can be reduced by an amount corresponding to the step of forming the dummy protrusion 408B.

Next, as shown in FIG. 4N, the high resistance RH of the memory cell is
In the formation region, a p − type semiconductor region 410 is formed on the main surface of the epitaxial layer 403 of the protruding island region 404 . The p-type semiconductor region 410 has a thickness of 1, for example 10 (a
toms/ai) l & degree B of 30-50 (K
It can be formed by introducing an ion implantation method with an energy of about 2.5 eV). By forming this p″″ type semiconductor region 410, the high resistance RH is completed. Note that the high resistance RH may be formed before the patterning step of the first electrode forming layer, that is, before the step of forming the base drawing Tt4408A.

Next, as shown in FIG. 40, the base extraction electrode 408
A top, dummy protrusion 408B top and dummy protrusion 408
The layer 11jl insulating film 411 is formed on the entire surface of the substrate including the layer 11jl insulating layer 1411, in order to improve the surface flatness, for example, a silicon oxide group coated by the CVD method and coated on top of it by the SOG method is used. It is formed from a composite film consisting of a silicon oxide film and a silicon oxide film. ! *The spacing film 411 is at least half the distance between the dummy protrusions 408B in the isolation region Iso.
For example, the lower silicon oxide group layer is formed to have a thickness of about 7000 to 8000 (A), and the upper layer silicon oxide group is formed to a thickness of about 1000 to 1500 (A). Further, the upper silicon oxide film coated by the SOG method is subjected to densification treatment after coating,
Anisotropic etching is applied to the entire surface to create interlayer insulation 'M441
The flatness of the surface of 1 may be further improved.

Next, a mask 442 is formed over the entire surface of the N opening 1411. The mask 442 is used as an etching mask for the interlayer insulating group 411 and a heat-resistant oxidation mask. The mask 442 is formed of, for example, a composite film of a silicon oxide film deposited by a CVD method and a silicon oxide film deposited thereon by a CVD method.

Next, the mask 442 is selectively removed in each of the base region and emitter region of the bipolar transistor Tr and the formation region of the scattering barrier diode SBD. Then, using the remaining mask 442, the interlayer insulation a411 is removed to form an opening 412. opening 4
Reference numeral 12 is formed so that a part of the surface of the base extraction electrode 408A on the side connected to the base region in the active region Act is exposed.

Next, as shown in the m4P diagram, using the mask 442 and the mask 437 on the protruding island region 404, an interlayer insulating group 41 is placed on the surface of the exposed part of the base extraction electrode 408A.
The 0-layer interlayer insulation layer 413 forming the base electrode 413 is made of a silicon oxide group formed by subjecting the surface of the base extraction electrode 413 to thermal oxidation treatment.
It is formed with a film thickness of about 0 to 4000 [A]. This interlayer loquat 413 is for pace drawer i! I, the pole 408A and the emitter lead-out electrode (419), the collector lead-out electrode (41)
9) and 5 to electrically isolate them from each other. In the mask 442, only a part of the pace extraction electrode 408A is subjected to thermal oxidation treatment, and the other parts of the base extraction electrode 408A, that is, the ends of the base extraction electrode 408A in the extending direction and the electrodes for separating the electrodes 408A are thermally oxidized. 405 is formed so as not to be subjected to thermal oxidation treatment.

This is caused by the element isolation insulator 405 directly below the end of the base extraction electrode 408A and the element isolation insulator 40 near it.
This is to prevent oxygen from being supplied into the semiconductor substrate 401 through the semiconductor substrate 401 . When oxygen is supplied into the semiconductor substrate 401, the surface of the semiconductor substrate 401 is oxidized,
Crystal defects are likely to occur within the semiconductor substrate 401.

Next, as shown in FIG. 4Q, the mask 442 is removed. Along with the process of removing this mask 442, the mask 437 on the protruding island region 404 is also removed.

Next, although not shown in the figure, there is a logic section Logic and a memory section Memory other than the one-way bipolar transistor Trl and the reverse bipolar transistor Try.
npn that connects each of the peripheral circuits (decoder circuits, etc.) of
2. Form an intrinsic space barrier of a type bipolar transistor (SICOS structure). ′ of this pibo 2 transistor
The JJc base region is an 11-way bipolar transistor Trl or a reverse bipolar 2-2 transistor Tr! Similarly, the protruding island region 404 is formed on the main surface of the epitaxial layer 403 . The intrinsic base area is, for example, 10”
(at.

tns /lyr&) 8 degrees B from 15 to 30 (Ke
It can be formed by introducing an ion implantation method with an energy of about V).

Next, in the formation region of the reverse bipolar transistor Tr, as shown in FIG.
4. Form each of the n-type semiconductor regions 415 in a j@th pattern. p
The base semiconductor region 414 is used as a base region and a potential barrier layer against minority carriers generated in the semiconductor substrate 401 due to α rays. p-semiconductor neck region 414 is %1
B of about 0” (atorr++s/cffl) to 140
It can be formed by introducing ions with an energy of about 160 [KeV: 1] using the ion injection method. The n-type semiconductor region 415 is used as part of a collector region. The n-type semiconductor region 415 has 10 (a tom
s/i, P of 1 frame degree is 140-160 (K e V
) can be formed by introducing energy by ion implantation method. The p-type semiconductor region 414
Each of the p-type impurity forming the n-type impurity and the n-type impurity forming the n-type medium/reservoir region 415 is formed within the region defined by the interlayer insulating film 413 formed on the surface of 408N for base extraction. be interrogated.

Next, the I'f1 direction bipolar transistor Try.

In each of the formation regions of the low resistance RL and the closed key barrier diode D, as shown in FIG. Each region 417 is formed sequentially. The p-type semiconductor core 416 is used as a potential barrier layer against minority carriers generated in the semiconductor substrate 401 due to the pace region and α rays. The p-type semiconductor region 416 can be formed by introducing B at 10 (atoms/cIl) by ion implantation with an energy of about 80 to 100 (K·V). It is used as a part of the emitter region, a part of the low resistance RL and a shut-keep parier diode SBD.The n-type semiconductor region 417 is 10"
(at oms/cIl) of P of 170 to 190
It can be formed by introducing an ion implantation method with energy on the order of (Kee).

Next, the forward direction bipolar transistor Tr/distor Tr, formation region,
In each of the reverse direction bipolar transistor Trl formation regions, the mask 436 on the protruding island region 404 is removed and a contact hole is formed.

collector opening) 418 is formed. The mask 436 is removed within the range defined by the J-opening edge film 413 formed on the surface of the base extraction electrode 408A.

Next, a second 'ftft formation layer 4! is formed on the entire surface of the substrate. Let it pile up. This electrode formation I- is formed with a film thickness of about 2000 to 3000 (A) using, for example, polycrystalline 1-silicon Xi deposited by the CVD method. A part of the layer 14 forming the contact hole 418 comes into contact with each of the n-type semiconductor regions 415 and 417 of the protruding island region 404 through the connection hole 418.

Next, a thin silicon oxide film is formed on the surface of the electrode formation layer, and four n-type impurities are applied to the electrode formation 1- through this silicon oxide film. The n-type impurity is, for example, 10 [at
oms/cb (] using the 8th of 8 degrees, 70-90 (K
eV) Introduced by ion implantation method with an energy of 8 degrees.

Next, the n-type impurity introduced into the electrode formation layer is subjected to activation treatment (heat treatment). Through this activation treatment, the n-type impurity introduced into the electrode formation layer in the connection hole 418 portion is transferred to the n-type semiconductor region. The light is diffused onto the main surfaces of 415° and 417°. The n-type impurity diffused into the main surface of the n-type semiconductor region 415 forms an n + -type semiconductor region 420 that becomes a part of the collector region of the reverse bipolar transistor Tr1. n diffused into the main surface of the n-type semiconductor region 417
The ff1 impurity forms an n-type semiconductor region 420 that becomes part of the emitter region of the forward bipolar transistor Trl. Through this step of forming the n+ type semiconductor region 420, each of the forward bipolar transistor Trl and the reverse bipolar transistor Trt is completed. AS as an n-type impurity has a slower diffusion rate than n-type impurities such as P, and can form a shallow emitter junction.

Next, as shown in Fig. 4T, form the second layer of 4m;
A pole 419 and a collector lead-out electrode 419 are formed respectively. The emitter lead-out electrode 419 is located in the processing region (n+ type semiconductor region 42) of the forward direction bipolar transistor Trl.
0).

%1419 for collector extraction is the collector region (n+ type semiconductor region 420) of the reverse direction bipolar transistor Tr.
connected to.

Next, apply insulation to the entire surface of the board including the top of the first emitter drawer-pole 419 and the top of the collector drawer mfk 419.
21 is formed. The glabella insulating film 421 is formed of a composite film of, for example, P S Gi deposited by the CVD method and a silicon oxide film coated thereon by the SOG method. Eyebrow desert 42
1 is formed with a film thickness of about 3000-5000 (A) square degrees, for example.

Next, in the capacitance element Ca formation region, the interlayer insulating film 421 is selectively removed to form an opening 422 through which the surface of the lower M electrode 419 is exposed.

Next, a dielectric film 423 is placed on the lower electrode 419 so as to contact the surface of the lower electrode 419 through the opening 422.
Each of the upper layer electrodes 423 is formed in one step. dielectric m42
3 and the upper layer electrode 423, fJU
As shown in the figure, the cord Ca is completely completed. Dielectric film 42
'3 is formed of Ta1O1 deposited by sputtering, for example, and has a film thickness of about 70 to 100 (A). The upper layer electrode 423 is made of M o S deposited by sputtering, for example.
Formed by i*.

It is formed with a film thickness of about 1500 to 2500 [A].

Each of the fat turtle body part 423 and the upper layer-pole 423 is formed in the same pattern.

Next, a glabella insulating film 42 is formed on the entire surface of the substrate including the capacitive element Ca.
The interlayer insulating film 424 forming part 4 is formed of PS GM deposited by CVD, for example, and has a thickness of 2500 to 3500.
It is formed with a film thickness of about (A).

Next, the interlayer insulating film 424 and the like on the emitter extraction electrode 419, the collector extraction electrode 419, the space extraction electrode 408A, the n-type semiconductor region 417, etc. are removed, and a connection hole 425 is formed.

Next, as shown in FIG. 4V, the first
A layer of wiring 426 is formed. The wiring 426 is formed of, for example, a composite film of a platinum silicide film 426A deposited by sputtering and aluminum &426B deposited thereon by sputtering. Shield Φ-barrier diode S
In the BD formation region, the platinum silicide M426A is directly in contact with the surface of the nff1 semiconductor region 417, forming a shield barrier diode SBD.

Next, the opening film 427, the second layer wiring 428, the interlayer insulating film 429, the third layer wiring 4301 and the interlayer insulating film 43
1.1 4th layer wiring 432, padge page seal-43
By sequentially forming each of 3, the semiconductor integrated circuit device LSI is completed as shown in FIG. 4A.

As described above, especially as shown in FIG. 4B, this embodiment is a combination of main frame combination
This is a logic/LSI with memory used in the PU section.

A gate array block is provided in the center, and Al(1)
~A l (4).

On the other hand, the memory sections on both sides are A I (1) to A I
(3), in particular, the complementary data i group DL made of Al(3) is orthogonal to the signal line group 555 made of Al(4) that connects a part of the gate array passing above it and the I10 cell. By doing so, they are arranged to reduce mutual coupling. - On the other hand, the word line group WL, which is composed of a lower layer Alt wiring and is relatively less affected by coupling as in this case, is arranged in parallel to the signal line group 555. In addition, in the above-mentioned FIG. 4B, the signal line 555. Although the word line group WL and the data group DL are shown distributed among the memory mats for convenience of drawing, it is not the case that they are provided for each memory mat or for each set of memory mats. Nor.

(5) Example 5 In the following description, the processes above A/(2) include the final page, badge page, Al(3), final page page, and the entire gate array with memory. Regarding the layout, those shown in the first to fourth embodiments are omitted.

Embodiment 5 of the present invention will be described below with reference to the drawings.

FIG. 5A is a plan view of a part of the static RAM (SRAM), and the left diagram is a plan view of a bipolar transistor that constitutes the peripheral circuit (I10 circuit, memory peripheral circuit).
The right factor is a plan view of two P-channel MISFETs and four N-channel MISFETs forming one memory cell. Note that a part of the gate array is composed of a CMOS circuit, but since it was mentioned in the previous example, the explanation will be omitted.

Figure 5B is a cross-sectional view taken along the line I--I in the left figure of Figure 5A, Figure 5C is a cross-sectional view taken along the line ■-■ in the right figure of Figure 5A, and the KSD figure is a cross-sectional view of the right figure in Figure 5A. It is a sectional view taken along the I■-■ cut Ur edge of the right figure.

In addition, FIG. 5A shows the structure of the element in order to make it easier to understand.
Insulating films such as field insulating films and interlayer insulating films are not shown.

First, the configuration of a bipolar transistor will be explained.

In the left diagram of FIG. 5A and FIG. 5B, 501 is a substrate made of P-type single crystal silicon, and N
A type buried layer NBL and a P type buried layer PBL are formed. The bipolar transistor has buried layers NBL, N
Type collector area 503, N type extraction area 504
, P''' type intrinsic pace region 506, intrinsic base lff#
P-type semiconductor region 505 as a lead-out region of 506
, N type emitter region 507. Collector region 503, intrinsic base region 506, semiconductor region 505
, emitter region 507 and collector extraction region 504
Each of these is formed on an epitaxial layer grown on a substrate 501. The area around the N-type buried layer NBL is P! It is surrounded by a lumped layer PBL and is isolated from other bipolar transistors (not shown).

As shown in FIG. 5B, N collector region 503, P+
type semiconductor region 505, P-type intrinsic base region 506, N
Each of the mold emitter regions 507 is formed on the digging layer NBL, that is, within the same protruding region on the substrate 501,
Further, the N type collector extraction region 504 is formed in a different protruding region from the above. Between these two protruding regions is the substrate 501 and the surface O11, that is, the wall J*N B
A surface of the L%PBL and a part of the side surface of the first protrusion region in which the collector region 503, the Pfi semiconductor region 505, the API: base region 506, and the emitter region 507 are provided;
The entire side surface of the second protruding region in which the collector lead-out region 504 is provided is separated by field insulation [502] made of &5'@ silicon group.

The +P type semiconductor region 505 is exposed from the field insulating film 502, and a base electrode 510 made of polycrystalline silicon is connected to this exposed portion in cell 7 alignment. The exposed surface of the base electrode 510 is covered with an insulating film 511 made of a silicon oxide group obtained by thermally oxidizing the base electrode (polycrystalline silicon film) 510. Note that the silicon oxide group 508 and silicon nitride 509 remaining on the intrinsic base region form the field insulating film 502 and the insulating film 5.
This was used as one screen when forming No. 11.

512 is an emitter electrode made of polycrystalline silicon &512
For example, W, Mo on top of A.

It is composed of two layers of high melting point metal J1.4 material 512B such as Ta, Ti, Pt, etc. or silicide G512B of high melting point metal such as these. Emitter electrode 512
An insulating film 514 made of silicon oxide/1lQj formed by CVD is exposed on the upper surface. The ivy 1a pole 512 has a connection hole 517 formed with insulating films 508, 509, 511.
It is connected to the vine area 507 through the hole. A side wall 513 formed at the time of forming a side wall 513 on a side surface of a gate electrode 512 of a MISFET, which will be described later, is attached to the side surface of the emitter pole 512. Board 5
Insulation U31 is formed by laminating a phosphosilicate glass (PSG) film on a silicon oxide film on the entire surface of 01.
5 is covered. Base electrode 510. - Mitter%
The connection hole 516 is provided in the pole 512, N extraction region 504.
Wiring 518 consisting of the first layer of aluminum spread through
B, 518E, and 518C are connected. Insulating film 51
For example, on top of 5, coated glass (5
An insulating film 519 is provided, which is formed by laminating a layer of OG) and further layering a PSG film, and the wiring 521 of the second layer is connected through a connection hole 520 formed by removing the insulation layer 519. is installed IM518B, 518E
, 518C.

Next, the structure of the memory cell shown in the right diagram of FIG. 5A, FIG. 5C, and mSD diagram will be explained.

The memory cell of this embodiment is a complementary MISFET, that is, a P-channel MISFET and an N-channel MISFET.
It is composed of FET. The equivalent circuit is shown in FIG. 5R.

In Figures 5A, 5C, and 5D, points P, , P,
, P, ,P is one memory cell area. P-channel MISFET that constitutes a memory cell
MP, , MP, , N channel MI 5FET MN, ,
, MN, , MN, , MN4 are each shown surrounded by a dot chain.

N-channel MISFET MN, MN, MN, ,
Each of MN4 is configured in a P well region 527 provided above the buried/#P B LO. On the other hand, P-channel MISFET MP,.

MP is an N-well region 53BB provided on the buried layer NBL. Said N channel MI 5F
Each of ET MNs, MNt, MNs, and MN4 has a gate electrode formed of a silicon oxide film formed by thermal oxidation of the surface of the well region 527, and W and Mo on the polycrystalline silicon film 512.

A gate electrode 512 formed by laminating a high melting point metal 512B such as Ta, Ti, Pt or the like or a silicide film 512B of the high melting point metal. It is composed of an N-W semiconductor region 524 and an N-type semiconductor region 525, which constitute source and drain regions. The gate electrode 512 is in the same layer as the emitter 1; pole 512 of the bipolar transistor. The distance between the gate' electrode 512 and the N" type semiconductor region 525 is defined by a sidewall 513 made of silicon oxide group. N-channel MI 5FET MN, MN, MN
N.

MN, game 1 [f1512 polycrystalline silicon film 512
A is made N-type by introducing an N-type impurity such as phosphorus or arsenic. N-channel MISFET MN, and M
The gate electrode 512 of N.sub.2 is formed integrally with the word bWL extending over the field insulating film 502. M
An Nff1 semiconductor region 526 is provided near the ISFET MN+, which is a field isolation v!
, 502, an N-type impurity in the polycrystalline silicon film 512A of the 1N4 gate electrode 512 is diffused into the well region 527.

A portion of the gate insulator M522 above the N-type semiconductor region 526 is an opening 523, through which the gate electrode 512 is connected. The top of the gate electrode 512 is covered with a wire 14 made of a silicone film.

N-channel MISFET MN, MN, MN, ,
P well region 52 in which each of MN and MN is provided.
7 is a collector region 503 of a bipolar transistor;
Like the P-type semiconductor region 505, the intrinsic base region 506, the emitter region 507, and the extraction region 504, it protrudes above the surface of the buried layer PBL, that is, the surface of the substrate 5010.

The P-channel MISFETs MP's and MPt are coated on the N well region 531 provided on the surface of the +N buried layer NBL, that is, the surface of the substrate 501, and are made of silicon oxide group by thermal oxidation of the surface of the well region 531. A gate wire film 522, a gate electrode 512 formed by forming 81 layers of high melting point gold maple or high melting point gold-silicide PA512B on a polycrystalline silicon film 512A, and a P-type semiconductor region 529 forming source and drain regions. It consists of

Polycrystalline silicon film 512A forming gate electrode 512 of P-channel MI 5FET MP+, MPt
is made into a P-type by introducing a P-type impurity such as boron. An opening 523 is formed near the P-channel MISFET MP, and the gate 'fM and pole 512 extending from the N-channel MISFET MN are connected to the well region 531 through the opening 523. The gate on the surface of this well region 531 is connected to the pole 512.
A P type impurity such as boron in the polycrystalline silicon film 512 is diffused into the connected portion to form a P type semiconductor region 530.

The N-well region 531 constituting the P-channel MISFET is connected to the N-channel MISFET MN, MNt.
, MN, , MN, are configured in the P-well region 5
27, above the buried layer NBL, that is, the substrate 501.
protruding above.

As shown in the fifth A[N, + The N buried layer NBL and the P buried layer PBL are.

The direction in which the word & WL extends, in other words, the data iD,
It extends in a direction intersecting the direction in which D extends.

Further, the N buried layers NBL and the P buried layers PBL are arranged alternately in the direction in which the data ID and D extend. N-channel MI 5FETs MN, and MN are configured in the same P well region 527, and N-channel MI
SFETs MN and MN4 are configured in the same P-well region 527. On the other hand, P-channel MISF
ETMP1 and MP are configured in different N-'' well regions 531.These four well regions 5
Between 27 and 531, element isolation is provided by a field insulating film 502- and buried layers NBL and PBL. That is, element isolation between MISFETs is performed in the same manner as element isolation between bipolar transistors. In each N″″ well region 531, word lines WL,
Wiring 5 in the same layer as the gate electrode 512 and emitter electrode 512
12 is connected through the opening 523, and this wiring 512 connects 1! A source potential VCC of, for example, 5V is applied. That is, potential VCC is applied within the memory cell. The polycrystalline silicon film 512A of the wiring 512 is made into N-type by introducing an N-type impurity such as phosphorus or arsenic. In a portion of the surface of the well region 5310 to which the wiring 512 is connected, an N-type semiconductor region 526 is formed by diffusing N-type impurities in the polycrystalline silicon film 512.

Data i? is sent to the p-well 11527 for each predetermined number of memory cells such as 4 cells, 8 cells, or 16 cells.
D, The second layer of aluminum extends in the same direction as D! A circuit ground potential V88, for example Ov, is applied to the P-buried layer PBL from (not shown). The second layer wiring to which this potential 18B is applied is connected between memory cells. A well region 527 separated from other P well regions 527 is provided in the part where the potential Vi8 wiring of the P buried 7JPBL is connected, and a P well region 527 is provided through this P well region 527.
Power is supplied to the buried layer PBL, and the P-channel MISFE
Power is supplied to the P well region 527 in which the TMP, . P well region 527 to which the aluminum wiring that supplies power to VI8 is connected.
On the surface of the P-channel MISFET MP, , MP
, P in the same process as the source and drain regions 529
forming a type semiconductor region.

518 is the first layer of aluminum wiring, and the connection hole 5
16 is connected to the upper surface of the gate electrode 512, the upper surface of the N type semiconductor region 525 serving as the source and drain regions, or the upper surface of the P type semiconductor region 529. The data iD and D are made of a second layer of aluminum film, and are provided on one of the N semiconductor regions 525 of the N channel MISFETs MN and MN.
518, a connection hole 520 formed by removing the insulating film 519
connected through. N-channel MISFETMNs
Each of the N type semiconductor regions 525 constituting a part of the source region of MN4 and MN4 is provided with a ground potential VSS wiring made of a second layer of aluminum film. ! 528 is connection hole 5
20. Aluminum wiring - 518. Connected through connection hole 516.

As explained above, according to the bipolar transistor and MISFET of this embodiment, the N-channel MISFE
T MN,, MN,, MN,, MN4 are composed of N
Well region 531 and P channel MISFET M
P,,MP! The P well region 527 in which the bipolar transistor is formed is the protruding region in which the collector region 503 of the bipolar transistor, the intrinsic space region 506, the + P type semiconductor region 505, and the emitter region 507 are formed, or the protruding region in which the extraction region 504 is formed. By having a structure similar to that of MI
Similar to the isolation between bipolar transistors, element isolation between the 5FETs can be performed using the field isolation R film 502 and the PN junction between the N2 buried layer NBL and the P+ buried layer PBL.

Next, the manufacturing method will be explained.

Figure 5EA, Figure 5EB, Figure 5EC to Figure 5EA,
5EB and 5EC are plan views or cross-sectional views in the manufacturing process. In addition, Fig. 5EA, Fig. 5EB, Fig. 5
As in EC drawings, the drawing number consists of Arabic numerals and alphabets, and cross-sectional views with the same first alphabet are cross-sectional views in the same process, and regarding the second alphabet, A indicates the same part as Figure 5B. cross section,
B represents a cross section of the same part as the MSC diagram, and C represents a cross section of the same part as the ISD diagram.

As shown in Figures 5EA, 5EB, and 5EC, P
An N buried layer NBL is formed by introducing an N type impurity such as antimony or lithium into the surface of the type single crystal silicon substrate 501, for example, by ion implantation, and a P buried layer PBL is formed by introducing a P type impurity such as boron. Form. After this, epitaxial r&1
Grow Epi.

Next, as shown in FIGS. 5FA, 5FB, and 5FC, the epitaxial layer Ep1 is injected with Nu, for example, by ion implantation using a mask made of, for example, a resist film.
An N well region 531 is formed by introducing an impurity such as antimony or phosphorus.

Further, a P-type impurity such as boron is introduced to form a P-well region 527.

Next, as shown in FIG. 5G, FIG. 5HA, FIG. 5HB, and FIG. 5HC, the entire surfaces of the well regions 527 and 531 are thermally oxidized to form a silicon oxide film 508. Silicon nitride film 509. An rII silicon pattern 532 is formed.

Then, for example, the silicon oxide film 532, silicon nitride, W2O3, and silicon oxide film 508 are etched by reactive ion etching (RI) using a mask made of a resist film.
E) in a predetermined pattern, that is, the collector region 503 of the bipolar transistor, the semiconductor region 505 .
A protruding region (first region) in which an intrinsic base region 506 and an emitter region 507 are provided, a protruding region (second region) in which a collector extraction region 504 is provided, and N-channel MISFETs MN, MN, MN.

MN,, P channel MISFET MP,, MP.

The pattern of the protruding region (third region) is etched. Further, it is also possible to form the protrusion by wet etching instead of RIE. After this etching, the mask consisting of the resist film is removed.
Next, P well region 527 or N well region 531
The exposed portions of the silicon oxide films 532 and 508 and the silicon nitride film 509 on the surface of the silicon nitride film 509 are rounded to a predetermined depth.
By etching with IE, the silicon oxide film 532, silicon nitride 1ff1509. The portion covered by the silicon oxide film 508 is made to protrude. Here, the predetermined depth means that when the field insulating film 502 is formed later, the bottom of the field insulating film 502 is the buried layer N.
The depth is such that it reaches BL%PBL.

Next, as shown in FIG. 5IA, FIG. 5IB, and FIG. 5IC, so as to cover the entire surface of the well regions 527 and 531,
For example, a silicon nitride film 533 is formed by CVD,
This is etched by RIE until the upper surfaces of the well regions 527, 531 are exposed, and the well regions 527, 531. Formed on the side surfaces of silicon oxide group 508, silicon nitride 11Q 509, and silicon oxide group 532.

Next IC1 Fig. 5J, wSKA Fig. 5KB, Fig. 5K
As shown in Figure C, the collector region 503 of the bipolar transistor, the P semiconductor region 505, and the intrinsic base region 5
06. After the protruding region where the emitter region 507 is formed is covered with a mask made of a resist film, the sidewall 533 exposed from this mask is removed. After selectively removing the sidewall 533, the mask made of this resist film is exposed from each of the silicon oxide film 532, silicon nitride film 509, and silicon oxide WA 508 in the P-well region 527. surface and N
Sidewall 533 of well region 531, silicon oxide JIIj532. The exposed surfaces of the silicon nitride film 71509 and the silicon oxide film 508 are thermally oxidized to form a field insulating film 50 made of a silicon oxide film.
form 2. The bottom surface of the field insulating film 502 is a buried layer NBL%, the top surface of the P well region 531 is a silicon oxide film 532, a silicon nitride film 532, a silicon oxide film 5
Only the protruding portion that is backward at 08 remains.

Here, N-channel MISFET MN,, MN,.

MN,, MN4. P-channel MISFET MP.

The shape of the field insulating film 502 in MP is the same as that of the field insulating film 502 in the protruding region where the lead-out region 504 of the bipolar transistor is formed. In this way, element isolation between MISFETs and between MISFETs and bipolar transistors is performed in the same process as element isolation between bipolar transistors. In addition, the fifth
502A in Fig. J indicates a bird's beak portion of the field insulating film 502.

After forming the field isolation M film 502, a mask made of a resist film with a pattern exposing the sidewall 533 is formed on the buried layers NBh and PBL, and then the sidewall 533 is removed by etching. During this etching, the silicon nitride film 509, that is, the collector region 503, exposed from the mask made of the resist film,
P semiconductor region 505, intrinsic pace region 506, engineering? Silicon nitride y5 on the protruding region forming the ivy region 507
The side of 09 is etched and recedes. After removing the sidewall 533, the mask made of the resist film used for etching is removed.

Next, as shown in FIG. 5LA, FIG. 5LB, and FIG. Using a mask made of a resist film with a pattern that exposes the protruding region to be formed, the side surfaces of the silicon oxide film 508 exposed from this mask are etched and retreated. After this, the mask made of the resist film is removed, and the buried layer NBL is formed.

A polycrystalline silicon film 510 is formed on the entire surface of the PBL by, for example, CVD. Next, a P-type impurity such as boron is introduced into the polycrystalline silicon 11A 510 by, for example, ion implantation, and annealing is performed. At this time, P type impurities in the polycrystalline silicon @S10 are introduced into the side surface of the N well region 531 on which the polycrystalline silicon film 510 is deposited to form a P semiconductor region 505.

Next, as shown in FIG. 5M, FIG. 5NA, FIG. Next, the exposed surface of the pace electrode 510 is thermally oxidized to form an insulating film 511 made of a silicon oxide film. silicon nitride film 50
9 serves as a mask for thermal oxidation.

Next, firewood 50 diagram, 5th PA diagram, 5th PB diagram, 5th PC
As shown in the figure, the exposed silicon nitride film 509 is etched, and the silicon oxide +1IA 508 is further etched. The exposed upper surfaces of the P well region 527 and the N-well region 531 are thermally oxidized to form a gate insulating film 522 made of silicon oxide. Next, P is etched by ion implantation using a mask made of a resist film.
″″Intrinsic base area 506, N engineering is ivy area 507,
Next, by etching using a mask made of a resist film, the gate insulating film 522 on the ivy region 507, the gate insulating portion that will become the opening 523, and the 1fi 522 are removed, respectively. After etching, the mask consisting of the first resist is removed, and the buried layer PBL% is removed by, for example, CVD.
Polycrystalline silicon 111512A is formed over the entire surface of the NBL. This polycrystalline silicon fi512A connects a portion above the P buried layer PBL and a wiring 5 that supplies potential VCC above the +N buried layer NBL.
For example, by ion implantation, N is applied to the part that becomes part of 12.
A type impurity such as phosphorus or arsenic is introduced, and a P-type impurity is introduced into other parts to lower the resistance. Said polycrystalline silicon! During annealing to activate the impurity introduced into the polycrystalline silicon film 5512A, the N-type impurity or the P-type impurity in the polycrystalline silicon film 512A is diffused through the opening 523 to form an N-type impurity.
A semiconductor region 526 and a P semiconductor region 530 are formed. At the same time, an N+ emitter region 507 is formed.
Alternatively, the +N semiconductor region 526 and the P semiconductor region 530 may be formed in the opening 5.
Before forming 23, it may be formed by ion implantation using a mask made of resist 1, and the N 2 nitride region 507 may be formed by diffusion from the polycrystalline silicon film 512A.

Further on the polycrystalline silicon IQ512A, a high melting point metal layer such as W, Mo, Ta, Tt, Pt, etc. is formed by CvD or sputtering, and then it is annealed to form a high melting point metal silicide film. 512B is formed. Further, a silicon oxide pM514 is formed on the high melting point metal silicide film 512B by, for example, CVD.Next, by etching using a mask made of a resist film, the silicon oxide film 514, the high melting point modern silicide film 512B1 and the polycrystalline silicon film are etched. 512A is sequentially etched to form the emitter electrode 512, gate electrode 512,
Word ll! First, wiring lines 512 for supplying power to WL and VCC are respectively formed. Next, an N type impurity such as phosphorus is introduced by ion implantation using a resist mask to form an N semiconductor region 524.

After forming the N semiconductor region 524, from FIG. 5A to #5
The sidewall 513 shown in FIG. D is made of silicon oxide formed by CVD, for example. N channel MI 5FET
MNr, MNl, MNs, N semiconductor region 525 which is part of the source and drain regions of MN4, and P-channel MISFET MP.

P semiconductor region 5 which is the source and drain region of MP
29, For example, silicon oxide film and PSG by CVD
Insulating film 515 made of 11M, connection hole 516, wiring 518, 518B, 518C, 518E1 made of first layer aluminum film by sputtering, for example, CVD
An insulating film 519 made of a laminated silicon oxide film, a coated glass film, and a PSG film, a connection hole 5201, an arrangement n521 made of a second layer aluminum film, for example, sputtered.
,528. Data mD and D are respectively formed.

Further, an interlayer insulation layer is further formed on A I (2) by any of the methods described in Examples 1 to 4 and so far. In addition, as shown in Section 5A (AJ(3)
A bypass signal line group 550 is formed that passes above the memory mat according to the method, and a final padding film is formed thereon, and then, if necessary, the bypass signal line group 550 is formed above the memory mat.
3) A predetermined portion of the upper final badge page opening is opened to form bonding pads or CCB pads, and the present LSI chip is completed.

As explained above, the collector region 50 of the substrate 501
3. P A first region where a semiconductor region 505, an intrinsic space region 506, and an emitter region 507 are provided, a second region where a collector extraction region 504 is provided, MI 5FET
silicon nitride g on each of the three regions where
SO9 (IT mask) is formed, and the periphery of each of the first, second and third regions is etched to make the first, second and third regions protrude, and a side surface of the protruded first region is etched. Form silicon nitride A533 (12 masks),
By oxidizing the surface of the substrate 1 exposed from the first and second masks to form field insulation M502,
Since element isolation technology between bipolar transistors is used for element isolation between MISFETs and between MISFETs and bipolar transistors, element isolation between two piebolad transistors, between MISFETs, and between bipolar transistors and MISFETs is the same. It can be done in a process.

Each of Figures 5QA, 5QB, and 5QC is a cross-sectional view of the semiconductor integrated circuit device in Example 1H, and Figure 5QA is a cross-sectional view of the same part as Figure 5B, and Figure 5Q is a cross-sectional view of the same part as Figure 5B.
Figure B is a sectional view of the same part as Figure 5C, and Figure 5QC is a cross-sectional view of the same part as Figure 5C.
It is a sectional view of the same part as figure D.

In this embodiment, the pace voltage 1rI of a bipolar transistor is
1510 and P-channel MISFET MP.

MP,, N channel MI 5FET MN,, MNl
.

MN@g Each gate of MN4'FtL pole 51
For example, CV
Polycrystalline silicon 1lk510A by D and W, No.

It is composed of two layers F including a high melting point metal film 510B such as Ta, TI, Pt, etc. or a silicide Jfu 510B of these high melting point metals. Further, the emitter region 507 of the bipolar transistor is defined by a sidewall 513 made of a silicon oxide film formed by CVD, for example, provided on the side of the gate electrode 510, and an N-channel MISFET
MN.

The high threshold region 525t of the source and drain regions of MN, MN, MN is defined by a sidewall 513 formed in the same process as the sidewall 513 provided on the side of the base electrode 510.

A silicon oxide film 514 is formed by, for example, CVD on the high melting point metal film or the high melting point metal silicide film 510B. The polycrystalline silicon film 510A is a trench layer PBL.
After forming on the entire surface of the buried layer PBL and the buried layer NB, for example, by ion implantation, the portion on the buried layer PBL and the buried layer NB are formed.
N-type impurities are introduced into a portion of the portion above L that becomes part of the wiring 510 that supplies potential VCC, and P-type impurities are introduced into other portions to lower the resistance.

The N semiconductor region 526 of the Mepeak recell region is formed by diffusing an N type impurity such as phosphorus or arsenic in the polycrystalline silicon *510A, and the P semiconductor region 530 is formed by diffusing a P type impurity such as boron in the polycrystalline silicon 1510A. It is formed by Furthermore, the P semiconductor region 505 of the bipolar transistor is made of polycrystalline silicon &510
It is formed by diffusing a P-type impurity such as boron inside.

The ET region 512 of the bipolar transistor is made of polycrystalline silicon, which is the second layer of the cylinder, for example, made by CVD. EITSUTA [1512 is a base portion with an opening above the emitter region 507, and a side wall 513° formed on the 5I11 surface of the pole 510.
It is connected to the eight pointer region 307 through a connection hole 517 formed of silicon oxide N508. The film thickness of the sidewall 513 in the lateral direction, in other words in the planar direction, is K[l-included layer NBI, in order to form the sidewall 513.

This can be controlled by adjusting the thickness of the silicon oxide film formed on the top of the PBL. On the other hand, the emitter region 507 is
It is formed by diffusing an N-type impurity such as phosphorus in the emitter electrode (polycrystalline silicon II!D). However, the ivy region 507 may be formed by ion implantation using a mask made of resist.

As explained above, the gate electrode 51 of the MISFET
A high concentration region 5 of the source and drain regions is provided on the side of the source and drain regions.
The sidewall 513 defining 25 and the sidewall 513 of I- are connected to the emitter electrode 5 of the base electrode 510.
Since the emitter region 507 is formed around the opening through which the electrode 12 passes through, the emitter region 507 is formed in a cellulose-poor manner with respect to the base electrode 510, so that miniaturization and high-quality rapeseed can be achieved. Further, since the sidewall 513 of the bipolar transistor and the sidewall 513 of the MISFET are formed in the same process, an increase in the number of manufacturing steps can be suppressed.

Note that the polycrystalline silicon film of the same layer as the Entsuta electrode 512 is used as a P-channel MI 5FET MP, MP.

The source and drain regions of the P semiconductor region 529 and the N-channel MISFET MN, respectively.

Provided as an electrode on the N semiconductor region 525, which is a part of the source and drain regions of MN, MN, MN4, and connected to the aluminum arrangement a518,
The wiring 518 may be connected to the +P semiconductor region 529 and the N+ semiconductor region 525 by a self-line. It is removed when the wall 513 is formed.

Further, the electrode made of polycrystalline silicon group on the N 2 semiconductor region 525 and the gate electrode 510 are insulated by a silicon oxide film 514 and a sidewall 513.

In this embodiment, the planarization of the substrate 501 is achieved by providing a conductive layer of the same layer as the base electrode 510 and a thermal oxidation mask 533 around the collector lead-out region 504 and around the MISFET region, respectively, in an insulated manner. Further, the encroachment of the field insulating film 5020 is reduced to eliminate the need for dimension conversion.

This example will be explained according to the manufacturing process.

Figure 5SA, Figure 5SB to Figure 5VA, and Figure 5VB are cross-sectional views in the manufacturing process. Figures with the same first letter of the number represent cross-sections in the same process, and the second letter A is M2R. A cross-sectional view of the same part as in the figure, second alpha-pella) B represents a cross-section of the same part as in Fig. 5C. Note that a cross section in the manufacturing process at the same portion as in FIG. 5D is not shown.

ψ: As shown in Figure 5SA and Figure 5SB, 5HAli! 7I, the process up to Figure 5HB and ゛
+ Similarly, N buried layer NBL, P ffi buried layer P
BL, P well 527, N well 531, silicon oxide film 508, silicon nitride film 509, silicon oxide LZ! After forming the P well region 527 and the N well region 531, the P well region 527 and the N well region 531 are patterned into a predetermined pattern.

Next, as shown in Figure 5TA and Figure 5TB, trap N”m
A silicon nitride film 533 is formed over the entire upper part of the buried FWINBL and the P+ buried layer PBL(1') by, for example, CVD.

Next, as shown in FIG. 1 SUA and FIG.
The sidewall 533 is formed by etching until the upper surface of the well 531 is exposed, and then the P'''' well 5 is etched.
A field insulating film 502 is formed by thermally oxidizing the surface exposed from the oxide silicon film 509 and sidewall 533 of the second well 531.

Field insulation 9502 is connected to the collector region 503. of the bipolar transistor. Not only in the protruding regions where the P semiconductor region 505, the intrinsic base region 506, and the emitter region 507 are formed, but also in the protruding regions forming the collector lead-out region and the protruding region where the MI 5FET is formed, only on the side surfaces of these protruding regions. Therefore, the field insulating film 502 does not dig into each of the above-mentioned protruding regions, resulting in one-dimensional conversion, that is, the size of each protruding region before and after the field insulating film 502 is formed. The difference between the two is disappearing.

Next, as shown in FIGS. 5VA and 5VB, by etching using a mask made of a resist film, the collector region 503, the P semiconductor region 505, the intrinsic base exchange region 506, and the emitter region 50 of the respective protruding regions are etched.
The sidewall 533 is removed only in the protruding region where the N well region 531 is provided to expose the side surface of the N well region 531. Thereafter, a polycrystalline silicon film 510 is formed over the entire upper part of the N+ buried layer NBL and the P buried layer NBPBL by, for example, CVD. This polycrystalline silicon film 510+
The protruding regions forming the collector region 503, P type semiconductor region 505, intrinsic base region 506, and emitter region 507 are attached to the side surfaces of the N well region 531, but the protruding regions where the collector extraction region 504 is formed are In the protruding region forming the MISFET, a PW impurity such as boron is introduced into the polycrystalline silicon film 510 by ion implantation into the zero order which is insulated by the sidewall 533, and is annealed to lower the resistance. The P type impurity is diffused into the N'''' well region 531 on which the crystalline silicon film 510 is deposited to form the P+ semiconductor region 505. That is, the upper portion of the silicon nitride film 509 is removed by etching using a mask made of a resist film.

The mask made of resist film is removed after etching. P The polycrystalline silicon film 510 connected to the semiconductor region 505 is the base electrode 510, and the polycrystalline silicon film 510 is provided around the protruding region where the collector extraction region 504 is provided and the protruding region where the MISFET is provided. May be separated.

Since the space between each protruding region is filled with a polycrystalline silicon film 510, planarization on the substrate 501 can be achieved.
The exposed surfaces of 10 are thermally oxidized to form an insulating layer 511 made of a silicon oxide film. Next, the exposed surfaces of silicon nitride hI 509 and silicon oxide ILC 508 on the upper surface of each protruding region are exposed from the edges 511. By etching the P″″ shell region 527, N
″″The surface of the well region 5310 is exposed.

The subsequent steps are shown in FIG. 50 of Part I of this embodiment.

The steps after the steps shown in FIG. 5PA, FIG. 5PB, and FIG. 5PC are the same.

As described above, according to this embodiment, field insulation around the protruding area (second protruding area) where the collector extraction area 504 of the bipolar transistor is provided and the protruding area (brush 3 protruding area) where the MISFBT is provided The film 502 is formed into a collector region 503 of the IBO-2 transistor.
6. Similar to the field insulating film 502 of the protruding region (first protruding region) where the emitter region 507 is provided, by not providing it on the upper surface thereof, the field insulating film 502 is not dug in, so the amount of dimensional conversion is reduced. can be eliminated.

Furthermore, by leaving the polycrystalline silicon film (conductor layer) 510 in the same layer as the base [pole 510] on the field insulation layer 502, the spaces between the respective protruding regions are filled, so that the flattening of the substrate 501 is achieved. can be measured.

The arsw diagram is a cross-sectional view of a bipolar transistor, the fifth
FIG.

FIG. 5XB is a plan view of the SRAM with the first conductive layer removed.

FIG. 5Y is a sectional view taken along the line II in FIG. 5X. FIG. 5Y shows all the conductive layers from the first layer to the second layer and the third layer. Further, in FIGS. 5XA and 5XB, the field insulating film 502 and the interlayer insulating film are not shown in order to make the structure of the device easier to understand.

The memory cell of the SRAM of Example 5 (2) includes two high resistances R, four N-channel MISFETs MN,
, MNt, MNs, and MN4.

The base electrode 510 of the bipolar transistor, the gates of the N-channel MISFETs MN, MNl, MN, MN, and the wiring 510 for supplying the ground potential Vsm to the electrode 510 and the substrate 501 are each made of a first layer formed by CVD, for example. polycrystalline silicon film 510A and a high melting point metal film or high melting point silicide film 51 laminated thereon.
It consists of 0B. A P-type impurity such as boron is introduced into the polycrystalline silicon film 510A of the base electrode 510.
MISFET MNs, MNs, MNA
-MN4 gate 1. The polycrystalline silicon @510A of the pole 510 and the wiring 510 is doped with an N-type impurity such as phosphorus or arsenic. The arrangement j510g is an insulating film 514 made of a silicon oxide film formed by, for example, CVD or the like.
An insulating film 534 made of silicon oxide and silicon oxide is further formed by laminating a silicon oxide film, a coated glass film, and a PSG film on top of this by, for example, CVD. The first
Layer #518 made of aluminum and san connects,
The ground potential Vilsi is supplied through this distribution MI518. Placement 1+! 518 is also a MISFET
N semiconductor region 525 which is part of the source region of MN4
0 surface through a connection hole 516. The load resistance R and the conductive layer 535 are made of a second-layer polycrystalline silicon film formed by, for example, CVD, and an N-type impurity such as phosphorus or arsenic is introduced into the conductive layer 535 by, for example, ion implantation to lower the resistance. There is. An insulator @534 made of a silicon oxide film formed by CVD, for example, insulates between the gate square 510, the arrangement 7pJ510, 4'WI, the layer 535, and the load resistor R. The conductive layer 535 is connected to the upper surface of the gate electrode 510 or to the N2 semiconductor region 526 through a contact hole 536 formed by removing the insulating film 534 and the insulating film 514 or the gate insulating film 522.

D is a MISFET MN, which is made from the first layer of aluminum film by sputtering, for example.
It is connected to one N semiconductor region 525 of MN through a connection hole 516.

N-channel MISFET MN, , MNI , MN,
, MN, each has N buried layers NBI.

configured in an N-well region 531 protruding from the surface of the
Also, N-channel MISFET MN, , MN, , MN
, , MN are separated by a field insulating film 502 and a P buried 4PBL.

Here, similarly to the previous example of this embodiment,! As shown by the dashed line 5 in the 5XB diagram, a signal line 550 made of A I (3) is formed to connect a part of the gate array above the memory and the I10 cell. Part of the gate array is A l (1
) to Al(2), signals can be freely extracted from a part of the gate array using A/(3). In this case, the I10 circuit and the memory peripheral circuit are constituted by BICMOS circuits, while the memory cells and part of the gate array are formed by single channel MO8 type SRAM cells and CMOS logic circuits, respectively, so the low Gate array LSI with memory that consumes less power and has high external drive capability
can be supplied.

(6) Explanation of literature, patents, and applications to supplement each embodiment ECLI: For logic and memory circuits, etc., see "Digital Integrated Circuits J (T
aub & Sohilling, 1977; M
eGraw-Hllll, Jnc, @Digital
416~ of IntegratedC1rw1ts'')
As explained in pages 431 and 229-256,
This is hereby made a part of the description of this application.

Regarding the design and manufacturing method of gate arrays, please refer to "Modern MOS Technology J (D*G, Ong," 19F+6, 1986, published by the same company) by Ong.
McGray-Hi 11 eJnc, @mod
ern MOS Technology 327~3
Since it is explained on page 31, it becomes part of the description of this application.

Furthermore, for the detailed circuit system of each part of bipolar memory, see Luga, Mize, and Kerr.

``Semiconductor Memory Design and Application Book'' published by the company in 1973 (Luecks, Italy, mlz@* and Carr, e 1973)
*McGraw-H1ll Jnc・,”Sem1co
nductor memory d+s1gnand
appllcatlon"), pages 93 to 113, which are hereby incorporated as part of the description of the present application.

Also, regarding the construction method of CMOS gate array, please refer to the magazine "
This is explained in the article by Fujii et al. in the July 1986 issue of Electronic Materials J, pp. 86-91, and is hereby incorporated as part of the description of the present application.

Furthermore, the details of the structure of the gate array with memory are explained in the article by Shimizu on pages 66 to 71 of the same issue of the same magazine, which is hereby incorporated as part of the description of the present application.

Also, regarding the structure of the ECL gate array, bat and I10 cell arrangement, package, basic circuit, device, etc., please refer to the articles in the column on pages 104 to 109 of the same issue of the same magazine, and the articles on pages 110 to 110 of the same issue.
It is explained in the article by Art Materials et al. on page 115, and is hereby incorporated into the description of this application.

Furthermore, regarding the TAB technology of ECL gate array, see 1.
985 "Solid State Circuit-Can77"
Lens Proceedings J (The proceeded -1ng
s of the 5old-8tit@C1rcu
its Con-f@r@nce)'s 200-20
Page 1 /' 7 Hans Ullr
Since this article is described in the article by (iah) et al., it is hereby incorporated as part of the description of the present application.

Furthermore, ECL-PLA (ECL Programab
l@Array Logic IC), see Milhoran (M, S, Mi
As explained in the article by llhollan et al.
This is expressed as part of the description of the present application.

Furthermore, bipolar memory cell circuits, worded 2 IPers, array drivers, and cell layouts.

For other systems, see Proceedings 21 of 1986.
0-211 membered chi + y (Y*H, Chan) et al. as described in the article, which is incorporated herein by reference.

Furthermore, the device structure of the ECL-RAM of BICMO3# includes a wine input buffer, a word decoder, a word driver, a memory cell, a level control circuit,
The sense amplifier, output buffer, and overall system are explained in the article by Ogiu Z (K, 0g1ue) et al. on pages 212-213 of the same Proceedings in 1986, so this is a part of the description of this application. Nasu.

Furthermore, the details of the high-speed bipolar ECL-RAM circuit,
In other words, regarding the cross-sectional structure of the address buffer, @ operation timing, word driver, and memory cell, 1
Ya1guchi (K, Y
As explained in the article by Amaguchi et al.
This is hereby made a part of the description of the present application.

In addition, regarding the device cross section and bit line configuration of the peripheral ECL BICMOS@SRAM, please refer to the 1988
Tran (HeV*Tra) in the same year's proceedings, pages 188-189.
n) et al., and is hereby incorporated into the description of this application.

Furthermore, from ECL of BIC~its-8RAM to BICM
Conversion circuit to O3, read/write circuit.

Column sense circuits, timing charts, etc. are explained in the article by R.A. Kartim et al. on pages 186-187 of the same Proceedings in 1988, so this is hereby incorporated as part of the description in this application. Eggplant.

Furthermore, poly S10-doped N-ah MOS memory cells
Outline of type B ICMOS-RAM differential 5 chair,
Overall layout, input buffer.

For connections between memory cells and peripheral circuits, see 198
Tanno ((N.

Tamba et al., which is incorporated herein by reference.

Also, regarding the configuration method of logic cells and voltage source wiring (Vga, V(c)) of a CMOS gate array, see 198 of the same document.
For the 8th grade child @#, block (-g(R, Bl)
umberg), which is hereby incorporated by reference as part of the description of this application.

Furthermore, regarding the role of the CMOS gate array and how to configure each block and power path line, please refer to Fi
t 198 s Collection of manuscripts 72-73 Sada no Takechi (M, T
akechi et al., which is hereby incorporated by reference as part of the description of this application.

Also, SST (Super Self-aligned)
ed process Technology ) is used ~
・For the gate array, see the 1988 collection of manuscripts 70.
~71 True Suzuki (M.

5uzuki et al., this is hereby incorporated as part of the description of the present application.

Furthermore, the device structure and read/write circuit of ECL-RAM having PNP) transistor load memory cells are explained in the 1983 Proceedings, pp. 106-107, and the description of this application is based on this. Part of it.

Furthermore, for similar parts of different types, the same
Toyoda (K, To
7oda et al., which is incorporated herein by reference.

Furthermore, MTL (Merged Transist
For high-speed RAM using
This is explained in the article by S. Km Wledman et al. in the 1983 collection of high-speed RAM articles.

This is hereby made a part of the description of the present application.

Furthermore, LCC (Leadl@ss Chip Ca
Regarding the gcL-RAM installed in
As explained in the article by bo) et al., with this,
It shall be part of the description of this application.

Furthermore, ECL using poly S1 embedded isolation carbon/
-RAM and overall circuit configuration in 1983
This is explained in the article by Ooami et al. in the same edition of the Nenshi Manuscripts, and is hereby incorporated as part of the description of this application.

Also, TTL- used in BICMOS gate array.
Regarding the CMOS level conversion circuit, please refer to Suzuki (5uzu
U.S. Pat. No. 4,689,503 to Nishio (Y,N
imhxo) et al. European Patent Publication 0125504-A
It is described in detail in Section 1, which is hereby incorporated into the description of this application.

Also, a specific example of I10 cell (in case of MOS-FEF configuration)
and panda electrode or s CCB (control
led-Collapse Solder-Bumps
) is described in British Patent No. 2104284 to Takahashi, which is incorporated herein by reference.

Additionally, for other uses of I10 cells and bonding pads in gate arrays, see
) et al., European Patent Publication No. 0023118A1, which is incorporated herein by reference.

Additionally, general ECL gate array construction methods and processes are described in U.S. Patent IE 4,255,672 to Oates et al.
For master slicing technology in general, and the I10 pad and I10 cell in particular, please refer to Balyo's
U.S. Pat. Regarding the routing technique,! Tsumura (Mats
Umura et al., US Pat. No. 4,412,237, which is incorporated herein by reference.

In addition, so-called assembly technology, especially wafer division such as dicing, die bonding, wire bonding,
TAB technology, clip chip technology, ceramic sealing,
Regarding packages such as glass sealing, plastic sealing, lead frames, lancefer molds using metal molds, epoxy sealing resins, chip carriers, etc., see "VLsI Technology" (S, M , Sze; 1983. McGra
w-Hllll Jne.

"VLSI Technology") 551~
It is explained on page 598, and these constitute the description of the embodiment of the present application.

〔Effect of the invention〕

According to the present invention, in a gate array with RAM, when the signal lines between the logic section of the gate array and the same I10 unit circuit are bypassed above the RAM, in order to suppress mutual interference, the signal lines of adjacent lines are crossed at right angles. By arranging the gate array IC and adjusting the wiring pitch of different layers running in parallel so that noise is canceled in differential sensing, it is possible to provide a gate array IC with a memory having high speed and high integration density.

[Brief explanation of the drawing]

FIG. 1A is a plan view showing a memory LSI with logic according to Part I of Embodiment 1 of the present invention, and FIG. 1B is a plan view showing a memory LSI with logic according to Part I of Embodiment 1 of the present invention. . @2A diagram is a memory L with logic according to Embodiment 2 of the present invention.
FIG. 2B is an enlarged schematic diagram of the main parts of a memory LSI according to a second embodiment of the present invention. 3A is a schematic partial sectional view showing the structure of a semiconductor device to which the present invention is applied; FIG. 3B is a plan view of a mother chip of the semiconductor device; and FIG. 3C is a semiconductor chip of the semiconductor device. FIG. 3D is an equivalent circuit diagram of a memory cell with a memory function built into the semiconductor chip. FIG. 3E is a sectional view of the main part of the mother chip. The mother chip and protrusion! FIG. 3P is a plan view of the mother chip showing the formation areas of the protruding electrodes and dummy protruding electrodes, and FIGS. 3Q to 3T are cross-sectional views of the main parts shown for each manufacturing process of the semiconductor device. Schematic cross-sectional views shown for each assembly process; Figure 3U is a layout diagram showing the configuration of a semiconductor chip of a semiconductor device by a different wafer process in an embodiment of the present invention; and Figure 3V is a configuration of the semiconductor chip. FIG. 3W is an equivalent circuit diagram showing an SRAM memory cell built into the semiconductor chip, and FIG. 3XF is a cross-sectional view of the semiconductor chip. FIG. 4A shows a SICOS which is a fourth embodiment of the present invention.
? 4B is a chip layout diagram of a semiconductor integrated circuit device having the bipolar transistor, and FIG. 4C is an enlarged view of the main parts of the semiconductor integrated circuit device shown in FIG. 4B. A plan view, FIG. 4D is an enlarged plan view of a main part of the semiconductor integrated circuit device shown in FIG. 4C, and FIGS. 4E and 4F are reproductions modeling wiring portions extending in the semiconductor integrated circuit device. 4G to 4V are sectional views of essential parts showing each manufacturing process of the semiconductor integrated circuit device. FIG. 5A is a plan view of a bipolar transistor and a MISFET of a memory cell constituting the peripheral circuit of the SRAM I of the fifth embodiment, and FIG. 5B is a plan view of I-I of FIG. 5A.
Figure #5C is a cross-sectional view taken along the TI-II line in Figure 5A; Figure 5D is a cross-sectional view taken along the line ■-■ in Figure 5A; Figures 5EA to 5PC are , a plan view or a sectional view for explaining the manufacturing process of the fifth embodiment I, and 5th QA to 1rSQC diagrams are sectional views of the SRAM in the embodiment A cross-sectional view of the constituent bipolar transistors, Figure 5QB is a cross-sectional view of the same part as Figure 5C of the memory cell, Quasi-SQC diagram is a cross-sectional view of the same part as Figure 5D of the memory cell, and ISN diagram is a cross-sectional view of the same part as Figure 5D of the memory cell. Etc. How many circuits of memory cells, 5th S
Figures A to 5VB show S in the fifth embodiment 111.
Cross-sectional view 1 for explaining the manufacturing process of RAM. Figures 5W to 5Y show the SRAM of Example 5 of 5'.
FIG. In the figure, 101... semiconductor chip, 102... input/output circuit section, 103... memory section, 104... logic section,
105...Signal wiring, SC...Signal wiring channel. * Figure 7A Figure IB Figure 2A Figure 3Q Figure 3R Figure 3S Figure 3δ53043δ83093'083b8, Figure 31 Figure 3U Figure in 325 clout Figure 4B MEMORY wu++,; v
wMxy Figure 4C + 1J Figure 4D Act Is
. 4E Figure 4 et al. 4F Figure &ILJl Wa01-

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having the following configuration: (a) a substantially rectangular or square plate-shaped integrated circuit chip having first and second principal surfaces facing each other; (b) a logic circuit block consisting of a large number of logic gates provided approximately in the center on the first main surface of the chip; (c) along a first edge on the first main surface; (d) mutually orthogonal I/O cells provided between the logic block on the first main surface and the first I/O cell group; a RAM-type memory mat having a large number of word lines and data line pairs and its peripheral circuit; (e) connecting each I/O cell in the first I/O cell group to the logic block; a plurality of signal lines; wherein the plurality of signal lines and the word line are arranged to be perpendicular to each other over at least the entire width of the memory mat that the signal crosses; It passes through the area in an almost straight line. 2. Each of the data line pair and the signal line is arranged in parallel over almost the entire length of the data line, and each signal line has equal coupling with each complementary data,
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged at an equal distance from the paired data lines. 3. The semiconductor integrated circuit device according to claim 2, wherein the data line comprises a first layer Al wiring. 4. The semiconductor integrated circuit device according to claim 3, wherein the word comprises a second layer Al wiring. 5. The semiconductor integrated circuit device according to claim 1, wherein the first I/O cell group is mainly composed of bipolar elements. 6. The semiconductor integrated circuit device according to claim 5, wherein the memory cells of the RAM type memory circuit are ECL type bipolar memory cells. 7. The semiconductor integrated circuit device according to claim 6, wherein the logic block mainly comprises an ECL type bipolar circuit. 8. The semiconductor integrated circuit device according to claim 1, wherein each of the I/O cells is connected to the outside by a solder bump electrode provided on the first main surface of the chip. 9. The semiconductor integrated circuit device according to claim 8, wherein the bump electrode is not formed on the memory mat. 10. Semiconductor integrated circuit device consisting of the following configuration: (a)
(b) a substantially rectangular or square plate-shaped integrated circuit chip having opposing first and second major surfaces; (c) a first I/O cell group provided along a first edge on the first main surface; (d) a logic circuit block consisting of logic gates; A RAM type memory mat and its peripheral circuitry having a large number of mutually orthogonal word lines and data line pairs provided between the logic block and the first I/O cell group on the main surface; (e) a plurality of signal lines connecting each I/O cell in the first I/O cell group and the logic block; wherein the plurality of signal lines and the word line or data are connected to each other; , are arranged so as to be perpendicular to each other over at least the entire width of the memory mat that the signal lines cross, and these signal lines extend almost linearly above the memory mat. 11. The semiconductor integrated circuit device according to claim 10, wherein the logic block mainly comprises a CMOS circuit. 12. The semiconductor integrated circuit device according to claim 11, wherein the I/O cell group is mainly composed of bipolar elements or a mixed circuit of bipolar elements and MOSFET elements. 13. The memory cell is a single channel MOSFET SRAM with a load made of high resistance poly-Si.
13. The semiconductor integrated circuit device according to claim 12, comprising a cell. 14. A master slice type semiconductor integrated circuit device having the following configuration: (a) a substantially rectangular or square plate-shaped integrated circuit chip having first and second principal surfaces facing each other; (b) an integrated circuit chip of the above chip; (c) a gate array logic circuit block consisting of a large number of logic gates provided approximately in the center of the first main surface; (c) along a first edge of the first main surface; (d) mutually orthogonal I/O cells provided between the logic block on the first main surface and the first I/O cell group; a RAM type memory mat having a large number of word lines and data pairs and its peripheral circuit; (e) a plurality of memory mats connecting each I/O cell in the first I/O cell group and the logic block; (f) a plurality of bonding pads provided near each of the I/O cells; (g) a plurality of leads whose inner lead portions extend near the periphery of the chip; (h) a bonding wire that connects each of the pads and the inner lead; (i) a sealing resin body that seals the chip, the wire, and the inner lead; here, the plurality of signals and the word line or data; The lines are arranged so as to be orthogonal over at least the entire width of the memory mat traversed by the signal line,
These signal lines extend substantially linearly above the memory mat. 15. The semiconductor integrated circuit device according to claim 14, wherein the line orthogonal to the signal line is a data line of a memory. 16. A master slice type gate array monolithic integrated circuit device having the following configuration: (1) a monolithic substrate for an integrated circuit in the form of a substantially rectangular or square plate having first and second principal surfaces facing each other; (b) disposed approximately at the center on the first main surface of the substrate and having a substantially rectangular shape, the short sides of which are opposite first and second end sides of the first main surface, respectively; (c) a pair of SRAM circuit blocks provided on both sides of each long side of the gate array block, the longitudinal direction of which is parallel to the gate array block; and; (d) along and close to the opposing third and fourth edges of the first principal surface;
first and second I/O cell groups each consisting of a large number of I/O cells; (e) space above the memory circuit between each cell of each I/O cell group and the gate array block; Al of memory circuit
(f) a large number of word lines and data lines that are orthogonal to each other provided in the memory mat of the memory circuit; , the word line and the data line, which are formed by the upper Al wiring, are arranged to be orthogonal to the signal line at least over the entire memory mat area.