JPH01227455A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figure 4) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems (1) First aspect of the present invention Example (Figure 1.2) (2)
Second Embodiment of the Present Invention (Figure 3) Effects of the Invention [Summary] To provide a semiconductor device that suppresses side gate effects with a small voltage, stabilizes transistor characteristics, and enables high integration. In a semiconductor device having an element bone M8N region between compound semiconductor elements, a conductive layer selectively formed on a plate and a conductive layer that does not reach the element isolation region i; The device is configured to include a conductive impurity doped region selectively formed and an interelement electrode selectively formed on the impurity doped region.

[Industrial application field]

The present invention relates to a semiconductor device, and in particular, for example, GaA
For example, MES F E using compound semiconductors such as s-based
T (a + etal semiconductor F
ET) and t(EMT (high electron
The present invention can be applied to ICs such as high-performance transistors, and particularly relates to semiconductor devices that have stable transistor characteristics and can be highly integrated.

Recently, it has been reported that in ICs such as MES FETs and HEMTs that use compound semiconductors, when a voltage is applied to the electrodes across the element isolation region, the applied voltage changes the transistor characteristics, such as increasing the threshold voltage. , a so-called side gate effect occurs, which is a major obstacle to higher integration. The side gate effect is G
This phenomenon tends to occur when an aAs-based compound semiconductor is used, and it also tends to become more noticeable when the distance between elements is small (during high integration). For this reason, there is a demand for a semiconductor device having a structure that can suppress the side gate effect, which tends to be a problem especially in the case of high integration, and stabilize transistor characteristics.

[Prior Art] As a known example of a conventional technology for suppressing side gate effects, for example, IEEE BLBCTRON DI! V
ICIELETTERS, VOL, IEDL-6,
k4. APRIL 1985. P169～
It is described in p. 171.

Hereinafter, this will be explained in detail with reference to the drawings.

FIG. 4 is a cross-sectional view showing the structure of an example of a conventional semiconductor device.

In this figure, 1 is a semi-insulating substrate made of GaAs, for example, 2 is an n-type semiconductor layer made of AffiGaAs, 3 is an n-type cap layer made of GaAs, 4 is a source electrode, 5 is a gate electrode, 6 is a drain electrode, and 7 is an inter-element electrode, which functions as a Schottky electrode.

8 is an element isolation region, 9 is an opening, IO is a recess groove, 1
5 is a two-dimensional electron gas layer.

In addition, as a semiconductor element, for example, HEMT (HE M
T: high electron mobHit
y transistor, which is called a high electron mobility transistor and is a field effect transistor that uses a two-dimensional electron gas layer 15 formed at the heterojunction interface as a channel layer) is formed, and is an n-type semiconductor made of AfGaAs. A two-dimensional electron gas layer 15 is formed at the heterojunction interface between the layer 2 and the semi-insulating substrate 1 made of GaAs. The active layer is composed of a semiconductor N2 and a camp layer 3.

Next, the manufacturing process will be briefly explained.

First, A/GaAs%G is deposited on the substrate 1 by epitaxial growth using, for example, MOCVD or MBE.
A semiconductor N2 and a cap layer 3 are sequentially formed by depositing aAs. Next, by etching, for example, a photoresist is used to selectively remove the camp layer 3, semiconductor layer 2, and regions of the substrate 1 other than the element region to form an opening 9. At this time, the semiconductor element is separated into the element isolation region 8.
is formed.

Next, for example, A is deposited on the cap layer 3 by, for example, a vapor deposition method.
U G e /A u are selectively deposited and alloyed to form a recess groove 10 in the source electrode 4, drain electrode 6, and cap layer 3, and the recess groove 10 is formed by, for example, a vapor deposition method.
Then, an inter-element electrode 7 is formed on the gate electrode 5 and the element isolation region 8. Although not shown here, the semiconductor device is completed by forming an interelement insulating film, wiring, etc. Note that a two-dimensional electron gas IJ15 is formed at the heterojunction interface between the semiconductor N2 and the substrate l.

In the above device, an inter-element electrode 7 functioning as a Schottky electrode is provided on an element isolation region 8 between semiconductor elements (transistors), and a negative voltage is applied to this inter-element electrode 7 to suppress the side gate effect. .

It is presumed that this is because the side gate effect is suppressed by adjusting the potential by applying a negative voltage.

[Problems to be Solved by the Invention] However, in such conventional semiconductor devices, when increasing integration, transistor characteristics such as threshold voltage change depending on the voltage applied to adjacent elements. In order to suppress the so-called side gate effect, it is necessary to apply a very large voltage of about -10 V (normally about ±1 to 2 cm is ideal) to the inter-element electrode 7 to suppress the side gate effect. The problem was that it was not possible.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that suppresses side gate effects with a small voltage, stabilizes transistor characteristics, and enables high integration.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention has a semiconductor device having an element isolation region between compound semiconductor elements, and includes a conductive layer selectively formed on a substrate, and a conductive layer that reaches the element isolation region up to the conductive layer. The device includes a conductive impurity doped region selectively formed on the impurity doped region, and an inter-element electrode selectively formed on the impurity doped region.

In the present invention, a conductive layer selectively formed on a substrate refers to a mode in which the conductive layer is formed directly on the substrate, and a mode in which the conductive layer is formed on the substrate via a semiconductor layer, for example, a buffer layer. This includes aspects.

[For production]

In the present invention, a conductive layer is selectively formed on a substrate, an implantation region is selectively formed in an element isolation region to reach the conductive layer, and an inter-element electrode is selectively formed on the implantation region. It is composed of:

Therefore, it is possible to configure a semiconductor device in which the side gate effect is a problem to be shielded by the conductive layer and the implanted region.
The side gate effect can be suppressed with a small voltage.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a sectional view showing the structure of an embodiment of the semiconductor device according to the present invention, and FIG. 2 is a schematic plan view of the semiconductor device according to the present invention shown in FIG.

In these figures, the same reference numerals as in FIG. 3 indicate the same or equivalent parts, 7a is an inter-element electrode made of, for example, A u G e /Au (corresponds to the inter-element electrode according to the present invention), and 9 a is an opening. , 11 are, for example, i-type buffer layers made of GaAs, and 12 is, for example, n.

13 is an i-type semiconductor layer made of GaAs, and 14 is an n-type implanted region (corresponds to the conductive impurity doped region according to the present invention). (here, it is formed by ion implantation, but it may also be formed by thermal diffusion).

Note that, for example, a HEMT is formed as the semiconductor element. The active layer includes a semiconductor layer 2 made of, for example, n-type AlGaA3 and a camp layer 3 made of, for example, n-type GaAs.
It consists of

Further, in the illustrated example, the semiconductor element in which the side gate effect becomes a problem is a semiconductor element formed inside the injection region 14, and normally, the more negative voltage is applied to the semiconductor element, the more the side gate effect becomes a problem.

Next, the manufacturing process will be explained.

First, a buffer layer 11. A conductive layer 12, a semiconductor layer 13, a semiconductor N2, and a cap layer 3 are sequentially formed. Next, for example, by etching the photoresist, the semiconductor elements are separated by grooves or the like in the cap layer 3, the semiconductor layer 2, and the semiconductor layer 13 other than the element areas, and element isolation regions 8 are formed. Next, a single ion of 3i, for example, is applied to the element isolation region 8 around the semiconductor element where the side gate effect is a problem and is activated by annealing to selectively form an implanted region 14 that reaches the thick conductor 112. Next, AuGe'/A u
After selectively depositing fc and alloying to form the source electrode 4, drain electrode 6, and inter-element electrode 7a, camp N3
A recess groove 10 is formed in C1.A gate electrode 5 is formed in the recess groove 10 by, for example, a vapor deposition method. Although not shown here, the semiconductor device is completed by forming an inter-element insulating film, wiring, etc. Furthermore, a two-dimensional electron gas is formed at the heterojunction interface between the semiconductor layer 2 and the semiconductor layer 13. layer 15
is formed.

That is, in the above embodiment, the semiconductor element where the side gate effect is a problem is shielded by the conductive layer 12 and the implanted region 14 (specifically, the inter-element electrode is grounded and the conductive layer 12 and the implanted region are shielded). 14), the side gate effect can be suppressed with a small voltage, the transistor characteristics become stable, and high integration becomes possible. The semiconductor element to be shielded is a semi-quadrilateral element where side gate effect is a problem, and it is sufficient to shield only this element (suppressing side gate effect).
This is advantageous in terms of integration.

In the above embodiment, a preferred embodiment in which the conductive layer 12 is formed on the buffer layer 11 formed on the substrate 1 has been described, but the present invention is not limited to this. It may also be a case where it is formed.

In the above embodiment, as shown in FIGS. 1 and 2, the inter-element electrode 7a is formed on a part of the injection region 14, but the present invention is not limited to this. It suffices if it is formed at least selectively on the injection region 14, preferably over the entire surface of the injection region 14.

Although the above embodiment describes the case where the conductivity type of the implantation region 14 and the thermoelectric layer 12 is n-type, the present invention is not limited to this, and the implantation region 14 and the conductive layer 1
The second conductivity type may be p-type.

In the above embodiment, the injection region 14 is formed to reach the conductive layer 12 in the element isolation region 8 around the semiconductor element where the side gate effect is a problem, but the present invention is not limited to this. The implanted region 14 may be formed as appropriate to the extent that the side gate effect can be suppressed.As shown in FIG.
A may be partially formed.

Although the above embodiment describes a preferable embodiment in which the semiconductor element is constituted by a HEMT, the present invention is not limited to this, and the present invention is not limited to this.
It is also useful to apply to a compound semiconductor element formed using an m-v group compound semiconductor layer such as BT.

〔effect〕

According to the present invention, side gate effects are suppressed with a small voltage, transistor characteristics are stabilized, and high integration is possible.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of one embodiment of the semiconductor device according to the present invention, FIG. 2 is a schematic plan view of one embodiment, and FIG. 3 is the structure of another embodiment of the semiconductor device according to the present invention. FIG. 4 is a cross-sectional view showing the structure of an example of a conventional semiconductor device. ■...Substrate, 2...Semiconductor layer, 3...Cap layer, 4...Source electrode, 5...Gate electrode, 6 ......Drain electrode, 7a...Inter-element electrode, 8...Element isolation region, 9a...Opening, 10...Recess groove , 11... B-7 γ layer, 12... Conductive layer, 13... Semiconductor layer, 14... Injection region, 15... ...Two-dimensional electron gas layer.

Claims (1)

[Claims] A semiconductor device having an element isolation region between compound semiconductor elements, comprising: a conductive layer selectively formed on a substrate; and a conductive layer selectively formed in the element isolation region so as to reach the conductive layer. 1. A semiconductor device comprising: a conductive impurity doped region; and an interelement electrode selectively formed on the impurity doped region.