JPH0120550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that improves the current amplification factor h _FE and 1/noise characteristics of a bipolar transistor.

Traditionally, bipolar transistors and bipolar
The standard electrode formation process for IC was performed as follows. Impurities such as boron or phosphorus are introduced into predetermined locations on the main surface of the silicon substrate or epitaxial island region by thermal diffusion or ion implantation to form emitter regions, base regions, and high concentration regions for leading out collector electrodes. After that, a portion of the oxide film on the surface of these diffusion regions is removed by etching to form an emitter contact hole, a base contact hole, and a collector contact hole. . Next, a metal such as aluminum (hereinafter referred to as Al) is deposited on the entire surface, a photolithography process (hereinafter referred to as PR process) is performed to form a wiring pattern, and then a heat treatment at 400 to 500°C (hereinafter referred to as aluminum By carrying out an alloying process (referred to as an alloying process), ohmic contact between Al and the silicon in the contact hole can be obtained. In this aluminum alloy process, a portion of the silicon in the contact hole diffuses into the Al electrode, and conversely, Al atoms diffuse into the silicon in the contact hole and then into the silicon vacancies. Therefore, when the area of the Al electrode in the contact hole is large, a large amount of Al atoms diffuse into the silicon in the contact hole and reach a deeper portion. This phenomenon is particularly problematic in the emitter region where the diffusion depth is shallow, and when the emitter-base junction is shallow, Al atoms reach the emitter-base junction, degrading the crystallinity of this junction. This increased the reverse leakage current of the emitter-base junction, leading to a decrease in _hFE and an increase in noise. Therefore, the deeper the emitter region is and the longer the distance between the contact hole and the surface of the emitter region, the more the junction breakdown due to aluminum diffusion will not occur, but the high frequency characteristics cannot be improved.

On the other hand, experiments have shown that in an electrode structure in which the periphery of the emitter contact hole is formed close to the surface of the emitter region, the absolute value and linearity of h _FE are improved, and 1/noise is also improved. It is known. This phenomenon occurs during the aluminum alloy process, when the hydroxyl groups (-OH) contained in the oxide film undergo an oxidation reaction with Al, hydrogen ions (H ⁺ ) are generated, and this generates electrons near the Si-SiO ₂ interface. captured,
This is interpreted to be a result of decreasing the surface state density.

In recent years, in bipolar ICs, higher frequencies,
Due to the strong demand for improving characteristics for energy saving and reducing the area of elements associated with LSI, the depth of the bonding part is gradually becoming shallower, and the size of the contact hole is also increasing from 10μ x 10μ to 4μ x 4μ. The decline is underway. For this reason, there is an increased risk that aluminum atoms will diffuse from the above-mentioned aluminum electrode into the vicinity of the emitter-base junction and deteriorate the junction. However, on the other hand, there are also strict demands for improvements in _hFE characteristics and 1/noise. For this reason, conventional bipolar transistors have given up on satisfying the above contradictory requirements at the same time.
Instead of widening the opening for the emitter contact to the vicinity of the emitter-base junction to improve _hFE , we adopted a method that deepens the emitter-base junction and prevents aluminum atoms from melting and diffusing to the emitter-base junction. was. With this method, it is difficult to satisfy the above-mentioned requirements for improving high frequency characteristics, reducing element size, and saving energy.

The present invention improves the above-mentioned drawbacks, and even if the emitter-base junction is shallow and the transistor has excellent high frequency characteristics, H ⁺
By overlapping the oxide film on the emitter-base junction with a material that generates ions,
A semiconductor device with improved h _FE and 1/noise characteristics is obtained by reducing the surface state density.

According to the present invention, since the electrode area in contact with the emitter region is small, Al will not diffuse to the vicinity of the emitter-base junction and deteriorate the crystallinity of the junction, and the emitter-base junction will not be oxidized by the electrode metal. Since it is coated with a film, it is possible to realize a transistor with excellent h _FE and 1/noise characteristics. In addition, the depth of the emitter-base junction can be made sufficiently shallow, resulting in excellent frequency characteristics.
It is possible to realize a transistor that supports energy saving.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

_Figures 1 and 2 show vertical PNP transistors (hereinafter referred to as V-
Planar structure near the emitter (written as PNP) (first
Fig. 2) and a structural cross-sectional view of V-PNP (Fig. 2). This V-PNP is particularly effectively used in the case of differential connections where a small V _BE offset is required. In FIGS. 1 and 2, 1.E and 2.E are emitter diffusion regions, and 1E.C and 2E.C are emitter contact openings made in the surface oxide film. 1・E・B and 2・E・B indicate emitter-base joints. Further, 1.AL and 2.AL indicate Al lead electrodes that contact the emitter regions 1.E and 2.E through the emitter contact openings. In addition, the V-PNP shown in FIG.
, and N-type epitaxial layers 2 and 4 are formed on the surface.
The type regions 2 and 5 are formed by diffusion, and the epitaxial layers 2 and 4 surrounded by the P type regions 2 and 5 are formed with a P type emitter region 2 and E and an N ⁺ region 2 and 6 for taking out the base electrode.
was formed.

As can be seen from Figs. 1 and 2, in V-PNP with severe V _BE offset, Al extraction electrodes 1 and 2 from emitter regions 1 and 2 and E are
AL and 2・AL are connected to the emitter area 1・E・C, 2・E・C on the entire surface of the emitter area contact openings 1・E・C, 2・E・C.
A widely used method is to contact the emitters E, 2 and E, and to overlap them to the outside of the emitter-base junction. On the other hand, the emitter regions 1, 2 and 2 of V-PNP tend to become shallower due to the demand for smaller element areas and higher frequencies. This is due to the following reasons.

Analyzing the element area of a transistor in a bipolar IC, the area between the base and the insulating layer, between the collector and
The amount of space between insulation layers is large, and this is what makes MOSIC
This is a major reason why the chip size of bipolar ICs cannot be made smaller than that of conventional ICs. Therefore, in order to reduce the size of transistors, it is important to reduce the epitaxial thickness and reduce the lateral extent of the insulating region.

For this reason, a method has been adopted in which the emitter of the V-PNP is shallowly diffused separately from the base of the NPN transistor to reduce the epitaxial thickness. V- with such a shallow emitter and base junction
When Al electrodes as shown in Figures 1 and 2 are formed on PNP, Al diffuses to the emitter-base junction and deteriorates the emitter-base junction.・
Accidents of so-called alloy spikes that spread through E and into the base region often occur.

Next, FIG. 3 shows a plan view of the vicinity of the emitter showing the first embodiment of the present invention, and FIG. 4 shows a structural sectional view when applied to a V-PNP.

First, referring to FIG. 4, V-PNP is manufactured by forming N-type buried layers 4.3 and P-type buried layers 4.2, 4.2' on a P-type silicon substrate 4.1. A type epitaxial layer 4.4 is grown. During this vapor phase growth, each buried layer rises up onto the epitaxial layers 4, 4, as shown in FIG. Next, a P-type impurity is diffused at a high concentration to form a P-type isolation region 4.
5 to reach the P-type buried layer 4.2 and separate the epitaxial layer 4.4 into a plurality of island regions,
The P-type wall regions 4, 5' reach the P-type buried layer 4, 2', and a part of the epitaxial layer 4, 4 forms the P-type wall region 4, 5' and the P-type buried layer 4, 2'. Surround it with . Next, a P-type emitter region 4-E and an N ⁺ -type base are formed in the epitaxial layer 4, 4 surrounded by the P-type wall region 4, 5' and the P-type buried layer 4, 2'.
Contact regions 4 and 6 are formed.

Next, contact openings are formed in the surface oxide film to lead out the base, emitter, and erector electrodes, and electrode wiring is formed by selective etching using photoetching after Al is deposited on the entire surface. is shown in FIG.

In these figures 3 and 4, 3E and 4E are V-
This is the emitter region of PNP, and its depth is approximately 1μ. 3.E.C and 4.E.C indicate openings for emitter contacts, and the opening area is 4μ×4μ. Opening hole 3・E・for emitter contact
The first Al electrodes 3AL(a), 4AL(a) are arranged from inside C, 4・E・C to the oxide film 2.5 μ outside of it, and also in the vicinity including the emitter-base junction. Also, Al electrodes 3AL(b) and 4AL(b) are formed on the oxide film, and these are connected to each other by an Al wiring A having a width of 5 to 7.5 μm.

In this way, the area of the Al electrodes 3AL(a), 4AL(a) in contact with the emitter regions 3・E, 4・E is at least 1/noise because the areas of the Al electrodes 3AL(b), 4AL(b) are Moreover, since the amount of silicon that diffuses into the Al electrodes 3AL(a), 4AL(a) through the contact openings 3, E, and C is small in the Al electrodes 3AL(a), 4AL(a), Compared to the conventional Al electrode placement method, this is significantly less. Also, since the width of Al wiring A is narrow, Al
The silicon diffused into electrodes 3AL(a) and 4AL(a) hardly diffuses into the large amount of Al electrodes 3AL(b) and 4AL(b) placed in the vicinity including on the emitter-base junction. . For this reason, emitter region 3・E,
Since the amount of Al that diffuses into the silicon crystal in 4.E is small, Al will not diffuse to the emitter-base junction and deteriorate the crystallinity of the junction.
Therefore, a transistor with excellent high frequency characteristics, large h _FE and low noise can be obtained.

FIG. 5 shows an electrode part as another embodiment of the present invention, and shows part A, that is, the emitter region 5.
Al extraction electrode 5AL(a) in contact with E and placed on the oxide film on the emitter-base junction
The Al wiring that connects the Al electrode 5AL(b) is shown in Figure 3.
Since the length is longer than that of the embodiment shown in FIG. 4, the effect of preventing the silicon diffused into the Al electrode 5AL(a) from diffusing into the outer Al is even more remarkable.

The embodiments described above can be easily realized on a mask pattern without changing the conventional process. In other words, conventionally, the Al extraction electrode in the emitter contact hole has the role of taking out the Al wiring from the contact hole and reducing the surface level through an oxidation reaction with the oxide film in the aluminum alloy process. However, in the present invention, since these are separated, the element area can be reduced, and the 1/noise characteristics and _hFE characteristics and high frequency characteristics can be improved.

FIG. 6 is a plan view showing still another embodiment of the present invention, in which an Al electrode 6AL(a) in contact with an emitter region 6E and an Al electrode 6AL(a) formed on an oxide film in the vicinity including on the emitter-base junction. The wiring 6・poly that connects the electrode 6AL(b) is a low resistance semiconductor material formed by diffusing phosphorus, boron, Al, etc. into polysilicon, and at the boundary between the Al electrode 6AL(a) and the wiring 6・poly, Since the concentration of silicon is higher in the wiring 6/poly part, the silicon diffused from the contact openings 6/E/C to the Al electrode 6AL(a) is placed on the outside of the Al electrode 6/AL(b). It will not spread to. Therefore, the above effects are even more subtle. At this time, there is no problem even if the length of the wiring 6/poly is short.

As described above, the bipolar transistor according to the present invention is extremely effective when the emitter-base junction is shallow, and therefore has excellent high frequency characteristics and is also highly effective at low device sizes. or,
By coating the oxide film near the emitter-base junction with a material that generates H ⁺ ions during the heat treatment process, such as Al, the surface state density is reduced, resulting in excellent _hFE characteristics and 1/noise characteristics. When used in connection transistors, excellent semiconductor devices with sufficiently small _VBE offsets can be realized.

Although the present invention has mainly been described with respect to Al extraction of the V-PNP emitter and contact of a bipolar IC, it goes without saying that it is equally applicable to devices having shallow junctions and requiring a reduction in surface state density.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a V-PNP emitter electrode portion of a conventional bipolar IC. 1E...Emitter (P ⁺ layer), 1E・C...Emitter, contact, 1E・B...Emitter, base junction, 1A/L...Al of emitter contact
Extraction electrode. FIG. 2 is a structural sectional view showing a conventional V-PNP. 2.1...P-type substrate, 2.2...Embedded P ⁺ layer,
2.3...Buried N ⁺ layer, 2.4...N type epitaxial region, 2.5...Insulating P ⁺ region, 2.6
...Base N ⁺ layer, 2・E... Emitsuta (P ⁺ layer),
2・E・C……Emitsuta Contact, 2・E・C
B... Emitter/base junction, 2/A/L... Emitter, contact Al lead electrode. FIG. 3 shows a V-
FIG. 3 is a plan view showing an emitter electrode portion of a PNP. 3・E……Emitsuta (P ⁺ layer), 3・E・C……
Emitter, contact, 3・E・B……emitter, base junction, 3・AL(a)……emitter, Al electrode near the contact, 3・AL(b)……emitter,
Al electrode placed on the oxide film on the base junction, A...A narrow Al electrode connecting 3AL(a) and 3AL(b). FIG. 4 shows a V- according to the first embodiment of the present invention.
FIG. 2 is a structural cross-sectional view showing a PNP. 4.1...P-type substrate, 4.2...Embedded P ⁺ layer,
4.3...Buried N ⁺ layer, 4.4...N type epitaxial region, 4.5...Insulating P ⁺ region, 4.6
...Base N ⁺ layer, 4・E... Emitsuta (P ⁺ layer),
4・E・C……Emitsuta, contact, 4・E・
B... Emitter, base junction, 4・AL(a)... Emitter, Al electrode near the contact, 4・AL(b)...
...Al electrode placed on the oxide film on the emitter-base junction. FIG. 5 shows a V-PNP according to another embodiment of the present invention.
FIG. 3 is a plan view showing an emitter electrode section. 5・E……Emitsuta (P ⁺ layer), 5・E・C……
Emitter, contact, 5・E・B……Emiter, base junction, 5・AL(a)……Al electrode near the emitter/contact, 5・AL(b)……Emiter,
Al electrode placed on the oxide film on the base junction, A...A narrow Al electrode connecting 3AL(a) and 3AL(b). FIG. 6 shows a V-
FIG. 3 is a plan view showing an electrode section of a PNP. 6・E……Emitsuta (P ⁺ layer), 6・E・C……
Emitter, contact, 6・E・B……emitter, base junction, 6・AL(a)……emitter, Al electrode near contact, 6・AL(b)……emitter,
Al electrode placed on the oxide film on the base junction, 6.poly...polysilicon with boron, phosphorus,
A low resistance region formed by diffusing Al, etc.

Claims (1)

[Claims] 1. An N-type semiconductor layer formed on a P-type semiconductor substrate is separated into a plurality of island regions by a P-type insulating region, and is arranged vertically in at least one island region. A semiconductor comprising a PNP transistor having a P-type collector region, an N-type base region, and a P-type emitter region, and in which the collector region is insulated and separated from the semiconductor substrate by an N-type buried region. The device comprises a first electrode material covering at least an emitter-base junction of the PNP transistor with an insulating film interposed therebetween, and a second electrode material directly contacting the emitter region, the first electrode material being in direct contact with the emitter region. The material and the second electrode material are electrically connected to each other, and the first and second electrode materials on the insulating film are at least partially separated from each other. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the first and second electrode materials are interconnected by a semiconductor material containing impurities.