JPH01117350A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01117350A JPH01117350A JP27609287A JP27609287A JPH01117350A JP H01117350 A JPH01117350 A JP H01117350A JP 27609287 A JP27609287 A JP 27609287A JP 27609287 A JP27609287 A JP 27609287A JP H01117350 A JPH01117350 A JP H01117350A
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- lead frame
- resin
- island
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はリードフレームの一部であるアイランドに接着
された半導体素子にリードを接続したのち樹脂で封止し
た樹脂封止型半導体装置に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device in which leads are connected to a semiconductor element bonded to an island that is part of a lead frame and then sealed with resin. It is.
(従来の技術〕
第3図および第4図は従来におけるこの種樹脂封止型半
導体装置を示し、第3図はその縦断面図、第4図(a)
はリードフレームの平面図、第4図(ロ)は第4図(a
)のAA断面図である。図において、半導体装置lのリ
ードフレーム2は、薄板材により長方形枠状に形成され
たリードフレーム枠3と、その中心部に位置する長方形
のアイランド4と、これらの部材3,4を連結する吊り
リード5とで一体形成されており、リードフレーム枠3
とアイラ、ンド4とは、同じ厚みに形成されている。ア
イランド4上には、半導体素子6が接着剤7で固着され
ており、この半導体素子6の周囲には、複数個のインナ
リード8が、互いの間およびリードフレーム枠3との間
をこれと一体形成のタイバー9で連結されて配設されて
いる。各インナリード8の先端部は、2字状に折曲げら
れて半導体素子6に近接しており、この先端部と半導体
素子6とは、ワイヤ10によって電気的に接続されてい
る。また、各インナリード8には、リードフレーム枠3
に一体形成により支持されたアウタリード11がそれぞ
れ一体形成されており、各アウタリード11は、外部装
置との間を図示しないリード線により電気的に接続され
ている。(Prior Art) FIGS. 3 and 4 show a conventional resin-sealed semiconductor device of this type, FIG. 3 being a vertical cross-sectional view thereof, and FIG. 4(a)
4(b) is a plan view of the lead frame, and FIG. 4(b) is a plan view of the lead frame.
) is an AA cross-sectional view. In the figure, a lead frame 2 of a semiconductor device 1 includes a lead frame frame 3 formed in a rectangular frame shape from thin plate material, a rectangular island 4 located at the center of the lead frame frame 3, and a suspension connecting these members 3 and 4. It is integrally formed with the lead 5, and the lead frame frame 3
, air conditioner 4, and air conditioner 4 are formed to have the same thickness. A semiconductor element 6 is fixed on the island 4 with an adhesive 7, and around the semiconductor element 6, a plurality of inner leads 8 are arranged between each other and the lead frame frame 3. They are connected by an integrally formed tie bar 9. The tip of each inner lead 8 is bent into a double-shape and is close to the semiconductor element 6 , and the tip and the semiconductor element 6 are electrically connected by a wire 10 . Each inner lead 8 also has a lead frame frame 3.
Outer leads 11 are integrally formed and supported by the outer leads 11, and each outer lead 11 is electrically connected to an external device by a lead wire (not shown).
このようにして組立てられた各部材の中心部であるイン
ナリード8の先端部を含む半導体素子6等の部材は、通
常、トランスファー成形等により半導体封止樹脂12で
封止されて外部環境から保護されている。The semiconductor element 6 and other members including the tip of the inner lead 8, which is the center of each member assembled in this way, are usually sealed with a semiconductor sealing resin 12 by transfer molding or the like to protect them from the external environment. has been done.
このような樹脂封止型半導体装置1のリードフレーム2
は、最終製品におけるリード曲げ強度の要求から所定値
以上の厚みが必要であり、また樹脂封止後のリードフレ
ーム2全体の強度を確保するためにリードフレーム枠3
にも所定値以上の厚みが必要である。そこで従来、リー
ドフレーム2は、全体が均一に所定値以上の厚み、例え
ば0.15m以上の厚みを有している。Lead frame 2 of such a resin-sealed semiconductor device 1
The thickness of the lead frame 3 is required to be at least a predetermined value due to the requirement for lead bending strength in the final product.
It is also necessary for the thickness to be at least a predetermined value. Conventionally, the lead frame 2 has a uniform thickness of at least a predetermined value, for example, a thickness of 0.15 m or more.
一方、半導体素子6が半導体装置1全体の投影面積の1
/3以上を占有するような大チップサイズの場合には、
半導体装置1を構成する部材の線膨張係数の不整合によ
る半導体装置lの熱歪み変形が問題になるので、これを
無くすためには、半導体素子6を最適位置に設ける必要
がある。On the other hand, the semiconductor element 6 is 1 of the projected area of the entire semiconductor device 1.
In the case of a large chip size that occupies /3 or more,
Since thermal strain deformation of the semiconductor device 1 due to mismatching of linear expansion coefficients of the members constituting the semiconductor device 1 becomes a problem, in order to eliminate this problem, it is necessary to provide the semiconductor element 6 at an optimal position.
さらに、半導体封止樹脂7の成形時における半導体素子
6上方の封止樹脂厚と、アイランド4下下方の封止樹脂
厚とのバランスは、封止樹脂12の流動挙動に影響を及
ぼすものであって、このバランスが崩れると、封止樹脂
12の流動が不均一になって製品の品質が低下するので
、これを適正に設定する必要がある。なお、半導体素子
6から上方へ突出するワイヤ10の突出高さは通常、0
.2〜0.3■必要である。Furthermore, the balance between the thickness of the encapsulation resin above the semiconductor element 6 and the thickness of the encapsulation resin below the island 4 during molding of the semiconductor encapsulation resin 7 affects the flow behavior of the encapsulation resin 12. If this balance is disrupted, the flow of the sealing resin 12 will become uneven and the quality of the product will deteriorate, so it is necessary to set this appropriately. Note that the protrusion height of the wire 10 that protrudes upward from the semiconductor element 6 is usually 0.
.. 2 to 0.3 ■ is required.
(発明が解決しようとする問題点〕
しかしながら、このような従来の樹脂封止型半導体装置
においては、例えば半導体装置l全体の厚みが1.2閣
であって、そのうちの半導体素子6の厚みが0.4 w
a、線膨張係数が半導体素子6に近いリードフレーム2
(例えば42%N1−Fe)の厚みが0.2目、接着剤
7の厚みが0.05園で構成されている場合、熱歪みに
よる変形を最小にしかつ金型内における封止樹脂12の
流動を均一にしようとすると、前記上下の封止樹脂厚が
それぞれ0.25−になる、これに対してワイヤ10の
突出量が前述したように0.2〜0.3 mであるから
、はとんどの場合、ワイヤ10が封止樹脂12の面から
露呈してしまうという問題がある。また、これを回避し
ようとして上側の封止樹脂厚みを0.31にすると、下
側の封止樹脂厚みが0.2閣になり、熱歪みが大きくな
ったり、成形時の樹脂の流動が不均一になったりして製
品の品質が低下するという問題があった。(Problems to be Solved by the Invention) However, in such a conventional resin-encapsulated semiconductor device, the thickness of the entire semiconductor device l is 1.2 mm, of which the thickness of the semiconductor element 6 is 0.4w
a, lead frame 2 whose coefficient of linear expansion is close to that of the semiconductor element 6;
(for example, 42% N1-Fe) is 0.2 mm thick, and the adhesive 7 is 0.05 mm thick to minimize deformation due to thermal distortion and maintain the sealing resin 12 in the mold. If an attempt is made to make the flow uniform, the thickness of the upper and lower sealing resins will each be 0.25-0.25 m, whereas the protrusion amount of the wire 10 is 0.2 to 0.3 m as described above. In most cases, there is a problem that the wire 10 is exposed from the surface of the sealing resin 12. In addition, if the thickness of the upper sealing resin is set to 0.31 in an attempt to avoid this, the thickness of the lower sealing resin becomes 0.2 mm, resulting in increased thermal distortion and poor flow of the resin during molding. There was a problem that the quality of the product deteriorated due to uniformity.
本発明は以上のような点に鑑みなされたもので、全体の
厚みが1.2 wm以下の超薄型でも、熱歪みが少なく
樹脂の成形性の良好な樹脂封止型半導体装置を提供する
ことを目的としている。The present invention has been made in view of the above points, and provides a resin-sealed semiconductor device that is ultra-thin with a total thickness of 1.2 wm or less, has little thermal distortion, and has good resin moldability. The purpose is to
[問題点を解決するための手段]
このような目的を達成するために本発明においては、装
置全体の厚みが1.2mm以下の樹脂封止型半導体装置
において、半導体素子を装着するリードフレームのアイ
ランドの厚みをその他のリードフレーム部分に比べて半
分以下にした。[Means for Solving the Problems] In order to achieve such an object, the present invention provides a resin-sealed semiconductor device in which the overall thickness of the device is 1.2 mm or less, and a lead frame on which a semiconductor element is mounted. The thickness of the island is less than half that of the other lead frame parts.
アイランドの厚みを減少することにより、その減少分だ
け封止樹脂厚が増加するので、半導体素子上方の樹脂厚
とアイランド下方の樹脂厚とのバランスの選択範囲が増
大する。By reducing the thickness of the island, the thickness of the sealing resin increases by the amount of the decrease, so the range of selection for the balance between the resin thickness above the semiconductor element and the resin thickness below the island increases.
第1図および第2図は本発明に係るる樹脂封止型半導体
装置の実施例を示し、第1図はその縦断面図、第2図(
a)はリードフレームの平面図、第2図ら)は第2図(
a)のBB断面図である0図において第3図および第4
図に示す従来の樹脂封止型半導体装置と同符号を付した
部材はこれと同構成であるからその詳しい説明を省略し
以下これを簡単に説明する。半導体装置21のリードフ
レーム22は、リードフレーム枠3と、その中心部のア
イランド24と、これらを連結する吊りリード5とで一
体形成されていて、アイランド24上には、半導体素子
6が接着剤7で固着されており、この半導体素子6には
、外部装置に電気接続されたアウタリード11と一体の
インナリード8がワイヤlOで電気接続されている。こ
のようにして組立てられた各部材の中心部であるインナ
リード8の先端部を含む半導体素子6等の部材は、通常
、トランスファー成形等ににより半導体封止樹脂32で
封止されて外部環境から保護される。1 and 2 show an embodiment of a resin-sealed semiconductor device according to the present invention, FIG. 1 is a longitudinal sectional view thereof, and FIG.
a) is a plan view of the lead frame, and Fig. 2) is a plan view of the lead frame.
Figures 3 and 4 in Figure 0, which is the BB sectional view of a).
Components denoted by the same reference numerals as those of the conventional resin-sealed semiconductor device shown in the drawings have the same configurations, so a detailed description thereof will be omitted and will be briefly described below. The lead frame 22 of the semiconductor device 21 is integrally formed with a lead frame frame 3, an island 24 at the center thereof, and a hanging lead 5 connecting these parts, and a semiconductor element 6 is mounted on the island 24 with an adhesive. The semiconductor element 6 is electrically connected to an inner lead 8 integrated with an outer lead 11 electrically connected to an external device by a wire IO. The components such as the semiconductor element 6, including the tip of the inner lead 8, which is the central part of each component assembled in this way, are usually sealed with a semiconductor sealing resin 32 by transfer molding or the like to protect them from the external environment. protected.
そして、本装置においてはアイランド24の厚みがリー
ドフレーム2の他の部分の厚みの半分以下に形成されて
いる。例えば半導体装置21全体の厚みが1.2111
である本実施例においては、半導体素子6の厚みが0.
4鰭に形成されており、またアイランド24の厚みは、
線膨張係数が半導体素子6に近いリードフレーム2(例
えば42%N1−Fe)の厚み0.2mの1/400.
05 mに形成されている。接着剤7の厚みは0.05
閣である。この結果封止樹脂32は、半導体素子6上方
の厚みと、アイランド24下方の厚みとがともに0.3
5−となる。これは前記ワイヤ10の突出量0.2〜0
.3閣よりも大きいので、ワイヤ10が封止樹脂32の
表面から露呈することがなく、まな上下の厚みバランス
がとれるので、熱歪みによる変形が発生したり成形時に
問題となったりすることがない。In this device, the thickness of the island 24 is less than half the thickness of other parts of the lead frame 2. For example, the thickness of the entire semiconductor device 21 is 1.2111
In this embodiment, the thickness of the semiconductor element 6 is 0.
It is formed into four fins, and the thickness of the island 24 is
1/400 of the thickness of 0.2 m of the lead frame 2 (for example, 42% N1-Fe) whose coefficient of linear expansion is close to that of the semiconductor element 6.
05 m. The thickness of adhesive 7 is 0.05
It is a temple. As a result, the thickness of the sealing resin 32 above the semiconductor element 6 and the thickness below the island 24 are both 0.3.
It becomes 5-. This is the protrusion amount of the wire 10 from 0.2 to 0.
.. Since the wire 10 is larger than the three cabinets, the wire 10 is not exposed from the surface of the sealing resin 32, and the upper and lower thicknesses are balanced, so there is no deformation due to thermal distortion or problems during molding. .
以上の説明により明らかなように本発明によれば装置全
体の厚みが1.21以下の樹脂封止形半導体装置におい
て、半導体素子を装着するリードフレームのアイランド
の厚みをその他のリードフレーム部分に比べて半分以下
にしたことにより、この減少分だけ封止樹脂の厚みが増
し、電気接続用のワイヤを封止樹脂の表面から露呈させ
ることなく封止樹脂の厚みを、半導体素子の上方とアイ
ランドの下方とで同寸法にすることが可能となるので、
熱歪みによる変形が発生したり、封止樹脂成形時の流動
が不均一になったりすることがなく、外観が美麗で信顛
性の高い樹脂封止型半導体装置が得られる。As is clear from the above description, according to the present invention, in a resin-sealed semiconductor device in which the overall thickness of the device is 1.21 mm or less, the thickness of the island of the lead frame on which the semiconductor element is mounted is compared with that of the other lead frame parts. By reducing the thickness to less than half, the thickness of the encapsulating resin increases by this reduction, and the thickness of the encapsulating resin can be increased by reducing the thickness of the encapsulating resin above the semiconductor element and between the islands without exposing the electrical connection wires from the surface of the encapsulating resin. Since it is possible to have the same dimensions as the lower part,
A resin-sealed semiconductor device with a beautiful appearance and high reliability can be obtained without deformation due to thermal distortion or uneven flow during molding of the sealing resin.
第1図および第2図は本発明に係る樹脂封止型半導体装
置の実施例を示し、第1図はその縦断面図、第2図(a
)はリードフレームの平面図、第2図(b)は第2図(
a)のBB断面図、第3図および第4図は従来の樹脂封
止型半導体装置を示し、第3図はその縦断面図、第4図
(a)はリードフレームの平面図、第4図(ロ)は第4
図(a)のAA断面図である。
6・・・・半導体素子、21・・・・樹脂封止型半導体
装置、22・・・・リードフレーム、24・・・・アイ
ランド、32・・・・半導体封止樹脂。1 and 2 show an embodiment of a resin-sealed semiconductor device according to the present invention, FIG. 1 is a longitudinal sectional view thereof, and FIG. 2 (a
) is a plan view of the lead frame, and FIG. 2(b) is a plan view of the lead frame.
BB sectional view in a), FIGS. 3 and 4 show a conventional resin-sealed semiconductor device, FIG. 3 is a vertical sectional view thereof, FIG. 4(a) is a plan view of a lead frame, Figure (b) is the fourth
It is AA sectional view of figure (a). 6... Semiconductor element, 21... Resin-sealed semiconductor device, 22... Lead frame, 24... Island, 32... Semiconductor-sealed resin.
Claims (1)
装置において、半導体素子を装着するリードフレームの
アイランドの厚みをその他のリードフレーム部分に比べ
て半分以下にしたことを特徴とする樹脂封止型半導体装
置。A resin-sealed semiconductor device in which the thickness of the entire device is 1.2 mm or less, characterized in that the thickness of the island of the lead frame on which the semiconductor element is mounted is less than half the thickness of the other lead frame parts. type semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27609287A JPH01117350A (en) | 1987-10-30 | 1987-10-30 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27609287A JPH01117350A (en) | 1987-10-30 | 1987-10-30 | Resin-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01117350A true JPH01117350A (en) | 1989-05-10 |
Family
ID=17564691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27609287A Pending JPH01117350A (en) | 1987-10-30 | 1987-10-30 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01117350A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0534678A2 (en) * | 1991-09-25 | 1993-03-31 | AT&T Corp. | Method of making electronic component packages |
US7012325B2 (en) | 2001-03-05 | 2006-03-14 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device and method for manufacturing the same |
-
1987
- 1987-10-30 JP JP27609287A patent/JPH01117350A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0534678A2 (en) * | 1991-09-25 | 1993-03-31 | AT&T Corp. | Method of making electronic component packages |
EP0534678A3 (en) * | 1991-09-25 | 1994-03-16 | American Telephone & Telegraph | |
US7012325B2 (en) | 2001-03-05 | 2006-03-14 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device and method for manufacturing the same |
US7253026B2 (en) | 2001-03-05 | 2007-08-07 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device and method for manufacturing the same |
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