JP2011071579A - PCI Express (R) COMMUNICATION SYSTEM - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PCI Express (R) communication system that improves communication method of self diagnostic information to be transmitted from an end point and reducing fault recovery time. <P>SOLUTION: The PCI Express (R) communication system includes: a route complex 1 provided with a time synchronizing signal generation part 1a for generating a time synchronizing signal for setting in advance the same transmission cycle simultaneously with respect to the plurality of end points 3a-3c; a plurality of end points provided with synchronous transmission setting parts 3a1-3c1 for receiving the time synchronizing signals and exclusively setting in advance the transmission timing and data band width of data for the data to be transmitted from the end points to the route complex; and a switch 2 for relaying the transmission of the data between the route complex and the end points. The presence of the error of the data is transmitted to the route complex in the set data band width. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a PCI Express communication system, and more particularly to a PCI Express communication system in which a communication method of self-diagnosis information transmitted from an endpoint is improved.

  The PCI Express (registered trademark) bus is a high-speed serial interface with a point-to-point connection recently developed to transfer data of computer systems and other electronic devices. The area is small and further miniaturization is possible, and its use is being studied in many fields.

  Details of this standard have been standardized as PCI Express Base Specification by PCI-SIG (Peripheral Component Interconnect-Special Interest Group), which is the main body of the PCI standard, and a manual of this standard has been published (for example, (Refer nonpatent literature 1.).

  First, an outline of the PCI Express communication system will be described with reference to FIGS. The configuration of the PCI Express communication system includes, for example, devices of a root complex 1, a switch 2, and endpoints 3 (3a, 3b, 3c, 3d) as shown in FIG.

  Further, the root complex 1 and the switch 2 each have a plurality of ports, and the PCI Express buses 7a to 7e that connect these and the end point 3 have a three-layer structure as shown in FIG.

  Each layer consists of a transaction layer 101 that guarantees reliable communication between the traditional PCI-compatible service and end-to-end data to the upper software layer consisting of the top-level driver and application software, between adjacent components. A data link layer 102 that guarantees reliable data communication and a physical layer 103 that transmits and receives communication packets on a physical medium, and transmits and receives data in the form of packets.

  Further, the root complex 1 is located at the top of the tree structure of the PCI Express communication system, and is connected to the CPU 5 by the system bus and the memory 6 by the memory bus.

  In this configuration, the switch 2 serves as a TLP relay device in the communication between the root complex 1 and the endpoint 3a, and the switch 2 and the route complex 1 serve as a relay device in the communication between the endpoint 3a and the endpoint 3d.

  The transmission path connection between devices of the PCI Express communication system configured in this way is a point-to-point connection, which is a dual simplex system that uses two unidirectional differential amplifiers and a link speed. Has a bandwidth of 2.5 Gbps and has a bandwidth of 5 Gbps in both directions.

  Furthermore, by increasing the number of bidirectional transmission paths (called lanes) from two to three, the bandwidth of the bus can be configured to be scalable, and data can be transmitted and received by transmitting and receiving packets on this transmission path. Perform transmission.

  As shown in FIG. 8, the packets of each layer are generated in the transaction layer and the data link layer, and are called a transaction layer packet (TLP, Transaction Link Packet) and a data link layer packet (DLLP, Data Link Layer Packet), respectively.

  Also in the physical layer, a physical layer packet (PLP) is generated for link control.

  In addition, packets of each layer are exchanged with the same layer of the other party connected by the link, and as shown in FIG. 9, information is added before and after in the lower protocol layer and finally transmitted to the transmission path. The The received packet is passed to the upper protocol layer with the previous and subsequent information deleted in each protocol layer.

  Specifically, the TLP for end-to-end communication consists of a TLP header, data payload, and optional TLP digest (ECRC, called end-to-end CRC) at the transaction layer, and the data link layer. In addition, the sequence number and LCRC are added at the time of transmission and deleted after inspection at the time of reception.

  DLLP is a short packet for exchanging information on both links, such as TLP delivery response (acknowledgment ACK and negative acknowledgment NAK).

  Further, control characters (STP and END) for detecting start and end on the receiving side of the physical layer are added to both ends of the packet in each TLP. Also, control characters (SDP and END) for detecting the start and end of DLLP are added to each DLLP at both ends of the packet.

  In data transmission using such a symmetric bidirectional serial bus, in the case of unidirectional data transfer, the opposite bus only returns an ACK response, so the amount of data that can be transmitted per unit time, that is, Since the data bandwidth is wasted, there is a method of suppressing a decrease in the data bandwidth by making the bus multiplicity asymmetric (see, for example, Patent Document 1).

  Further, not only when a response at the time of data transmission is returned, but also when self-diagnosis information such as an error detected by the endpoint itself is transmitted to the root complex, there is a problem that data bandwidth is reduced and transmission delay occurs.

  Next, in the PCI Express communication system configured as described above, the problem of error processing in the transaction layer when the endpoint detects an error will be described in detail with reference to FIG.

  FIG. 10 is a diagram for explaining a problem when an error is detected during transmission of data transmitted from the endpoint 3a in the PCI Express communication system including the route complex 1, the switch 2, and the endpoints 3a to 3c. It is.

  FIG. 10A shows completion with data from the endpoint 3a to the root complex 1, that is, transmission of TLP2 of 1024 double words (hereinafter referred to as DW) to the root complex 1 while the endpoint 3b is transmitting TLP1. 6 shows a state when an error that cannot be repaired is detected in the untransmitted data of the TLP 1 in the end point 3a after starting the process.

  In this case, as shown in FIG. 10B, the end point 3a disables TLP1 by adding “EDB” (EnD Bad) instead of “END” as the control character at the end of the TLP, An attempt is made to send an error message TLP3 indicating that this error is fatal to the complex 1.

  Since the TLP 2 transmitted from the end point 3b is in a standby state in the buffer in the switch 2 until the transmission of the TLP 1 ends, as shown in FIG. 10C, when the transmission of the TLP 1 ends, the switch 2 , TLP2 is transmitted to the root complex 1. TLP3 of the error message waits in the buffer of switch 2 because TLP2 is transmitting.

  Then, as shown in FIG. 10D, when transmission of TLP2 is completed, transmission of TLP3 to the root complex 1 is started.

  In the case as described above, when the error message TLP3 is 2.5 Gbps and the number of lanes is 1, there is a problem that a maximum delay of about 16 μsec (1024 DW × 16 ns / DW) occurs. In the case where the switch 2 is a system in which many endpoints are connected, this delay may be further increased.

  Further, in the case of a duplex system in which the endpoint 3c is configured as a standby device of the endpoint 3a and the device is switched by using the TLP3 of this error message as a trigger, the malfunctioning endpoint 3a is There is a problem that a delay in switching time for switching to the standby endpoint 3c causes a failure of the duplex system.

JP 2008-219766 A

Nobutaka Arai, Naoshi Satomi, Akihiro Tanaka, "Introduction to PCI Express", Denpa Shimbun, Inc., issued April 1, 2007, Chapters 1-5

  As described above, for TLP transactions based on the conventional PCI Express specifications, there is a delay in sending errors as self-diagnostic information detected from the endpoint to the root complex when an error is detected. There is a problem that slows down.

  The present invention has been made to solve the above-described problems, and provides a PCI Express communication system capable of shortening a failure recovery time by improving a communication method of self-diagnosis information transmitted from an endpoint. With the goal.

  In order to achieve the above object, a PCI Express communication system according to claim 1 of the present invention is a PCI Express communication system in which a data bandwidth of data to be transmitted is set in advance. A route complex that includes a time synchronization signal generation unit that generates a time synchronization signal that presets the same transmission cycle, and data that is received from the end point and transmitted from the respective endpoints to the route complex. A plurality of endpoints including a synchronous transmission setting unit that exclusively sets data transmission timing and the data bandwidth, and a switch that relays data transmission between the root complex and the endpoint; And transmitting data from each of the endpoints to the root complex. And preset data bandwidth of data, with or without the set the data bandwidth of the error of the data, characterized by being adapted to transmit to the root complex.

  In order to achieve the above object, a PCI Express communication system according to claim 4 of the present invention is a PCI Express communication system in which a data bandwidth of data to be transmitted is preset, and data transmitted from a plurality of endpoints. In response to the time synchronization signal and a route complex including a time synchronization signal generation unit that generates a time synchronization signal that is set to be transmitted at an exclusive transmission timing between the endpoints in advance. Each of the plurality of endpoints for transmitting data to the root complex with a preset data bandwidth, and a switch for relaying transmission of data between the root complex and the endpoints. Self-diagnosis of transmitted data by exclusively setting the transmission cycle of data transmitted from the endpoint Distribution and, characterized in preset data bandwidth that is to be sent to the root complex.

  ADVANTAGE OF THE INVENTION According to this invention, the PCI Express communication system which can improve the communication method of the self-diagnosis information transmitted from an end point and can shorten failure recovery time can be provided.

The block diagram of the PCI Express communication system of this invention. FIG. 2 is an operation explanatory diagram of the PCI Express communication system according to the first embodiment of this invention. Explanatory drawing of the structure of the endpoint of this invention, and operation | movement of an endpoint. Comparison explanatory diagram of operation at the time of error detection of the present invention The block diagram of the PCI Express communication system of Example 2 of this invention. Explanatory drawing of operation | movement of the PCI Express communication system of Example 2 of this invention. The block diagram of the conventional PCI Express communication system. The figure explaining the structure of the conventional PCI Express. The figure explaining the conventional TLP format. The figure explaining the problem of the conventional PCI Express communication system.

  Hereinafter, this embodiment will be described with reference to the drawings.

  Embodiments of a PCI Express communication system according to the present invention will be described below with reference to the drawings.

  First, a description will be given with reference to FIGS. The same parts of the first embodiment as those of the PCI Express communication system of the conventional embodiment shown in FIGS. 7 to 10 are denoted by the same reference numerals, and the description thereof is omitted.

  The configuration of the first embodiment shown in FIG. 1 is different from that of the conventional PCI Express communication system shown in FIG. 7 in that the root complex 1 includes a time synchronization signal generator 1a1 and the end points 3a to 3 A synchronous transmission setting unit 3a1, which receives the time synchronization signal from the time synchronization signal generation unit 1a1 at the point 3c and sets the transmission timing of data including self-diagnosis information and its data bandwidth exclusively, The synchronous transmission setting unit 3b1 and the synchronous transmission setting unit 3c1 are provided.

  Before describing the configuration and operation of each part, first, the principle of the invention of the first embodiment will be described with reference to FIG.

  A PCI Express communication system configured so that the route complex 1 can receive data from a plurality of endpoints 3a to 3c via the switch 2 with a preset data bandwidth. In the time synchronization signal generation unit 1a1 provided, a time synchronization signal s1 having a preset transmission cycle is generated, and the plurality of endpoints 3a to 3c are connected to the plurality of endpoints 3a to 3c via the switch 2 as shown in FIG. As shown, the same time synchronization signal s1 is transmitted simultaneously (multicast).

  Each of the endpoints 3a to 3c receives the time synchronization signal s1, synchronizes with the time synchronization signal s1, and sets a preset transmission timing and data bandwidth. 3a1 to 3c1 exclusively generate respective transmission timing signals 3a1 to 3c1 from their own endpoints, and simultaneously transmit data and self-diagnosis information of the data in each data bandwidth Thus, the principle of the invention is to transmit the delay of the self-diagnosis information to the root complex 1 without delay.

  Next, the configuration and operation of the end point 3a (3b, 3c, which is referred to as the end point 3 when all these end points are called) for generating such a transmission timing signal will be described with reference to FIG. .

  The synchronization transmission setting unit 3a1 of the end point 3a receives a TLP in which a specific value is set in the message code as the time synchronization signal s1 from the root complex 1, and synchronizes with the time synchronization signal s1, and transmits from the own end point 3a. A counter setting circuit 11a that generates a transmission band reference signal s2 having a transmission value for designating the transmission timing, data bandwidth, and data bandwidth of each endpoint 3, and one of the transmission values. And a transmission value determination circuit 12a for transmitting the transaction layer self-diagnosis information at the transmission timing of the matched transmission value (signal s3a).

  The operation of the synchronous transmission setting unit 3a1 configured as described above will be described with reference to FIG. The time synchronization signal s1 is transmitted at a constant cycle Ts. However, the period Ts is set to be equal to or longer than the total time of the data bandwidths so that the data bandwidths of the plurality of endpoints 3 connected to the root complex 1 can be secured.

  The counter setting circuit 11a counts an internal clock signal (not shown) from the time synchronization signal s1, and generates a transmission band reference signal s2 having continuous transmission values (1 to n). For example, when the data bandwidths of n endpoints 3 are set to be the same, the width of each transmission value is set to the same signal width as Ts / n, and the transmission value is incremented in time series. Configure.

  In addition, the counter circuit 11a generates the same transmission band reference signal s2 with the same configuration at any end point 3.

  Next, the transmission value determination circuit 12a selects any transmission value of the transmission band reference signal s2 output from the counter circuit 11a, and generates the transmission timing signal s3a (˜s3n) of its own endpoint 3 Thus, different transmission values are preset in advance at the respective end points 3.

  For example, in the endpoint 3a, the transmission timing signal s3a is generated at a timing at which the transmission value 1 of the transmission band reference signal s2 matches the transmission value 1 set in the preset endpoint 3a, and in the endpoint 3b, A transmission timing signal s3b is generated at a timing at which the transmission value 2 of the transmission band reference signal s2 matches the preset transmission value 2.

  The endpoint 3 configured as described above exclusively transmits the data of each endpoint and the self-diagnosis information of the data at the timing set by each transmission value from the preset transmission band reference signal s2. Can be sent.

  The self-diagnosis information is configured to detect not only data error information caused by a soft error in the transaction layer but also hardware failure information of the PCI Express communication unit upper circuit.

The self-diagnosis information when the TLP is transmitted at the transmission timing of the set transmission value can be route-transmitted immediately.

  It is also possible to arbitrarily set the signal width of each transmission value of the transmission band reference signal s2, and to set the data bandwidth of data transmitted from each end point to be different.

  Next, referring to FIG. 4 for the operation at the time of error detection of the PCI Express communication system configured as described above, the operation at the time of error detection by the prior art (FIG. 4A) and the operation by this embodiment ( FIG. 4B will be described in comparison with a time chart.

  Transmission of completion data from the endpoint 3a to the root complex 1 is started (t1). Assume that data transmission from the endpoint 3b to the root complex 1 is started (t2) during this data transmission.

  After this, if an error is detected in the transmission data of the endpoint 3a (t3) and the self-diagnosis information of the error is transmitted at time t4, if there is no data transmission from the endpoint 3b, the error is transmitted to the route complex 1. Is received without delay at time t5, but if the transmission of data from the endpoint 3b is at time t2, the endpoint is received after the time t6 when the data transmission from the endpoint 3b is received at the route complex 1. The self-diagnosis information 3a is received at time t7.

  In this case, since the self-diagnosis information from the end point 3a requires a maximum transmission time of about 16 μsec, the self-diagnosis information in the route complex 1 is delayed by about 16 μsec from t5 to t7.

  However, according to the present embodiment, since the respective transmission timings and data bandwidths are exclusively set by the synchronization signal setting unit 3a1, the self-diagnosis information of the end point 3a is not delayed and is sent to the root complex 1 at time t5. Received at.

  Accordingly, the root complex 1 can immediately transmit the self-diagnosis information when transmitting the TLP at the transmission timing of the preset transmission value to the root complex 1, so that the system failure recovery determined by the root complex 1 side can be performed. Time can be shortened.

  Further, according to this embodiment, it is not necessary to make a special modification to the relay switch 2 and a general-purpose product can be used.

  Next, Example 2 will be described with reference to FIGS. The configuration of the second embodiment shown in FIG. 5 is different from the first embodiment shown in FIGS. 1 and 2 in that the time synchronization signal generation unit 1a1 provided in the root complex 1 in the first embodiment has a transmission cycle of the entire system. Are set by a time synchronization signal of one cycle, each end point 3 generates a transmission band reference signal s2 synchronized with the time synchronization signal s1, and each end point 3 is automatically transmitted from the transmission band reference signal s2. In the second embodiment, a plurality of time synchronization signals s1 are transmitted from the root complex 1 to the respective endpoints at exclusive transmission timings. Each data bandwidth is set.

  Therefore, the switch 2 and the end point 3 can be composed of general-purpose products.

  For example, as shown in FIG. 5, a TLP as a time synchronization signal s1a is transmitted to the end point 3a, and a time synchronization signal s1b is transmitted to the end point 3b after a predetermined time.

  By securing the interval between the time synchronization signal s1a and the time synchronization signal s1b for a predetermined time, the data bandwidth of the endpoint 3a can be secured.

  FIG. 6 shows a time chart of data transmission according to the present embodiment. Each time synchronization signal s1a (s1b, s1c) sets the data bandwidth of each endpoint 3 by transmitting the transmission timing at predetermined intervals Ts and at predetermined intervals.

  According to the second embodiment, the root complex 1 transmits a specific message TPL to each endpoint 3 as a time synchronization signal s1 (s1b, s1c), so that the load on the root complex 1 itself becomes heavy. The load on the transmission line is reduced.

  The present invention is not limited to the embodiments as described above, and the data bandwidth of each endpoint is exclusively set, and the data to be transmitted and its self-diagnosis information are transmitted in the data bandwidth. Any modifications can be made without departing from the spirit of the present invention.

1 Route complex 1a Time synchronization signal generator 2 Switch 3, 3a, 3b, 3c, 3d Endpoint 3a1, 3b1, 3c1 Synchronous transmission setting unit 5 CPU
6 Memory 7a, 7b, 7c, 7d PCI Express bus 11a Counter setting circuit 12a Transmission value determination circuit 5 CPU
6 memory

Claims (4)

A PCI Express communication system in which the data bandwidth of data to be transmitted is preset,
For a plurality of endpoints, at the same time, a root complex including a time synchronization signal generation unit that generates a time synchronization signal that presets the same transmission cycle;
The synchronous transmission setting unit that exclusively sets the transmission timing of the data and the data bandwidth in advance for the data that is received from the time synchronization signal and transmitted from the respective endpoints to the root complex. Multiple endpoints,
A switch that relays transmission of data between the root complex and the endpoint;
A data bandwidth of data transmitted from each of the end points to the root complex is set in advance, and the presence or absence of an error in the data is transmitted to the root complex in the set data bandwidth. PCI Express communication system. The time synchronization signal is transmitted as a TLP in which a specific value is set in a message code, and the synchronization transmission setting unit receives the time synchronization signal and transmits it from each endpoint in synchronization with the time synchronization signal. A counter setting circuit that generates a transmission band reference signal having a transmission value that specifies the transmission timing and data bandwidth of the data to be transmitted;
It is determined that one of the transmission values of the transmission band reference signal matches the transmission value of a preset self endpoint, and the transaction layer self-diagnosis information is transmitted at the transmission timing of the matching transmission value. The PCI Express communication system according to claim 1, further comprising a transmission value determination circuit.   The PCI Express communication system according to claim 1, wherein a transmission cycle of the time synchronization signal is set to be equal to or greater than a value obtained by adding data bandwidths of the plurality of endpoints. A PCI Express communication system in which the data bandwidth of data to be transmitted is preset,
A route complex including a time synchronization signal generating unit that generates a time synchronization signal in which a transmission cycle of data transmitted from a plurality of endpoints is set in advance so as to be transmitted between the endpoints at an exclusive transmission timing. When,
A plurality of endpoints transmitting data to the root complex with a preset data bandwidth in response to the time synchronization signal;
A switch that relays transmission of data between the root complex and the endpoint;
The transmission cycle of data transmitted from each of the endpoints is exclusively set, and self-diagnosis information of the data to be transmitted is transmitted to the root complex in a preset data bandwidth. PCI Express communication system.

Images