JP2003309372A - Thick film multilayer wiring board - Google Patents
Thick film multilayer wiring boardInfo
- Publication number
- JP2003309372A JP2003309372A JP2002115052A JP2002115052A JP2003309372A JP 2003309372 A JP2003309372 A JP 2003309372A JP 2002115052 A JP2002115052 A JP 2002115052A JP 2002115052 A JP2002115052 A JP 2002115052A JP 2003309372 A JP2003309372 A JP 2003309372A
- Authority
- JP
- Japan
- Prior art keywords
- thick
- wiring board
- multilayer wiring
- layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims abstract description 70
- 239000004020 conductor Substances 0.000 claims abstract description 41
- 239000002344 surface layer Substances 0.000 claims abstract description 18
- 239000000919 ceramic Substances 0.000 claims abstract description 8
- 238000009966 trimming Methods 0.000 claims abstract description 4
- 238000010030 laminating Methods 0.000 claims abstract 2
- 238000010304 firing Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000007639 printing Methods 0.000 description 9
- 239000011521 glass Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、厚膜多層配線基板
に係り、特にセラミック絶縁基板にＡｇ系導体、厚膜受
動素子（抵抗Ｒ・コイルＬ・コンデンサＣ）、絶縁層を
積層してなる厚膜多層配線基板上に、チップ電子部品等
を搭載し、電子回路基板の小型化・高密度化を図ること
のできる厚膜多層配線基板の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick-film multilayer wiring board, and in particular, a ceramic insulating board on which an Ag-based conductor, a thick-film passive element (a resistor R, a coil L, a capacitor C), and an insulating layer are laminated. The present invention relates to a structure of a thick-film multilayer wiring board, which can mount a chip electronic component or the like on the thick-film multilayer wiring board so as to reduce the size and density of an electronic circuit board.
【０００２】[0002]
【従来の技術】従来の厚膜基板は、絶縁基板上に導体、
抵抗体、及びオーバーコートガラスをそれぞれスクリー
ン印刷によって印刷、焼成して形成し、チップ電子部品
及びボンディングパッド等をはんだによって接続し、回
路基板を形成していた。2. Description of the Related Art A conventional thick film substrate is a conductor on an insulating substrate,
The resistor and the overcoat glass are formed by printing and firing by screen printing, respectively, and the chip electronic components, bonding pads and the like are connected by solder to form a circuit board.
【０００３】また、厚膜多層配線基板においては、内層
に受動素子、特に抵抗体を形成する場合、後工程の焼成
によって抵抗体の抵抗値が大きく変化して実用化が難し
いため、導体だけを内層に形成していた。Further, in a thick film multilayer wiring board, when forming passive elements, especially resistors in the inner layer, the resistance value of the resistors greatly changes due to the firing in the subsequent step and it is difficult to put them into practical use. It was formed on the inner layer.
【０００４】このような事情から従来の厚膜多層配線基
板では、近年の各種電子回路基板の小型化・高密度化の
対応が難しい状態にある。この種の従来例には、特開２
０００−２８６５３９号、特開２０００−３５３８７７
号、実開平５−６９９７７号等がある。Under these circumstances, it is difficult for the conventional thick film multilayer wiring board to cope with recent miniaturization and high density of various electronic circuit boards. Japanese Unexamined Patent Application Publication No.
000-286539, JP 2000-353877.
No., No. 5-69977, etc.
【０００５】[0005]
【発明が解決しようとする課題】このような従来の厚膜
多層配線基板にあっては、各種電子回路基板の小型化・
高密度化を図るには技術的に限界が有り、小型化・高密
度化を目的とした回路設計及び配線パターン設計が難し
いものとなっている。In such a conventional thick film multilayer wiring board, miniaturization of various electronic circuit boards,
There is a technical limit to achieving high density, and it is difficult to design circuits and wiring patterns for the purpose of downsizing and high density.
【０００６】本発明の目的は、配線基板の小型化・高密
度化を図ることのできる厚膜多層配線基板を提供するこ
とにある。An object of the present invention is to provide a thick film multi-layer wiring board which enables miniaturization and high density of the wiring board.
【０００７】[0007]
【課題を解決するための手段】本発明の特徴は、配線基
板を多層化（立体化）、内層、表層に形成する受動素子
を並列又は直列接続することによって実装面積を小さく
しようというものである。また、内層に形成した受動素
子の直上表面にチップ電子部品を搭載することにより配
線基板の小型化・高密度化を図ろうとするものである。A feature of the present invention is to reduce the mounting area by making a wiring board multi-layered (three-dimensional) and connecting passive elements formed in an inner layer and a surface layer in parallel or in series. . In addition, by mounting a chip electronic component on the surface immediately above the passive element formed in the inner layer, it is intended to reduce the size and density of the wiring board.
【０００８】より具体的には、上記目的を達成するため
請求項１に記載の厚膜多層配線基板は、セラミック絶縁
基板にＡｇ系導体、厚膜抵抗体、絶縁層を積層してなる
厚膜多層配線基板上に、チップ電子部品を搭載した厚膜
多層配線基板において，厚膜抵抗体を、内層と表層に分
け抵抗トリミング可能に形成し、内層厚膜抵抗体と表層
厚膜抵抗体を並列及び直列に接続することによって構成
したものである。このように構成することにより請求項
１に記載の発明によると、厚膜多層配線基板の小型化・
高密度化を図ることができる。More specifically, in order to achieve the above object, the thick-film multilayer wiring board according to claim 1 is a thick-film multilayer board in which an Ag-based conductor, a thick-film resistor, and an insulating layer are laminated on a ceramic insulating substrate. In a thick-film multilayer wiring board with chip electronic components mounted on the multilayer wiring board, the thick-film resistor is divided into an inner layer and a surface layer so that resistance trimming is possible, and the inner-layer thick-film resistor and the surface thick-film resistor are arranged in parallel. And a series connection. According to the invention as set forth in claim 1, the thick film multilayer wiring board is downsized.
Higher density can be achieved.
【０００９】上記目的を達成するため請求項２に記載の
厚膜多層配線基板は、内層厚膜抵抗体と表層厚膜抵抗体
とによって形成した厚膜抵抗体の上にチップ電子部品を
搭載して構成したものである。このように構成すること
により請求項２に記載の発明によると、厚膜多層配線基
板の小型化・高密度化を図ることができる。In order to achieve the above object, a thick film multilayer wiring board according to a second aspect of the present invention mounts a chip electronic component on a thick film resistor formed by an inner thick film resistor and a surface thick film resistor. It is configured by. According to the invention described in claim 2, with such a configuration, it is possible to reduce the size and increase the density of the thick film multilayer wiring board.
【００１０】上記目的を達成するため請求項３に記載の
厚膜多層配線基板は、要求抵抗値を、内層厚膜抵抗体の
焼成回数による抵抗値変化量に合わせてパターン設計を
行うことによって厚膜多層配線基板の内層で得るように
したものである。このように構成することにより請求項
３に記載の発明によると、厚膜多層配線基板の小型化・
高密度化を図ることができる。In order to achieve the above object, the thick-film multilayer wiring board according to claim 3 is designed by patterning the required resistance value according to the resistance value change amount depending on the number of firings of the inner-layer thick-film resistor. This is obtained at the inner layer of the film multilayer wiring board. According to the invention described in claim 3, with such a configuration, the thick film multilayer wiring board can be downsized.
Higher density can be achieved.
【００１１】上記目的を達成するため請求項４に記載の
厚膜多層配線基板は、要求抵抗値を内層厚膜抵抗体の焼
成回数による抵抗値変化量に合わせて抵抗ペーストを使
用することによって厚膜多層配線基板の内層で得るよう
にしたものである。このように構成することにより請求
項４に記載の発明によると、厚膜多層配線基板の小型化
・高密度化を図ることができる。In order to achieve the above object, the thick film multilayer wiring board according to the present invention can be formed by using a resistance paste by adjusting the required resistance value to the resistance value change amount depending on the number of firings of the inner layer thick film resistor. This is obtained at the inner layer of the film multilayer wiring board. With this structure, according to the invention of claim 4, the thick-film multilayer wiring board can be downsized and the density can be increased.
【００１２】上記目的を達成するため請求項５に記載の
厚膜多層配線基板は、複数積層してなる絶縁層の最下層
に設けられる第１の導体と該絶縁層の最上層に設けられ
る第２の導体とを有し，第２の導体と絶縁層とを貫通し
てビアホールを形成し，ビアホールに埋め込むコンタク
ト導体を絶縁層の積層数と同じ層数に形成したものであ
る。このように構成することにより請求項５に記載の発
明によると、厚膜多層配線基板の小型化・高密度化を図
ることができる。In order to achieve the above object, a thick film multilayer wiring board according to a fifth aspect of the present invention is provided with a first conductor provided on the lowermost layer of a plurality of insulating layers and a first conductor provided on the uppermost layer of the insulating layer. Two conductors are provided, a via hole is formed through the second conductor and the insulating layer, and contact conductors to be embedded in the via hole are formed in the same number as the number of laminated insulating layers. With this structure, the thick film multilayer wiring board can be miniaturized and the density can be increased.
【００１３】上記目的を達成するため請求項６に記載の
厚膜多層配線基板は、ビアホールを、最下層絶縁層のビ
アホール径から最上層絶縁層のビアホール径に向かって
段階的に大きな径に形成し，ビアホール径の大きさが段
階的に異なるビアホールにコンタクト導体を埋め込ん
で、第１の導体と第２の導体とを電気的に接続したもの
である。このように構成することにより請求項６に記載
の発明によると、厚膜多層配線基板の小型化・高密度化
を図ることができる。In order to achieve the above object, in the thick film multilayer wiring board according to the present invention, the via hole is formed to have a diameter gradually increasing from the via hole diameter of the lowermost insulating layer to the via hole diameter of the uppermost insulating layer. The first conductor and the second conductor are electrically connected by embedding a contact conductor in the via hole having a stepwise difference in via hole diameter. With this structure, according to the invention of claim 6, it is possible to reduce the size and density of the thick-film multilayer wiring board.
【００１４】[0014]
【発明の実施の形態】以下、本発明に係る厚膜多層配線
基板の実施の形態について３層構造を例にとって説明す
る。図１には、本発明に係る厚膜多層配線基板の一実施
の形態が示されている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a thick film multilayer wiring board according to the present invention will be described below by taking a three-layer structure as an example. FIG. 1 shows an embodiment of a thick film multilayer wiring board according to the present invention.
【００１５】図１において、厚膜多層配線基板１は、次
のように構成されている。In FIG. 1, the thick film multilayer wiring board 1 is constructed as follows.
【００１６】すなわち、まず、セラミック絶縁基板２に
Ａｇ系導体（第１導体）４ａ及び厚膜受動素子である厚
膜コンデンサ８を印刷・焼成して形成し、その上に絶縁
層３ａ、絶縁層３ｂ及びコンタクト導体６を印刷・焼成
して形成する。そして、この上にＡｇ系導体（第２導
体）４ｂ、内層抵抗体７ａを印刷・焼成し、その上に絶
縁層３ｃ、絶縁層３ｄ及びコンタクト導体６を印刷・焼
成して形成する。更に、この上にＡｇ系導体（表層導
体）５、表層抵抗体７ｂ及びオーバーコートガラス９を
同様に形成した多層厚膜配線基板の部品搭載部にはんだ
ペーストを印刷しチップ電子部品１０・チップＩＣ１１
・ボンディングパッド１２等を搭載しはんだ１４、リフ
ロー・ワイヤーボンディング（アルミ線１３、金線１
５）にて電気的接続する構造となっている。That is, first, an Ag-based conductor (first conductor) 4a and a thick film capacitor 8 which is a thick film passive element are formed by printing and firing on a ceramic insulating substrate 2, and an insulating layer 3a and an insulating layer are formed thereon. 3b and the contact conductor 6 are formed by printing and firing. Then, an Ag-based conductor (second conductor) 4b and an inner layer resistor 7a are printed and fired on this, and an insulating layer 3c, an insulating layer 3d and a contact conductor 6 are printed and fired thereon. Further, a solder paste is printed on the component mounting portion of the multilayer thick film wiring board on which the Ag-based conductor (surface layer conductor) 5, the surface layer resistor 7b and the overcoat glass 9 are similarly formed, and the chip electronic component 10 and the chip IC 11 are printed.
-Mounting the bonding pad 12 etc., solder 14, reflow wire bonding (aluminum wire 13, gold wire 1
It has a structure for electrical connection in 5).
【００１７】このような構造について、厚膜受動素子、
特に厚膜抵抗体を例にとって、図２〜図４を用いて説明
すると、まず、セラミック絶縁基板２にＡｇ系内層導体
４及び内層厚膜抵抗体７ａを印刷・焼成して形成する。
その上に絶縁層３ａ、絶縁層３ｂ及びコンタクト導体６
を印刷・焼成して形成する。さらにその上に表層導体
５、表層厚膜抵抗体７ｂ及びオーバーコートガラス９を
印刷・焼成して形成する。このとき、内層厚膜抵抗体７
ａと表層厚膜抵抗体７ｂを並列及び直列接続することに
より抵抗体パターンが従来の約１／２の面積に縮小でき
る。Regarding such a structure, a thick film passive element,
2 to 4, the thick film resistor will be described as an example. First, the Ag-based inner layer conductor 4 and the inner layer thick film resistor 7a are formed on the ceramic insulating substrate 2 by printing and firing.
Insulating layer 3a, insulating layer 3b, and contact conductor 6 are formed on top of it.
Is formed by printing and firing. Further, the surface layer conductor 5, the surface layer thick film resistor 7b and the overcoat glass 9 are formed by printing and firing thereon. At this time, the inner thick film resistor 7
By connecting a and the surface thick film resistor 7b in parallel and in series, the area of the resistor pattern can be reduced to about 1/2 of the conventional area.
【００１８】図３に示す如き並列接続は、特に、消費電
力の大きい抵抗体に優位で、例えば消費電力１Ｗの１Ｋ
Ωの抵抗体は、従来、パターン寸法をＬ＝３．２ｍｍ／
Ｗ＝３．２ｍｍ／Ｐ＝１．０２４ｗ／Ｒ０＝１ＫΩで設
計していた。ところが、図２に示す如き構造を使用する
ことによって、Ｒ２を内層抵抗体とし、Ｒ１を表層抵抗
体に形成しそれぞれ２ＫΩパターン寸法Ｌ＝３．２ｍｍ
／Ｗ＝１．６ｍｍ／Ｐ＝０．５１２ｗ／Ｒ１・２＝２Ｋ
Ωにし上下の並列接続することにより、表層抵抗体パタ
ーンが１／２の面積で同じ消費電力の抵抗体の形成が可
能となる。The parallel connection as shown in FIG. 3 is particularly advantageous for a resistor which consumes a large amount of power, for example, 1K which consumes 1W.
Conventionally, the resistor of Ω has a pattern dimension of L = 3.2 mm /
The design was W = 3.2 mm / P = 1.024 w / R0 = 1 KΩ. However, by using the structure as shown in FIG. 2, R2 is formed as an inner layer resistor and R1 is formed as a surface layer resistor, and each 2KΩ pattern dimension L = 3.2 mm.
/W=1.6mm/P=0.512w/R1 ・ 2 = 2K
By connecting the upper and lower sides in parallel with each other with Ω, it is possible to form a resistor having a surface layer resistor pattern having a half area and the same power consumption.
【００１９】図４に示す如き直列接続は、例えば、２Ｋ
Ωの抵抗体を形成すると、従来、パターン寸法をＬ＝２
ｍｍ／Ｗ＝１ｍｍ／Ｒ０＝２ＫΩで設計していた。とこ
ろが、図２に示す如き構造を使用することによって、Ｒ
２を内層抵抗体とし、Ｒ１を表層抵抗体に形成し、それ
ぞれ１ＫΩパターン寸法Ｌ＝１ｍｍ／Ｗ＝１ｍｍ／Ｒ１
・Ｒ２＝１ＫΩにし、上下を直列接続することによって
表層抵抗体パターンが１／２の面積で同じ抵抗値を得る
ことができる。The series connection as shown in FIG. 4 is, for example, 2K.
When a resistor of Ω is formed, the pattern size is conventionally L = 2.
It was designed with mm / W = 1 mm / R0 = 2 KΩ. However, by using the structure shown in FIG.
2 is the inner layer resistor, R1 is formed on the surface layer resistor, and 1 KΩ pattern dimension L = 1 mm / W = 1 mm / R1
By setting R2 = 1 KΩ and connecting the upper and lower sides in series, the same resistance value can be obtained with a surface layer resistor pattern having an area of 1/2.
【００２０】また、内層厚膜抵抗体７ａは、トリミング
による抵抗値調整が不可能であり抵抗精度に限度があっ
たその点に付いても本構造は表層抵抗体をトリミングで
きるため解決可能である。さらにまた、表層厚膜抵抗体
７ｂの上にチップ電子部品１０等の搭載も可能でさらに
高密度化を図ることができる。ここでは、抵抗体に付い
て説明したが図５で示すような抵抗体以外の受動素子
（Ｌ・Ｃ）においても同様に構成することができる。Further, the inner thick film resistor 7a cannot be adjusted in resistance by trimming and the resistance accuracy is limited. However, this structure can be solved because the surface resistor can be trimmed. . Furthermore, the chip electronic component 10 or the like can be mounted on the surface thick film resistor 7b, and the density can be further increased. Although the resistor has been described here, the passive element (LC) other than the resistor as shown in FIG. 5 can be similarly configured.
【００２１】厚膜抵抗体７を内層に形成するに当たり内
層厚膜抵抗体７ａの形成後の焼成工程にあっては、内層
厚膜抵抗体７ａの抵抗値が変化する。本実施例において
は、図６に示した内層厚膜抵抗体７ａの形成後の焼成に
よる抵抗値変化率を把握し内層厚膜抵抗体７ａの形成後
の焼成回数により変化する抵抗に合わせたパターン設計
を実施することにより目標とする抵抗値を得られる。ま
た、図６の変化率に合わせた抵抗ペーストをブレンド等
によって作ることでも目標とする抵抗値を得ることがで
きる。In forming the thick film resistor 7 in the inner layer, the resistance value of the inner thick film resistor 7a changes in the firing step after the formation of the inner thick film resistor 7a. In the present embodiment, the rate of change in resistance value due to firing after formation of the inner thick film resistor 7a shown in FIG. 6 is grasped, and a pattern matched to the resistance that changes depending on the number of firings after formation of the inner thick film resistor 7a is formed. A target resistance value can be obtained by implementing the design. The target resistance value can also be obtained by making a resistance paste that matches the rate of change in FIG. 6 by blending or the like.
【００２２】例えば、内層厚膜抵抗体７ａの形成後に４
回の焼成工程がある場合は、１００ｋΩのシート抵抗を
使用する抵抗体に付いては６５％抵抗値が下がるため初
期抵抗値を６５％上げたパターンに設計する。または、
ペーストのブレンドによって６５％上げたペーストとし
目標抵抗値を形成する。同様に１０ｋΩのシート抵抗を
使用する抵抗体は、１５％上げ、１ｋΩのシート抵抗を
使用する抵抗体は９０％下げ対応することにより目標抵
抗値を形成することができる。For example, after forming the inner thick film resistor 7a, 4
In the case where the firing process is performed twice, the resistance value using the sheet resistance of 100 kΩ is reduced by 65%, so the initial resistance value is increased by 65%. Or
The target resistance value is formed by increasing the paste by 65% by blending the pastes. Similarly, a resistor using a sheet resistance of 10 kΩ is increased by 15%, and a resistor using a sheet resistance of 1 kΩ is decreased by 90%, so that a target resistance value can be formed.
【００２３】次に、絶縁層間のビアホール形成構造の特
徴に付いて図７を用いて説明する。図７が本実施例によ
る構造であり、絶縁基板２の上に内層導体４ａを印刷・
焼成して形成してある。その上に絶縁層３ａ及びコンタ
クト導体６ａを印刷・同時焼成する。さらに、絶縁層３
ｂを印刷・焼成し、最後にコンタクト導体６ｂを印刷・
焼成して１層が形成されている。Next, the features of the structure for forming via holes between insulating layers will be described with reference to FIG. FIG. 7 shows the structure according to this embodiment, in which the inner layer conductor 4a is printed on the insulating substrate 2.
It is formed by firing. The insulating layer 3a and the contact conductor 6a are printed and co-fired thereon. Furthermore, the insulating layer 3
b is printed and fired, and finally contact conductor 6b is printed and
One layer is formed by firing.
【００２４】このとき絶縁層３ａのビアホールを例えば
φ０．３ｍｍにしたとき、絶縁層３ｂはφ０．４ｍｍと
大きくする構造とし、図８で示す印刷ダレを抑制する。
また、コンタクト導体を６ａ・６ｂと２回にすることで
ビアホール部の凹みを抑制する構造とし接続信頼性の優
れた構造とすることができる。At this time, when the via hole of the insulating layer 3a is set to, for example, φ0.3 mm, the insulating layer 3b is made to be as large as φ0.4 mm to suppress the printing sag shown in FIG.
Further, by using the contact conductors 6a and 6b twice, it is possible to obtain a structure that suppresses the depression of the via hole portion and has a structure with excellent connection reliability.
【００２５】このようにして構成した厚膜多層配線基板
１は、図９に示す如き構成となる。すなわち、厚膜多層
配線基板１は、セラミック絶縁基板２にＡｇ系内層導体
４及び内層厚膜抵抗体７ａを印刷・焼成して形成し、そ
の上に絶縁層３ａ、絶縁層３ｂ及びコンタクト導体６を
印刷・焼成して形成し、さらにその上に表層導体５、表
層厚膜抵抗体７ｂ及びオーバーコートガラス９をそれぞ
れスクリーン印刷にて印刷・焼成して形成し、チップ電
子部品１０、１１及びボンディングパッド１２等をはん
だ１４にて接続し回路基板を形成している。１３は、ア
ルミ線である。The thick film multilayer wiring board 1 thus constructed has a construction as shown in FIG. That is, the thick film multilayer wiring substrate 1 is formed by printing and firing the Ag-based inner layer conductor 4 and the inner layer thick film resistor 7a on the ceramic insulating substrate 2, and then forming the insulating layer 3a, the insulating layer 3b, and the contact conductor 6 thereon. Is formed by printing and firing, and the surface conductor 5, the surface thick film resistor 7b, and the overcoat glass 9 are printed and fired thereon by screen printing to form chip electronic components 10 and 11 and bonding. The pads 12 and the like are connected with solder 14 to form a circuit board. 13 is an aluminum wire.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
配線基板を多層化（立体化）、内層、表層に形成する受
動素子を並列又は直列接続することによって実装面積を
小さくすることができる。As described above, according to the present invention,
The mounting area can be reduced by forming the wiring board in multiple layers (three-dimensional) and connecting passive elements formed in the inner layer and the surface layer in parallel or in series.
【００２７】また、本発明によれば、内層に形成した受
動素子の直上表面にチップ電子部品を搭載することによ
り配線基板の小型化・高密度化を図ることができる。Further, according to the present invention, by mounting the chip electronic component on the surface immediately above the passive element formed in the inner layer, it is possible to reduce the size and density of the wiring board.
【図１】本発明の一実施の形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】図１に図示の抵抗体の構成を示す局部断面図で
ある。FIG. 2 is a local cross-sectional view showing the configuration of the resistor body shown in FIG.
【図３】図１に図示の表層抵抗対の並列接続時のパター
ン図である。FIG. 3 is a pattern diagram when the surface layer resistance pairs shown in FIG. 1 are connected in parallel.
【図４】図１に図示の表層抵抗対の直列接続時のパター
ン図である。FIG. 4 is a pattern diagram when the surface layer resistance pairs shown in FIG. 1 are connected in series.
【図５】図１に図示の抵抗体以外の受動素子（Ｌ・Ｃ）
の構成を示す局部断面図である。5 is a passive element (LC) other than the resistor shown in FIG.
It is a local cross-sectional view showing the configuration of.
【図６】焼成回数による抵抗変化を示す図である。FIG. 6 is a diagram showing a resistance change depending on the number of firings.
【図７】ビアホール部の局部断面図である。FIG. 7 is a partial sectional view of a via hole portion.
【図８】図７に図示のビアホール部の効果を説明するた
めの局部断面図である。FIG. 8 is a local cross-sectional view for explaining the effect of the via hole portion shown in FIG.
【図９】図１に図示の厚膜多層配線基板の斜視図であ
る。9 is a perspective view of the thick film multilayer wiring board illustrated in FIG. 1. FIG.
１…………………厚膜多層配線基板 ２…………………セラミック絶縁基板 ３ａ〜ｄ…………絶縁層 ４ａ〜ｂ…………Ａｇ系内層導体 ５…………………Ａｇ系表層導体 ６…………………コンタクト導体 ７ａ………………内層抵抗体（厚膜抵抗体） ７ｂ………………表層抵抗体（厚膜抵抗体） ８…………………厚膜コンデンサ ９…………………オーバーコートガラス １０………………チップ電子部品 １１………………チップＩＣ １２………………ボンディングパッド １３………………アルミ線 １４………………はんだ １５………………金線 1 ………………………… Thick film multilayer wiring board 2 …………………… Ceramic insulating substrate 3a-d ………… Insulating layer 4a-b ............ Ag system inner layer conductor 5 …………………… Ag system surface conductor 6 …………………… Contact conductor 7a ……………… Inner layer resistor (thick film resistor) 7b ……………… Surface layer resistor (thick film resistor) 8 …………………… Thick film capacitor 9 …………………… Overcoat glass 10 ……………… Chip electronic components 11 ……………… Chip IC 12 ……………… Bonding pad 13 ……………… Aluminum wire 14 ……………… Solder 15 ……………… Gold wire
───────────────────────────────────────────────────── フロントページの続き (72)発明者 湖口 秀和 茨城県ひたちなか市大字高場2520番地 株 式会社日立製作所自動車機器グループ内 Ｆターム(参考） 4E351 AA07 AA13 BB05 BB24 BB26 BB31 CC11 CC23 DD01 EE01 FF04 FF06 GG01 GG06 5E346 AA02 AA12 AA14 AA15 AA17 AA32 AA43 BB01 BB20 CC01 CC39 CC46 DD03 DD09 DD13 DD34 EE32 FF35 FF45 GG18 GG19 GG40 HH01 HH22 HH33 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hidekazu Koguchi Hitachinaka City, Ibaraki Prefecture 2520 Takaba Ceremony Company Hitachi Ltd. Automotive equipment group F-term (reference) 4E351 AA07 AA13 BB05 BB24 BB26 BB31 CC11 CC23 DD01 EE01 FF04 FF06 GG01 GG06 5E346 AA02 AA12 AA14 AA15 AA17 AA32 AA43 BB01 BB20 CC01 CC39 CC46 DD03 DD09 DD13 DD34 EE32 FF35 FF45 GG18 GG19 GG40 HH01 HH22 HH33
Claims (6)
抵抗体、絶縁層を積層してなる厚膜多層配線基板上に、
チップ電子部品を搭載した厚膜多層配線基板において，
前記厚膜抵抗体を、内層と表層に分け抵抗トリミング可
能に形成し、前記内層厚膜抵抗体と表層厚膜抵抗体を並
列及び直列に接続することによって構成したことを特徴
とする厚膜多層配線基板。1. A thick-film multi-layer wiring substrate, which is formed by laminating an Ag-based conductor, a thick-film resistor, and an insulating layer on a ceramic insulating substrate.
In a thick film multilayer wiring board with chip electronic components,
A thick-film multilayer, wherein the thick-film resistor is divided into an inner layer and a surface layer so that resistance trimming is possible, and the inner-layer thick-film resistor and the surface layer thick-film resistor are connected in parallel and in series. Wiring board.
いて，前記内層厚膜抵抗体と前記表層厚膜抵抗体とによ
って形成した前記厚膜抵抗体の上にチップ電子部品を搭
載してなる厚膜多層配線基板。2. The thick-film multilayer wiring board according to claim 1, wherein a chip electronic component is mounted on the thick-film resistor formed by the inner-layer thick-film resistor and the surface thick-film resistor. Thick multilayer wiring board.
いて，要求抵抗値を、前記内層厚膜抵抗体の焼成回数に
よる抵抗値変化量に合わせてパターン設計を行うことに
よって前記厚膜多層配線基板の内層で得るようにしたこ
とを特徴とする厚膜多層配線基板。3. The thick film multilayer wiring board according to claim 2, wherein the required resistance value is designed in accordance with a resistance value change amount depending on the number of firings of the inner layer thick film resistor to perform pattern design. A thick film multilayer wiring board characterized by being obtained in an inner layer of the wiring board.
いて，要求抵抗値を、前記内層厚膜抵抗体の焼成回数に
よる抵抗値変化量に合わせた抵抗ペーストを使用するこ
とによって前記厚膜多層配線基板の内層で得るようにし
たことを特徴とする厚膜多層配線基板。4. The thick film multilayer wiring board according to claim 2, wherein the thick film is formed by using a resistance paste in which a required resistance value is matched with a resistance value change amount depending on the number of firings of the inner layer thick film resistor. A thick film multilayer wiring board characterized by being obtained in an inner layer of the multilayer wiring board.
られる第１の導体と該絶縁層の最上層に設けられる第２
の導体とを有し，前記第２の導体と前記絶縁層とを貫通
してビアホールを形成し，前記該ビアホールに埋め込む
コンタクト導体を前記絶縁層の積層数と同じ層数に形成
したことを特徴とする厚膜多層配線基板。5. A first conductor provided in the lowermost layer of a plurality of insulating layers and a second conductor provided in the uppermost layer of the insulating layers.
And a via hole is formed penetrating the second conductor and the insulating layer, and a contact conductor embedded in the via hole is formed in the same number as the number of laminated insulating layers. And a thick film multilayer wiring board.
いて，前記ビアホールを、前記最下層絶縁層のビアホー
ル径から前記最上層絶縁層のビアホール径に向かって段
階的に大きな径に形成し，前記ビアホール径の大きさが
段階的に異なるビアホールにコンタクト導体を埋め込ん
で、第１の導体と第２の導体とを電気的に接続したこと
を特徴とする厚膜多層配線基板。6. The thick-film multilayer wiring board according to claim 5, wherein the via hole is formed to have a diameter gradually increasing from a via hole diameter of the lowermost insulating layer to a via hole diameter of the uppermost insulating layer. A thick film multilayer wiring board, wherein a contact conductor is embedded in a via hole having a stepwise difference in via hole diameter to electrically connect a first conductor and a second conductor.
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| JP2002115052A JP3913094B2 (en) | 2002-04-17 | 2002-04-17 | Thick film multilayer wiring board |
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|---|---|---|---|
| JP2002115052A JP3913094B2 (en) | 2002-04-17 | 2002-04-17 | Thick film multilayer wiring board |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008026513A (en) * | 2006-07-20 | 2008-02-07 | Sony Corp | Display device |
| KR101046138B1 (en) * | 2009-07-17 | 2011-07-01 | 삼성전기주식회사 | Multilayer Wiring Board and Manufacturing Method Thereof |
| CN109244045A (en) * | 2018-09-29 | 2019-01-18 | 北方电子研究院安徽有限公司 | A kind of thick film substrate miniaturization Can encapsulating structure |
| WO2022005097A1 (en) * | 2020-07-01 | 2022-01-06 | 주식회사 아모센스 | Power module and method for manufacturing ceramic substrate included therein |
-
2002
- 2002-04-17 JP JP2002115052A patent/JP3913094B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008026513A (en) * | 2006-07-20 | 2008-02-07 | Sony Corp | Display device |
| KR101046138B1 (en) * | 2009-07-17 | 2011-07-01 | 삼성전기주식회사 | Multilayer Wiring Board and Manufacturing Method Thereof |
| CN109244045A (en) * | 2018-09-29 | 2019-01-18 | 北方电子研究院安徽有限公司 | A kind of thick film substrate miniaturization Can encapsulating structure |
| CN109244045B (en) * | 2018-09-29 | 2024-04-05 | 北方电子研究院安徽有限公司 | Miniaturized metal tube shell packaging structure of thick film substrate |
| WO2022005097A1 (en) * | 2020-07-01 | 2022-01-06 | 주식회사 아모센스 | Power module and method for manufacturing ceramic substrate included therein |
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|---|---|
| JP3913094B2 (en) | 2007-05-09 |
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