EP0021250A1 - Traffic signal systems - Google Patents

Abstract

The invention relates to a method and a circuit arrangement for generating setting signals for signal transmitters of a traffic signal system, in particular a road traffic signal system, using information contained in an intermediate times matrix of intermediate times between mutually hostile traffic flows. The point is that for influencing or determining a signal change, either all or only certain selected entry signal groups of the entry signal groups hostile to the respective clearing signal groups should be decisive. For this purpose, according to a solution for each entry signal group (Sge), the intermediate times of the enemy clearance signal groups (Sgr) are read out from the split times matrix (ZM) and subtracted from the largest intermediate value relevant for the relevant entry signal group (Sge) . The value of the largest intermediate value in question is cyclically successively reduced. If this value is reduced to zero or if a zero difference is found in the course of the aforementioned difference formation, appropriate setting signals are emitted for the signal transmitters of the traffic signal system. Another solution to the problem shown is

Description

The invention relates to a method and a circuit arrangement for generating setting signals for signal transmitters of a traffic signal system, in particular a road traffic signal system, using information contained in an intermediate times matrix of intermediate times between mutually hostile traffic flows.

A method and a device for ensuring the intermediate times in road traffic signal systems are already known (DE-Note P 27 39 616.3). In this known method and in this known device, at the end of the green time of each individual signal of the traffic flows which are to be regulated independently, the time which then runs is summed up in actual value memories. These actual value memories are combined with the target value memories of the traffic flows hostile to the green signal to be switched on compared, and when the specified values are reached or exceeded, the associated switch-on command is released. In addition, all of the setpoint memory contents are summed in shorter intervals than the time cycle of the traffic signal system corresponds to another actual value memory, the content of which is compared with the content of a setpoint memory. If an error occurs, appropriate safety precautions are triggered. In this case, however, a corresponding command from the control center provided to the respective signal generator gives a switch-on command for switching on a green signal only when a coincidence check has established that all signal groups which are hostile to the signal group belonging to the respective signal generator each have specified clearing times (i.e. the time periods since the end of each green) have expired. The control signals required for activating the respective signal transmitter at the end of the green - that is to say so-called Rotbe & nLe― - take effect immediately, ie immediately with the signal transmitter in question. However, this means that such signal generators that could still remain set to green are disadvantageously set to red, at least in relation to the signal generators that subsequently receive green commands. Thus, in the known method concerned, there is only a relatively poor utilization of the actually available clearing times.

The invention is therefore based on the object of showing a way how. Setting signals for the optimal setting of signal transmitters of a traffic signal system and in particular a road traffic signal system can be generated in a simpler manner. In contrast to the previously known method, red commands should only take effect as late as the actual clearing times require.

The object outlined above is achieved according to the invention in a method of the type mentioned at the outset in that, from the split times matrix for each signal group as an at least one traffic flow, the entry signal group issuing a release setting signal contains the entry intermediate times in relation to those, clearing signal groups representing signal groups are read out and stored separately, which are used to control traffic flows that are hostile to the traffic flows controlled by the respective entry signal group, that in addition the largest intermediate entry time for the respective entry signal group is stored separately and cyclically in sequence in its value is reduced to zero so that the remaining entry times stored for the same entry signal group are subtracted separately from the largest entry intermediate times stored for the respective entry signal group and the value of which is cyclically reduced in succession If a zero difference occurs between two such subtracted entry intermediate times, a lock setting signal is emitted for that clearing signal group to which the intermediate entry time used in the relevant difference formation is based, and that after Reduction of the originally largest entry intermediate time to zero of the relevant associated entry signal group is supplied with a release setting signal.

The invention has the advantage that optimal setting signals for signal transmitters of a traffic signal system and in particular a road traffic system can be generated in a simple manner with regard to the actually existing clearing times. This is because only the information contained in an intermediate times matrix of intermediate times between traffic flows which are hostile to one another is used in order to generate the setting signals in question for the signal transmitters.

The largest entry intermediate time for the respective entry signal group is expediently reduced in value by one second. This has the advantage that time values based on seconds can be contained in the intermediate times matrix, which leads to particularly simple processing of the values contained in this intermediate times matrix.

To carry out the method according to the invention, it is expedient to use a circuit arrangement which is characterized in that an interrogation circuit is connected to the interim matrix, which, from the interim matrix, shows the interim times of all entry signal groups to the associated ones reads enemy clearing signal group and stores in the respective entry signal group the associated registers and the largest intermediate time of these intermediate times in a separate memory belonging to the relevant entry signal group, in which the relevant intermediate time can be reduced to zero in successive control cycles that the registers and the memory are subtracted downstream, which form the difference between the intermediate time value contained in the memory belonging to the respective entry signal group and the intermediate times contained in the associated registers, and that with respect to each entry signal group The difference values formed and the intermediate time value contained in the associated memory can be evaluated by means of evaluation circuits, each of which determines a difference value of zero or an intermediate value reduced to zero _. because output an output signal for the appropriate setting of the associated signal generator. This results in the advantage of a particularly low outlay in terms of circuitry for generating setting signals for signal generators of a traffic signal system and in particular a road traffic signal system.

The query circuit is preferably controlled by counters, one of which designates entry signal groups by its counter positions and the other by its counter positions designates the clearing signal groups hostile to the respective entry signal group; the counters are adjustable by a control device. This results in the advantage of a particularly simple possibility of reading out the time values contained in the intermediate time matrix for the generation of the setting signals mentioned.

With the help of the above-mentioned method according to the invention, it is thus possible in a simple manner to be able to generate optimal setting signals for signal generators of a traffic signal system and in particular a road traffic signal system with regard to the actual clearing times, namely only the information contained in an intermediate time matrix of Intermediate times between hostile traffic flows are used to generate the setting signals in question for the signal transmitters. However, it has been shown that it is sometimes impractical to take into account the entry intermediate times of all entry signal groups hostile to one and the same clearing signal groups when determining a signal change. For example, it often happens that certain signal groups, in particular pedestrian signal groups, which are to receive an enable signal, namely a green signal, because of their large interruptions, the termination of hostile signal groups, in particular vehicle signal groups, which make the current phase necessary. These vehicle signal groups could be related to them in turn, keep enemy vehicle signal groups green for a long period of time.

According to a further embodiment of the invention, in order to take into account only desired entry intermediate times for influencing a signal change from the entry intermediate times which are hostile to one and the same clearing signal groups and are read from the intermediate time matrix, Matrix read-in and separately stored entry intermediate times of those entry signal groups that are hostile to one and the same clearing signal groups, to obtain the intermediate times of the entry signal groups selected as irrelevant for influencing a signal change by means of separate marking, initially unchanged in their value and only then in the case of reducing their value to make effective that the unmarked entry intermediate times of the entry signal groups hostile to the same clearing signal groups have expired, and after the respective marked entry intermediate time has been reduced to zero belonging to the relevant entry en entry signal group to supply a release setting signal.

This results in the advantage that only certain desired entry times for the respective signal change are taken into account in a relatively simple manner from the entry times between the entry times read from the split times matrix and stored separately in the entry signal groups hostile to the same clearing signal groups can, while other selected entry intermediate times can be disregarded for influencing the respective signal change. However, this does not mean that the last intermediate times mentioned are completely ignored be sen; they are already taken into account with regard to their associated entry signal group, but not for influencing the general signal change between the signal groups which are hostile to one another.

Of the marked entry intermediate times belonging to an entry signal group, only the largest entry intermediate time is preferably used to generate an enable setting signal for the entry signal group concerned. This has the advantage of particularly easy handling of the marked intermediate entry times.

The largest intermediate entry time and the marked activated intermediate entry time are expediently reduced in value every 1 sec. This has the advantage that time values related to seconds can be contained in the intermediate times matrix, which leads to particularly simple processing of the values contained in this intermediate times matrix.

To carry out the method which represents a further embodiment of the invention, it is expedient to use a circuit arrangement corresponding to the circuit arrangement already specified above. A query circuit is connected to the intermediate times matrix, which reads the intermediate times of all entry signal groups to the hostile clearing signal groups from the intermediate times matrix and registers belonging to the respective entry signal group and the The largest intermediate time of these intermediate times is stored in a separate memory belonging to the relevant entry signal group, in which the relevant intermediate time can be reduced in value to zero in successive control cycles. Subtractor circuits are arranged downstream of the registers and the memory, which form the difference between the intermediate value contained in the memory associated with the respective entry signal group and the intermediate times contained in the associated registers. The difference values formed with respect to each entry signal group and the intermediate time value contained in the associated memory can be evaluated by means of an evaluation circuit which, when a difference value of zero or an intermediate value reduced to zero is determined, each have an output signal (binary signal "H") for the corresponding setting of the associated one Submit signal generator. According to the present invention, this switching arrangement is characterized in that the intermediate times of entry signal groups selected as immaterial for influencing a signal change of the entry intermediate times read out from the intermediate times matrix are each stored in a separate register as marked entry intermediate times, which with a control input receives its stored intermediate time value-reducing control impulses from a linkage arrangement only in the event that the intermediate entry times of those entry signal groups are reduced to zero, which together with the entry signal groups marked with regard to the intermediate entry times to the same Clear signal groups are hostile, and that an evaluation circuit is connected to the output of the above-mentioned separate register, which evaluation circuit only when determining an intermediate time value reduced to zero in the separate one in question Register saved intermediate time Output signal (binary signal "H") for the appropriate setting of the associated signal generator. This results in the advantage of low circuitry complexity for generating setting signals for signal transmitters of a traffic signal system and in particular a road traffic signal system, with particularly low circuitry complexity ensuring that only the entry intermediate times of the desired entry signal groups in each case are directly influenced by the respective signal change are taken into account.

The logic arrangement expediently has a first AND gate and a second AND gate. On the output side, the first AND gate emits a specific output signal only when the entry times reduced to zero in those entry signal groups which, together with the entry signal groups marked with regard to the entry times, are hostile to one and the same clearing signal groups. The second AND gate is connected to an input at the output of the first AND gate, and control pulses are fed to the second AND gate at a further input. On the output side, the second AND gate is connected to the control input of the separate register mentioned. In this way, the feed results in the advantage of a particularly low circuit up _'wands in terms of control pulses to the control input of said separate register to which in each case stored Meanwhile, to reduce in value.

• Fig. 1 zeigt eine Kreuzung, in der zur Erläuterung einer Ausführungsform der vorliegenden Erfindung drei Verkehrsflüsse eingetragen sind..
• Fig. 2 zeigt in einem Blockschaltbild eine Schaltungsanordnung gemäß der ersten Ausführungsform der Erfindung.
• Fig. 3 zeigt einen vereinfachten Signalablauf, wie er sich beim Betrieb der in Fig. 2 dargestellten Schaltungsanordnung für die in Fig. 1 gezeigten Kreuzung ergibt.
• Fig. 4 zeigt eine Kreuzung, in der zur Erläuterung einer zweiten Ausführungsform der Erfindung vier Verkehrsflüsse eingetragen sind.
• Fig. 5 zeigt in einem Blockschaltbild eine Schaltungsanordnung gemäß der zweiten Ausführungsform der Erfindung.
• Fig. 6 zeigt einen vereinfachten Signalablauf, wie er sich beim Betrieb der in Fig. 5 dargestellten Schaltungsanordnung für die in Fig. 4 gezeigte Kreuzung ergibt.

The invention is explained in more detail below using two exemplary embodiments with reference to drawings.

• 1 shows an intersection in which three traffic flows are entered to explain an embodiment of the present invention.
• Fig. 2 shows in a block diagram a circuit arrangement according to the first embodiment of the invention.
• FIG. 3 shows a simplified signal sequence as it results from the operation of the circuit arrangement shown in FIG. 2 for the intersection shown in FIG. 1.
• FIG. 4 shows an intersection in which four traffic flows are entered to explain a second embodiment of the invention.
• 5 shows in a block diagram a circuit arrangement according to the second embodiment of the invention.
• FIG. 6 shows a simplified signal sequence as it arises during operation of the circuit arrangement shown in FIG. 5 for the intersection shown in FIG. 4.

The intersection shown in Fig. 1 has four approaches, with respect to which only three traffic flows 1, 2 and 4 are indicated. As can be seen, the two traffic flows 1 and 2 are hostile to the traffic flow 4. To enable or stop the traffic flows 1, 2 and 4 indicated in FIG. 1, these individual signal generators Sg1 or Sg2 or Sg4 are associated. In the case of a traffic intersection, in the simplest case, these signal transmitters may each be green. and contain red signal lamps.

2 shows a circuit arrangement according to a first embodiment of the invention. This circuit arrangement allows the signal generators Sg1, Sg2, Sg4 indicated in FIG. 1 to be controlled in a manner which will become apparent in the following. The circuit arrangement contains, inter alia, an intermediate time matrix ZM which, for example, only belongs to the intersection shown in FIG. 1 and contains information about intermediate times between traffic flows or signal groups which are hostile to one another. For this purpose, so-called entry signal groups Sge are indicated in the top line of the intermediate time matrix ZM - these are signal groups that release their associated traffic flows (i.e. receive green signals). In the left outer column of the intermediate matrix ZM times so-called flush Signalgru are ^p pen Sgr shown - these are (thus obtained red signals) such signal groups, which lock their associated traffic flows. At the intersection of each entry signal group Sge and the respective evacuation signal group Sge, the intermediate time matrix ZM contains an indication of the time after which the respective entry signal group can receive a green signal if the respective evacuation signal group is hostile to it Sgr has received a green end signal. In relation to the numbers entered in the intermediate time matrix ZM, this means that the entry signal group Sge labeled "4" can receive a green signal at this time, for example three seconds after the end of the green of the clearing signal group labeled "1" Sgr is and which is, for example, six seconds after the end of green of the clearing signal group Sgr designated "2".

The intermediate time matrix ZM is connected to an interrogation circuit, which essentially consists of two read circuits Rcl, Rc2. These read circuits Rc1, Rc2 are indicated as circuits containing AND gates GU11 to GU1n and GU21 to GU2n, which are connected with their one inputs to one of two output sides of the intermediate time matrix ZM. The query circuit Rc1 is connected to the cells of the intermediate time matrix ZM designated by the individual clearing signal group Sgr. The interrogation circuit Rc2 is connected with its one input side to the cells of the intermediate time matrix ZM designated by the individual entry signal groups Sge.

The two interrogation circuits Rc1, Rc2 each have their own counter Cnt1 and Cnt2, which can be set by a control device PC. The counter Cnt1 specifies the clearing signal group Sgr by means of its respective counter position, with respect to which information can be read out from the intermediate time matrix ZM by means of the query circuit Rc1. The arrangement can be such that the query circuit Rc1 reads from this matrix all the information entered in relation to a clearing signal group Sgr in the intermediate time matrix ZM, and that the signals or information obtained in this way with the counter setting of the counter Cnt2 be linked in separate AND gates GUr1, GUr2. This then ensures a clear assignment of the information representing the intermediate times of the respective clearing signal group to the hostile entry signal group Sge.

The respective counter position of the counter Cnt2 also determines the entry signal group Sge with which the query circuit Rc2 reads information from the intermediate time matrix ZM. The interrogation circuit Rc2 should be designed such that it only reads out the largest numerical value for each entry signal group Sge from the intermediate time matrix ZM. In the case of the entry signal group Sge denoted by “4”, only the value “6” is thus read out of the intermediate time matrix, ZM by means of the query circuit Rc2. This largest intermediate value, which is decisive for the respective entry signal group, is output by the query circuit Rc2 to a memory cell of a memory Spe which is individually associated with the entry signal group concerned. In the case of the entry signal group labeled "4", the value 6 is stored in a memory cell Sp4e of the memory Spe. For this purpose, the memory Spe in question can be directly connected with its memory cells to corresponding outputs of the query circuit Rc2. At an input denoted by ST, control pulses are supplied to the memory Spe in a fixed cycle of, for example, 1 second, upon the occurrence of which the content of each memory cell of this memory Spe is reduced by a certain value, for example by 1. This will be discussed further below.

Registers Sp1r and Sp2r are connected on the input side to the outputs of the AND gates GUr1 and GUr2 already considered. These registers Sp1r, Sp2r are permanently assigned to the entry signal group labeled "4". This is indicated by a 4 in the right part of the respective register Sp1r, Sp2r. The clearing times representing the clearing times are entered in these two registers, those in the intermediate times matrix ZM with "1" or "2" designated clearance signal groups Sgr in relation to the entry signal group Sge designated "4". Accordingly, the value 3 is entered in the register Sp1r, and the value 6 is entered in the register Sp2r.

Subtractor circuits with their one inputs are connected to the outputs of the two registers last viewed. A subtracting circuit Sub1 is connected to the one input side at the output side of the register Sp1r. A subtrahistor circuit Sub2 is connected to the output side of the register Sp2r with its one input side. With their respective other input side, the subtracting circuits Sub1 and Sub2 are jointly connected to the output of one of the memory cells of the memory Spe. This is the memory cell that belongs to the entry signal group, to which the registers Sp1r, Sp2r connected to the subtracting circuits Subl, Sub2 also belong. In these subtracting circuits Sub1, Sub2, a difference is formed between the time information contained in the memory cell Sp4e of the memory Spe (6 surrounded by a circle) and the time information contained in the registers Splr and Sp2r (in each case framed by a square 3 or 6) .

An evaluation circuit Sw1, Sw2 and Sw4 is connected to the outputs of the subtracting circuits Subl, Sub2 and on the output side of the memory cell Sp4e of the memory Spe. These evaluation circuits may be threshold value circuits, which may emit a binary signal "H" on the output side if an input signal is supplied to them, which is characteristic of a difference value of zero between two subtracted numbers or one reduced to zero Time indication. The relevant evaluation circuits may also output a corresponding binary signal “H” on the output side if the difference signal supplied to them on the input side is characteristic of a negative difference between the numbers subtracted from one another.

The signal switches Sgl, Sg2 and Sg4 already mentioned in connection with FIG. 1 belong to the evaluation circuits Sw1, Sw2, Sw4 just considered. The signal generator Sg1 is on the input side at outputs Q, Q a bistable flip-flop BK1 connected, which is connected directly to a reset input R and to a set input S via a negation element GN1 at the output of the evaluation circuit Sw1. The signal generator Sg2 is on the input side in a corresponding manner at outputs Q, Q A bistable flip-flop BK2 is connected, which is connected directly to a reset input R and to a set input S via a negation element GN2 at the output of the evaluation circuit Sw2. The signal generator Sg4 is finally in a corresponding manner on the input side at the outputs Q, Q a bistable flip-flop BK4 connected, which is connected directly with its set input S and with its reset input R via a negation element GN4 to the output of the evaluation circuit Sw4. The circles in the signal transmitters Sg1, Sg2, Sg4 indicated in FIG. 2 and provided with a horizontal line are intended to indicate the respective basic signal lamp; however, a circle with a vertical line should indicate the red signal lamp in the respective signal transmitter.

After the structure of the circuit arrangement shown in FIG. 2 has been explained above, the mode of operation of this circuit arrangement will now be discussed went. The signal sequence shown in FIG. 3 is also dealt with here, by means of which the mode of operation of the circuit arrangement explained is particularly well illustrated. 3, the control processes to be carried out for the individual signal generators Sg1, Sg2, Sg4 according to FIGS. 1 and 2 are illustrated. A red signal phase is indicated by the thick lines, and a green signal phase is indicated by the thin lines. A green end is indicated by a circle, 'and a red end is indicated by a short vertical line. The transition times red / yellow or yellow are not taken into account in the illustration in question, since these do not appear to be essential for understanding the present invention.

As already explained in connection with the circuit arrangement shown in FIG. 2, the query circuits Rc1 and Rc2 read out time information from the intermediate time matrix ZM and into the respective registers in question, such as the registers Splr, Sp2r, and into a memory cell or a memory section, such as Sp4e, of the memory Spe is stored. This is followed by a subtraction in the subtracting circuits Sub1, Sub2 between the corresponding times. Before going into the related processes, it should be noted that the two bistable flip-flops BK1 and BK2 may be set first, so that the two signal generators Sg1 and Sg2 light up their green signal lamps. It is further assumed that the bistable flip-flop BK4 is initially reset, so that the red signal lamp of the signal generator Sg4 lights up.

Of the two aforementioned subtracting circuits, the subtracting circuit Sub2 immediately establishes the existence of a zero difference between the sub traced numerical values. The evaluation circuit Sw2 then outputs a binary signal “H” on the output side, upon the occurrence of which the bistable flip-flop BK2 is reset. As a result, the green signal lamp of the signal generator Sg2 goes out and the red signal lamp of this signal generator Sg2 lights up instead. This time corresponds to the time t0 in FIG. 3.

Since - as already explained above - the numbers or time values stored in the memory cells of the memory Spe are cyclically successively reduced, for example in a rhythm of one second, the subtracting circuit Sub1 will successively form a smaller and smaller difference between the time values subtracted from each other. The value of the time values stored in the memory cells of the memory S ^p e is reduced in rhythm. of one second each by the value 1, the subtracting circuit Sub1 will also determine the existence of a zero difference between the time values subtracted from one another after three seconds from the aforementioned time t0. The evaluation circuit Sw1 then outputs a binary signal "H", which leads to the resetting of the bistable flip-flop BK1. The green signal lamp of the signal generator Sg1 then goes out and the red signal lamp of this signal generator Sg1 now lights up. This time corresponds to time t3 according to FIG. 3.

Is the in the respective memory cell, such as the memory cell Sp4e; time value of the memory Spe is reduced to zero - which will be the case in the case of the memory cell Sp4e after six seconds - at this time the evaluation circuit Sw4 connected to this memory cell outputs a binary output signal "H". Upon the occurrence of this binary signal "H", the bistable flip-flop BK4 is set, as a result of which the red signal lamp which was lit up to this point in the signal transmitter Sg4 goes out, and instead the green signal lamp of this signal transmitter Sg4 lights up. This time corresponds to time t6 according to FIG. 3.

As already mentioned above, the two counters Cnt1, Cnt2 of the circuit arrangement shown in FIG. 2 are connected to the output of a control device PC. The two counters receive their counter setting signals from this control device PC. The delivery of these counter setting signals will take place in accordance with the overall signal plan to be processed, with respect to which the required intermediate times between the individual signal groups hostile to one another are contained in the intermediate times matrix ZM. The control device PC therefore only needs corresponding times at the time t0 according to FIG. 3 set the two counters Cnt1, Cnt2. For this purpose, the control device PC can contain information about the required meter settings (these are the meter setting signals) in a correspondingly defined schedule. In this case, the relevant control device PC will provide the corresponding information in good time.

3 shows that only the signal generator Sg2 receives an end of green signal at the time t0, so that it lights up its red signal lamp from the time t0. At this time, the signal generator Sg1 still lights up its green signal lamp, while the signal generator Sg4 still lights up its red signal lamp. At the time t3 - which may be three seconds after the time t0 - the signal generator Sg1 then also receives a green end signal, whereupon this signal generator Sg1 lights up its red signal lamp. The signal generator Sg4 continues to light up its red signal lamp. Only at time t6 - which may be six seconds after time t0 - does the signal generator Sg4 receive a rotating end signal, whereupon this signal generator Sg4 lights up its green signal lamp. With reference to the conditions indicated in FIG. 1, it thus follows that traffic flows 1 and 2, which are hostile to traffic flow 4, first stop traffic flow 2 and only then traffic flow 1 is stopped. This means that the traffic flow 2 has a longer clearing time than the traffic flow 1 in relation to the release of the traffic flow 4. Such a different stopping of the traffic flows 1, 2 with respect to the release of the traffic flow 4 can thus optimally do justice to actual conditions.

The intersection shown in FIG. 4 has four approaches, with respect to which only four traffic flows 1, 2, 4 and 5 are indicated. As can be seen, the two traffic flows 1 and 2 are hostile to the two traffic flows 4 and 5. To enable or stop the traffic flows 1, 2, 4 and 5 indicated in FIG. 1, these individual signal generators Sg1, Sg2, Sg4 and Sg5 are associated. In the case of a traffic intersection, these signal transmitters may contain green and red signal lamps in the simplest case.

5 shows a circuit arrangement according to a second embodiment of the invention. This circuit arrangement, which essentially corresponds to the circuit arrangement shown in FIG. 1, allows the signal generators Sg1, Sg2, Sg4 and Sg5 indicated in FIG. 4 to be controlled in a manner which will be explained in more detail below. The circuit arrangement in question contains, inter alia, an intermediate time matrix ZM, which, for example, only belongs to the intersection shown in FIG. 4 and contains information about intermediate times between traffic flows or signal groups which are hostile to one another. For this purpose, so-called entry signal groups Sge are indicated in the top line of the intermediate time matrix ZM - these are signal groups which release their associated traffic flows (ie receive green signals). So-called clearing signal groups Sgr are listed in the left outer column of the intermediate time matrix ZM - these are those signal groups that represent their associated traffic flows block (i.e. receive red signals). At the intersection of each entry signal group Sge and the respective evacuation signal group Sgr, the intermediate time matrix ZM contains information about the time after which the respective entry signal group can receive a green signal if the evacuation signal group hostile to it Sgr has received a green end signal. In relation to the numbers entered in the intermediate time matrix ZM, this means that the entry signal group Sge labeled "4" can receive a green signal at a point in time which is, for example, three seconds after the end of greening of the clearing signal group Sgr labeled "1" and which is, for example, six seconds after the end of green of the clearing signal group Sgr designated "2". In contrast, the entry signal group Sge designated "5" is to receive a green signal at a time which is eight seconds after the end of green of the two clearing signal groups Sgr1 and Sgr2.

The intermediate time matrix ZM is connected to an interrogation circuit, which essentially consists of two read circuits Rc1, Rc2. These read circuits Rcl, Rc2 are indicated as circuits containing AND gates GU11 to GU1n and GU21 to GU2n, which are connected with their one inputs to one of two output sides of the intermediate time matrix ZM. The interrogation circuit Rc1 is connected to the cells of the intermediate time matrix ZM denoted by the individual room signal groups Sgr. The interrogation circuit Rc2 is connected with its one input side to the cells of the intermediate time matrix ZM designated by the individual entry signal groups Sge.

The two query circuits Rc1, Rc2 each have their own, which can be set by a control device PC Counter Cnt1 or Cnt2 associated. The counter Cnt1 determines the clearing signal group Sgr by means of its respective counter position, with respect to which information can be read out from the intermediate time matrix ZM by means of the query circuit Rc1. The arrangement can be such that, by means of the query circuit Rc1, all the data from this matrix that has been entered in the intermediate time matrix ZM with respect to a clearing signal group Sgr. are read out and that the signals or data obtained in this way are linked to the counter position of the counter Cnt2 in separate AND gates GUr1, GUr2. This then ensures a clear assignment of the details of the respective clearing signal group representing the intermediate times to the egg signaling group Sge which is hostile to it.

The respective counter position of the counter Cnt2 also determines the entry signal group Sge with which the interrogation circuit Rc2 reads out information from the intermediate times matrix ZM. The interrogation circuit Rc2 should be designed such that it only reads out the largest numerical value for each entry signal group Sge from the intermediate time matrix ZM. In the case of the entry signal group Sge denoted by “4”, only the value “6” is thus read out of the intermediate time matrix ZM by means of the query circuit Rc2. With regard to the entry signal group "5" - which may be a pedestrian signal group - the value "8" is read out of the split time matrix ZM by means of the query circuit Rc2. These intermediate time values which are decisive for the respective entry signal group are output by the query circuit Rc2 to a memory or register cell of a memory Spe which is individually associated with the respective entry signal group. In the case of the entry signal group Sge4, the value 6 is stored in a memory or register cell Sp4e of the memory Spe. In the case of the entry signal group Sge5, the value 8 is stored in a separate register cell Sp5e of the memory Spe. For this purpose, the memory Spe in question can be directly connected with its memory cells to corresponding outputs of the query circuit Rc2. At an input denoted by ST, control pulses are supplied to the memory Spe in a fixed cycle of, for example, 1 second, upon the occurrence of which the content of those memory cells of this memory Spe is reduced by a certain value, for example by 1, associated with the relevant input ST In the present case, this applies to the memory or register cell Sp4e, but not to the memory or register cell Sp5e. This last-mentioned register cell Sp5e receives corresponding control pulses via an AND gate GU2e, which will be discussed below.

Registers Sp1t and Sp2t are connected on the input side to the outputs of the previously considered AND elements.GUr1 and GUr2. These registers Splt, Sp2t are permanently assigned to the entry signal group labeled "4". This is indicated by a 4 in the right part of the respective register Sp1t, Sp2t. In these two registers, the clearing times representing the clearing times are entered, which are those in the Intermediate time matrix ZM with "1" or "2" designated clearing signal groups Sgr with respect to the entry signal group Sge labeled "4". Accordingly, the value 3 is entered in the register Sp1t, and the value 6 is entered in the register Sp2t.

Subtractor circuits Sub1 and Sub2 with their one inputs are connected to the outputs of the two registers last viewed. For example, a subtractor circuit Sub1 with its one is on the output side of the register Sp1t an input side connected. At the output side of the register Sp2t, a subtraction circuit Sub2 is connected with its one input side. With their respective other input side, the subtracting circuits Sub1 and Sub2 are jointly connected to the output of one of the memory cells of the memory Spe. It is about. around the memory cell that belongs to the entry signal group, to which the registers Sp1t, · Sp2t connected to the subtracting circuits Sub1, Sub2 also belong. In these switching circuits Subl, Sub2, a difference is formed between the time information contained in the memory cell Sp4e of the memory Spe (given by a circle 6) and the time information contained in the registers Sp1t or Sp2t (time information 3. or 6 framed by a square) ).

An evaluation circuit Sw1, Sw2 or Sw4 is connected to the outputs of the subtracting circuits Subl, Sub2 and to the output side of the memory cell Sp4e of the memory Spe. These evaluation circuits may be threshold value circuits which emit a binary signal "H" on the output side when they are supplied with an input signal which is characteristic of a difference value of zero between two numbers subtracted from one another or for a time specification reduced to zero. The relevant evaluation circuits may also output a corresponding binary signal “H” on the output side if the difference signal supplied to them on the input side is characteristic of a negative difference between the numbers subtracted from one another.

The signal circuits Sg1, Sg2 and Sg4 already mentioned in connection with FIG. 4 belong to the evaluation circuits Sw1, Sw2, Sw4 just considered. The signal generator Sg1 is on the input side at the connections Q, Q one bistable flip-flop BK1 connected, which is connected with a reset input R directly and with a set input S via a negation element GN1 at the output of the evaluation circuit Sw1. The signal generator Sg2 is on the input side in a corresponding manner at outputs Q, Q a bistable flip-flop BK2 connected. sen, which is connected directly to a reset input R and to a set input S via a negation element GN2 at the output of the evaluation circuit Sw2. The signal generator Sg4 is finally connected in a corresponding manner on the input side to the outputs Q, Q of a bistable flip-flop BK4, which is connected with its set input S directly and with its reset input R via a negation element GN4 to the output of the evaluation circuit Sw4. The circles in the signal transmitters Sg1, Sg2, Sg4 and Sg5 indicated in FIG. 5 and provided with a horizontal line are intended to indicate the respective green signal lamp; a circle with a vertical line should indicate the red signal lamp in the respective signal transmitter.

In addition to the circuit elements explained above, an AND element GU1e is also provided in the circuit arrangement shown in FIG. 5, which forms a linkage arrangement together with the AND element GU2e already mentioned above. The inputs of the AND gate GU1e are connected to the outputs of the two evaluation circuits Sw1 and Sw2. With its output, the AND gate GU1e is connected to an input of the AND gate GU2e. This AND gate GU2e is connected to a further input at the switching point ST, to which control pulses are supplied. On the output side, the AND gate GU2e emits the control pulses supplied to it from the switching point ST in the event that it is capable of transmission. This output from the output of the AND gate GU2e These control pulses serve to successively reduce the value of the register cell Sp5e.

At the output of the register cell Sp5e of the memory Spe, an evaluation circuit Sw5 is connected, which may be designed in a manner corresponding to the other evaluation circuits Sw1, Sw2, Sw4 previously mentioned. At the output of this evaluation circuit Sw5, another bistable flip-flop BK5 with its set input S is connected directly and with its reset input R via a negation element GN5. At the outputs Q, Q This bistable flip-flop BK5 is connected to the signal generator Sg5.

The mode of operation of the circuit arrangement shown in FIG. 5 is explained in more detail below. The signal sequence shown in FIG. 6 is also discussed, by which the mode of operation of the circuit arrangement in question is particularly well illustrated. 6, the control processes to be carried out for the individual signal generators Sgl, Sg2, Sg4 and Sg5 according to FIGS. 4 and 5 are illustrated. A red signal phase is indicated by the thick lines, and a green signal phase is indicated by the thin lines. A green end is indicated by a circle, and a red end is indicated by a short vertical line. The transition times red / yellow or yellow are not taken into account in the illustration in question, since these are not essential here for understanding the invention.

As already explained in connection with the circuit arrangement shown in FIG. 5, the query circuits Rc1 and Rc2 read out time information from the intermediate times matrix ZM and into the relevant registers, such as the registers Sp1t, Sp2t, and in corresponding memory or register cells, such as Sp4e and Sp5e of memory Spe stored. This is followed by a subtraction in the subtracting circuits Sub1, Sub2 between the time information stored in the registers Sp1t and Sp2t. There is no need to go into the related processes here, since these processes have already been explained in detail in the main patent.

In contrast to the circuit arrangement shown in FIG. 2, however, the intermediate times of all entry signal groups which are hostile to one and the same clearing signal groups are not taken into account in the present circuit arrangement for influencing or determining a signal change. Rather, in the present case, the intermediate times of selected entry signal groups are disregarded by marking the relevant intermediate times separately. In the circumstances indicated in FIG. 5, the run-in split time of the run-in signal group Sge5 is such a marked split time. This intermediate time "8" has been stored in the intermediate times matrix ZM in the register Sp5e. In this separate register, this intermediate time "8" remains unchanged as a kind of marked intermediate time until the run-in intermediate times 3 and 6 of the run-in signal group Sge4 have expired, which is also hostile in relation to the clearing signal groups Sgr1 and Sgr2 like the entry signal group Sge5. Only when these intermediate times of the entry signal group Sge4 in relation to the clearing signal groups Sgr1 and Sgr2 have elapsed, does the AND gate GU1e provided in the circuit arrangement according to FIG. 5 emit a specific output signal (binary signal 'H') on the output side, on the latter If the control pulses occurring at the switching point ST occur via the AND gate GU2e, the value of the register Sp5e of the memory Spe is reduced.

If the content or intermediate value of the register Sp5e is reduced to zero, the evaluation circuit Sw5 outputs a binary signal "H" on the output side, by means of which the bistable flip-flop BK5 is set, so that the signal generator Sg5 lights up its green signal lamp. It is assumed that the signal generator Sg5 as well as the signal generator Sg4 are initially reset so that the red signal lamps of these signal generators first light up.

With regard to the entry signal group Sge5 indicated in the intermediate time matrix ZM according to FIG. 5, the following should also be noted. As previously explained, regarding this. Entry signal group Sge5 in the separate register Sp5e only a time 8 has been stored. This time indication is generally the largest time indication or intermediate time that is contained in the intermediate time matrix ZM for such a drive-in signal group in relation to all the evacuation signal groups that are hostile to it.

In order to emphasize the importance of the present Aasfahrangsform compared to the method used in Fig. 2 and compared to the circuit arrangement shown in Fig. 2, the diagram shown in Fig. 6 will now be discussed in more detail. It can be seen from the signal sequence shown in FIG. 6 that only the signal generator Sg2 receives a green end signal at the time t0, so that it lights up its red signal lamp from the time t0. At this time, the signal generator Sg1 still lights up its green signal lamp, while the signal generators Sg4 and'Sg5 still light up their red signal lamps. At the time t3 - which may be three seconds after the time t0 - the signal generator Sg1 then also receives a green end signal, whereupon this signal generator Sg1 lights up its red signal lamp. The signal encoders Ng4 and Ng5 continue to light up their red signal lamps. Only at time t6 - which may be six seconds after time t0 - does signal generator Sg4 receive a rotating end signal, whereupon this signal generator Sg4 lights up its green signal lamp. In relation to the traffic conditions indicated in FIG. 4, in the present case, as in the mode of operation explained for FIG. 2, it follows that traffic flows 1 and 2, which are hostile to traffic flow 4, first stop traffic flow 2 and only then traffic flow 1 is stopped. The signal generator Sg5 - as this should have become apparent - did not influence the signal change explained. The signal generator Sg5 lights up its red signal lamp until time t11. This point in time t11 is eight seconds after the point in time t3, that is the point in time from which, in the circuit arrangement according to FIG. 5, the AND gate GU1e outputs a binary signal “H” on the output side. From this point in time t3, the intermediate time information 8 contained in the register Sp5e - is gradually reduced to 0. Since in the present case this takes place every second, the signal generator Sg5 only switches on its green signal lamp eight seconds after the time t3, that is to say at the time t11. Due to the different stopping of the traffic flows 1 and 2 in relation to the release of the traffic flows 4 and 5, actual conditions can thus be optimally taken into account, while at the same time selectively the intermediate times of the entry points to be taken into account for determining or influencing the respective signal change. Signal groups can be selected. In other words, this means that the intermediate times of selected entry signal groups can be selectively disregarded in a corresponding manner. Such an intermediate period that has not been taken into account is the intermediate one Time 8 of the entry signal group 5 entered in the intermediate times matrix M according to FIG. 5. With regard to this entry signal group 5, it should also be noted that their entry intermediate time of eight seconds in the present case is maintained only in relation to the enemy clearing signal group Sg1 is, while there is a longer intermediate time to the enemy signal group Sg2 than required by the intermediate times matrix M. However, this is accepted in the present case, since the procedure described ensures that the entry signal group Sge5, because of its relatively long meantime, cannot prematurely terminate the clearing signal groups Sgr1 and Sgr2, which are hostile to it, in the event that this Clear signal groups still - each have a green signal.

In order to further clarify the last-mentioned processes, the following briefly considers the case in which the run-in signal group Sge5 is taken into account in deviation from the conditions previously explained and provided according to the present invention in the manner as explained for FIG. 2 has been. In this case, the intermediate time of eight seconds would be the largest entry intermediate time, which would then be processed with the remaining intermediate times of the intermediate time matrix in the manner explained for FIG. 2. The consequence of this would be that traffic flows 1 and 2 would be stopped immediately and traffic flows 4 and 5 would be released eight seconds later. However, such regulation of traffic flows can sometimes be undesirable, as has already been explained above. Accordingly, in the present embodiment, the intermediate times of certain selected entry signal groups are marked in the manner explained above. This marking can now also deviate from the conditions explained so that in the Marking information corresponding to the intermediate times matrix is included, which, when the associated intermediate times are read out, effect their corresponding treatment.

The following should be noted regarding the circuit arrangement shown in FIG. 5. The two counters Cnt1 and Cnt2 of the relevant circuit arrangement receive counter setting signals from the control device PC. The delivery of these counter setting signals will take place in accordance with the overall signal plan to be processed, with respect to which the required intermediate times between the individual signal groups which are hostile to one another are contained in the intermediate times matrix ZM. The control device PC therefore only needs to set the two counters Cnt1, Cnt2 at the points in time corresponding to FIG. 6. For this purpose, the control device PC can contain information about the required meter settings (these are the relevant meter setting signals) in a correspondingly defined schedule. In this case, the control device PC will provide the corresponding information in good time. This can be done in such a way that all the details of the intermediate time matrix ZM are read out in a rhythm of one second, as is also the case with the circuit arrangement according to FIG. 2.

Finally, it should also be noted that the circuit arrangements explained in connection with FIGS. 2 and 5 can now not only be implemented using discrete circuit technology, but that these circuit arrangements can also be constructed using a microcomputer system using at least one microprocessor.

Claims (9)

1. A method for generating setting signals for signal transmitters of a traffic signal system, in particular a road traffic signal system, using information contained in an intermediate times matrix of intermediate times between mutually hostile 'traffic flows, characterized in that from the intermediate times matrix (ZM) for each signal group as an entry signal group (Sge-4) which issues an enable setting signal to at least one traffic flow. Entry intermediate times (3, 6) with respect to those signal groups representing clearing signal groups (Sgr-1,2) are read out and stored separately, which are used to control traffic flows which are related to those by the respective entry signal group (S 4) controlled traffic flows are hostile, that in addition the largest entry intermediate time (6) for the respective entry signal group (Sge-4) is stored separately and is cyclically successively reduced in its value to zero, that of that for the respective entry -Signal group (Sge-4) stored largest and cyclically successively reduced entry intermediate time (6), the remaining entry intermediate times (3,6) stored for the same entry signal group (Sge-4) are separately subtracted so that when they occur a lock setting signal for that clearing signal group (Sg2 or Sg1) is emitted on a zero difference between two such subtracted entry intermediate times which is related to a run-in intermediate time used in the relevant difference formation, and that after the original largest run-in intermediate time (6) has been reduced to zero, the relevant associated run-in signal group (Sge-4) is supplied with a release setting signal. 2. The method according to claim 1, characterized in that the largest entry-intermediate. value (6) for the respective entry signal group (Sge-4) is reduced every 1 sec. 3. The method according to claim 1 or 2, characterized in that from the intermediate times matrix (ZM) read out and separately stored entry intermediate times of those entry signal groups which are hostile to one and the same clearing signal groups, the intermediate times (8 ) of the entry signal groups (Sge5), which are selected as being unimportant for influencing a signal change, are initially retained unchanged in their value by separate marking and are only made effective in order to reduce their value if the unmarked entry intermediate times (3, 6 ) the entry signal groups (Sge4) which are hostile to the same clearing signal groups (Sgr1, Sgr2) have expired, and that after the respective marked entry intermediate time (8) has been reduced to zero the relevant associated entry signal group (Sge5) Setting signal (binary signal "H") is supplied. 4. The method according to claim 3, characterized in that of the one entry signal group (Sge5) associated marked entry intermediate times (8) only the largest E3.nfahr intermediate time for generating an enable setting signal (binary signal "H") for the relevant entry signal group (Sge5) is used. 5. The method according to claim 3 or 4, characterized in that the largest unmarked run-in intermediate time (6) and the respectively made marked run-in intermediate time (8) are reduced in value in a rhythm of 1 sec. 6. Circuit arrangement for carrying out the method according to one of claims 1 to 5, characterized in that a query circuit (Rcl, Rc2) is connected to the intermediate times matrix (ZM), the intermediate times of all of the intermediate times matrix (ZM), Read-in signal groups (Sge) to the hostile clearing signal groups (Sgr) and registers (Sp1r, Sp2r) and the largest intermediate time (6) of these intermediate times in the respective entry-signal groups (eg Sge-4) in a separate, stores the memory (Spe) belonging to the relevant entry signal group (Sge-4), in which the relevant intermediate time (6) can be reduced in value to zero in successive control cycles that the registers (Sp1r, Sp2r) and the memory (Spe) Subtractor circuits (Subl, -Sub2) are subordinate, the difference between the intermediate value (6), which is contained in the memory associated with the respective entry signal group (Sge-4) (Sp4e in Spe), and de n in the associated registers (Sp1r; Sp2r) contain intermediate times (3, 6), and that the difference values formed with respect to each entry signal group (Sge-4) and the intermediate time value contained in the associated memory (Sp4e in Spe) can be evaluated by means of evaluation circuits (Sw1, Sw2, Sw4) are which, when determining a difference value of zero or an intermediate time value reduced to zero, emit an output signal (binary signal "H") for the corresponding setting of the associated signal generators (Sg1, Sg2, Sg4). 7. Circuit arrangement according to claim 6, characterized in that the query circuit (Rc1, Rc2) is controlled by counters (Cntl, Cnt2), one of which denotes entry signal groups (Sge) through its counter positions and the other of which through its counter positions indicates the respective entry Signal group enemy clearance signal groups (Sgr), and that the counters (Cnt1, Cnt2) are adjustable by a control device (PC). 8. Circuit arrangement according to Claim 6 or 7, characterized in that the intermediate times (8) of entry signal groups (Sge5), selected as immaterial for influencing a signal change, of the entry intermediate times (Sge4, Sge5) read out from the intermediate times matrix (ZM) ) can be saved as marked intermediate entry times in a separate register (Sp5e), which receives control impulses with a control input that reduce the value of its saved intermediate time from a linkage arrangement (GU2e, GU1e) only in the event that the intermediate entry times ( 3, 6) of those entry signal groups (Sge4) are reduced to zero that. together with the entry signal groups (Sge5) marked with respect to the entry intermediate times (8) are hostile to the same clearing signal groups (Sgr1, Sgr2), and that an evaluation circuit (Sw5) is connected to the output of the said separate register (Sp5e) , which outputs an output signal (binary signal "H") for the corresponding setting of the associated signal generator (Sg5) when determining an intermediate time value reduced to zero of the intermediate time stored in the relevant separate register (Sp5e). 9. Circuit arrangement according to claim 8, characterized in that the logic arrangement has a first AND gate (GU1e) and a second AND gate (GU2e), that the first AND gate (GU1e) on the output side a certain output signal (binary signal "H" ) only when the intermediate entry times (3, 6) of those entry signal groups (Sge4) are reduced to zero emits that are hostile to the same clearing signal groups (Sgr1, Sgr2) 'together with the entry signal groups (Sge5) marked with regard to the entry intermediate times (8), and that the second AND gate (GU2e) has one input is connected to the output of the first AND gate (GU1e) and receives control pulses (ST) fed to a further input and is connected on the output side to the control input of the said separate register (Sp5e).

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