DE2657281C3 - MIS inverter circuit - Google Patents

Description

Known MIS inverter circuits have the disadvantage that at certain levels of the input voltage a state of equilibrium can develop in which the output voltage is in the undefined range between the logical "0" and the logical "1". at In this state of equilibrium, no recharging current flows to the node capacities. Also in the vicinity of the In the state of equilibrium, the charge reversal currents are very small, so that this critical area is relatively slow is left.

The invention is concerned with an MIS inverter circuit clocked with respect to a two-phase clock system, i.e. with an inverter circuit whose logic state only occurs during the two clock pulses of the clock system is to change according to a logical input signal.

In integrated circuits or in circuit systems with such circuits, however, there is the problem that the input pulse can only be determined with difficulty in terms of its edge steepness and its phase relation to the clock signals of the clock system, which can be attributed, for example, to signal propagation times.
The invention relates to an MIS inverter circuit for generating a pulse synchronized with respect to a two-phase clock system from an input pulse according to the preamble of claim 1. Such an MIS inverter circuit was known from DE-OS 23 15 201. In this MIS inverter circuit, the lead electrode is fifth MIS field effect transistor connected to the power supply via a load transistor. The fifth MIS field effect transistor and the load transistor represent an inverter. The output of this inverter is connected to the gate electrode of the second MIS field effect transistor via the source-drain path of an MIS field effect transistor controlled by the second clock signal.
The object of the invention is a comparatively faster MIS inverter circuit with less circuit complexity for generating a pulse that is synchronized with respect to a two-phase clock system from an input pulse whose edge steepness and phase relation to the clock system is arbitrary

This object is achieved according to the invention by what is stated in the characterizing part of claim 1 Circuit measures solved

The MIS inverter circuit according to the invention also has the advantage over the known that at

jo of the former a quasi-stable state of equilibrium is avoided, which can then develop when the voltage at the gate electrode of the second MIS field effect transistor of the series circuit is approximately equal to the voltage at its connection point.

The MIS inverter circuit according to the invention is explained below with reference to the drawing, whose

F i g. 1 shows the basic circuit of an MIS inverter circuit on which the invention is based, whose

F i g. 2 to 4 modifications of the MIS inverter circuit according to FIG. 1 concern whose

F i g. 5 shows the circuit arrangement of a first embodiment of the MIS inverter circuit according to the invention, whose

F i g. 6 shows the circuit arrangement of a second embodiment of the MIS inverter circuit according to the invention, the
F i g. 7 the circuit arrangement of a third embodiment

5 (i approximate form of the MIS inverter circuit according to the invention show and their

8 serves to explain the mode of operation of the MIS inverter circuit according to the invention.
The circuit arrangement according to FIG. 1 shows a known clocked inverter with the two MIS field effect transistors Γ2 and Γ3 connected in series via the source-drain paths. To the gate electrode of the second MIS field effect transistor Tl, whose source electrode is at the reference potential

Wi Uss or ground, the input signal at f is applied via the source-drain path of a first MIS field effect transistor Ti. The first clock signal Φ 1 is applied to the gate electrode of this first MIS field effect transistor Ti. With the voltage source Udd

<v> both the drain electrode and the gate electrode of the second MIS field effect transistor Γ3 of the series circuit, which acts as a load transistor. That second clock signal Φ 2 receives the gate electrode of the

fourth MIS field effect transistor 74, the source-drain path of which lies between the common connection point of the two MIS field effect traiisitors 72 and 3 forming the series circuit and output A CI means the output capacitance of the clocked MIS inverter circuit.

At any ratio of the /} values of the two MIS field effect transistors 72 and 73

where is the source-drain current

= fiUe-υ, ύ

¹⁰

15th

is, there is a Ug at the gate electrode of the MIS field effect transistor 72 in which there is a steady-state case with Ua = Ug , ie a case with a negligible capacitor charging current ic- Here, i \ - h, which currents in the F i G. 1 are registered. This state is only longitudinal? m can be left in accordance with an input signal Ue . The MIS inverter circuit according to the invention provides a remedy here.

Instead of the between the dashed lines 1 and 2 of FIG. 1, MIS inverter circuit parts shown in FIGS. 2 to 4 can also be used in the MIS inverter circuit according to the invention with certain advantages. While in the inverter stage according to FIG. 3, the second clock signal Φ 2 you still lies to the gate electrode of lying on the supply voltage Udo third MIS field effect transistor, wherein the circuit arrangement of Figure 2, a further MIS field effect transistor 76, J5 has its gate electrode connected to the voltage supply Udo Hegt, inserted between the third MIS field effect transistor 73

The F i g. 4 shows an MIS inverter circuit part with a complementary pair of MIS field effect transistors T2 and 73, at whose common connection point there is a transmission gate with two MIS field effect transistors 77 and 78 connected in parallel, to whose gate electrodes the second clock signal Φ 2 is applied.

In the first embodiment of the MIS inverter circuit according to the invention according to FIG. 5, in which the MIS inverter circuit of FIG. 1 is assumed, the common connection point of the two MIS field effect transistors 72 and 73 is connected to the gate electrode of a fifth MIS field effect transistor T5 , the source-drain path of which is between the gate electrode of the second MIS field effect transistor 72 of the series circuit 72 and 73 and the reference potential Uss. Through this fifth MIS field effect transistor 75, which acts as a discharge transistor at the gate of the second MIS field effect transistor, the MIS inverter circuit according to FIG. 1 a preferred position.

If used with a subsequent bo digital differentiating switching T.g.; '?> d following conditions to be observed:

a) The output resistance of the inverter G1 connected to the input E must be so small that, in spite of the conductive MIS field effect transistor 75, the MIS field effect transistor 72 receives an input voltage which is high enough to enable it to be switched through.

b) The circuit part consisting of the MIS field effect transistors 72, 73, 74 and 75 must be fast be designed enough so that it reaches the final state of the logical "0" within the clock pulse duration or a logical "1"

The MIS inverter circuit according to the invention as shown in FIG. 5 can be modified using the MIS · Invertei circuit parts shown in FIGS. The output inverter G 2 controlled by the clock signal Φ 1 is connected to the output A

In the circuit arrangement according to FIG. 5, an inverter G 1 with a low output resistance is required according to the above condition a). This disadvantage is in the circuit arrangement according to FIG. 6 by inserting an MIS field effect transistor 76, to the gate electrode of which the clock signal Φ 2 is applied, in series connection with the fifth MIS field effect transistor TS . This enables the use of a simple standard low-power inverter for the inverter Gl, since no charge can flow away while the MIS field effect transistor 71 located between the inverter Gl and the gate electrode of the second MIS field effect transistor 72 is conductive The positive feedback caused by the MIS inverter circuit according to the invention therefore only becomes effective when the MIS field effect transistor 76 is conductive

In the embodiment according to FIG. 7 of an MIS inverter circuit according to the invention are FIGS Gate electrodes of the two MIS field effect transistors 72 and 73 of the inverter circuit part via the Inverter G 3 connected. This has the advantage that the fifth MIS field effect transistor 75 achieved The positive feedback effect is the quickest. This inverter G 3 is preferably in the form of a Series connection of two further MIS field effect transistors realized in the usual way

Although in the circuit arrangement according to FIG. 6, a relatively high-resistance inverter G1 can be used at input E , is an MIS inverter circuit according to FIG. 5 faster, since the positive feedback effect of the circuit with the MIS field effect transistors 72, 73 and 75 starts at the beginning of the clock signal Φ 1

To explain the positive feedback achieved in the MIS inverter circuit according to the invention, FIG. 8 the two clock signals Φ 1 and Φ 2 of the clock system plotted in chronological order. Underneath, an input signal Ue with a relatively low edge steepness is shown, the leading edge of which still falls within the clock range of the clock signal Φ 1 so that a signal occurs at the gate electrode of the MIS field effect transistor 72. As a result, the potential at the common connection point of the two MIS field effect transistors 72 and 73 is indeed lowered. From the gate electrode E 'of the MIS field effect transistor 72, the charge that was still applied during the clock pulse Φ1 in the rising part of the input signal Ue can flow away again, so that an output signal Ua with an unambiguous logic "0" according to FIG. 8 adjusts until the next pulse of the clock pulse signal Φ 1 occurs.

Because of this behavior, an MIS inverter circuit according to the invention is of particular advantage in digital differentiating circuits, since the edge of an input signal Ue in the “gray area” between a logical “0” and a logical “1” is not differentiated.

The MIS inverter circuit according to the invention can be used in any for the production of MIS integrated circuits suitable technology, the MOS, the CMOS or the silicon gate technology.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. MIS inverter circuit for generating a pulse synchronized with respect to a two-phase clock system from an input pulse which is applied to the gate electrode of a second via the source-drain path of a first MIS field-effect transistor, whose gate electrode is the first clock signal the reference potential lying MIS field effect transistor of the series connection of at least two MIS field effect transistors of an MIS inverter circuit part, in which the synchronized pulse at the common connection point of the two MIS field effect transistors via the source-drain path of a fourth MIS field effect transistor, at the gate Electrode the second clock signal is tapped, the common connection point via a fifth MIS field effect transistor, whose source-drain path connects the gate electrode of the second MIS field effect transistor to the reference potential and whose gate electrode is connected to the connection point, on the gate electrode of the second MIS field effect transistor is fed back, and the voltage is supplied via a third MIS field effect transistor of the series circuit, characterized in that one of the two lead electrodes of the drain-source path of the fifth MIS field effect transistor (TS) is connected directly to the gate electrode of the second MIS field effect transistor (T2) is connected 2. MIS inverter circuit according to claim 1, characterized in that a sixth MIS field effect transistor (TS) is connected in the source-drain series circuit to the fifth MIS field effect transistor (TS) , the source electrode of which is at the reference potential (Uss) and harbors the clock signal Φ 2 is applied to its gate electrode. 3. MIS inverter circuit according to claim 1 and / or 2, characterized in that the gate electrodes of the two MIS field effect transistors (T2 and Γ3) of the series circuit of the inverter circuit part are connected via an inverter (G 3).