CN119545798A - Erasing method of flash memory unit - Google Patents

Abstract

The present disclosure provides a method of erasing a flash memory cell. The flash memory cell includes a memory transistor and a gate transistor connected in series. The erase method according to the present disclosure includes applying respective erase voltages to respective electrodes of the flash memory cells and gate electrodes of the respective transistors, wherein the erase voltage applied to the gate electrodes of the erased memory transistors is lower than a second power supply voltage, so that channel hot electrons induce a thermal hole injection physical effect to attract hot holes in the channel into the memory medium layer to effect erase. The erase method of the flash memory cell of the present disclosure has a wider hole distribution and higher injection efficiency than the existing erase method with tunneling hot holes (BBHH), so that the erase method according to the present disclosure has higher erase speed, larger erase window, smaller hot carrier damage, lower leakage current, and higher endurance reliability.

Description

Erasing method of flash memory unit

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method of erasing a flash memory cell.

Background

Flash memory, abbreviated as flash memory, is a non-volatile memory, i.e. the stored data will not be lost even if the power is turned off, and is especially suitable for the fields of mobile communication and computer storage parts. In addition, some flash memories also have high density storage capability, and are suitable for applications such as mass storage media.

Conventional flash memories employ a floating gate type cell structure. The floating gate type nonvolatile memory originates from MIMIS (Metal-Insulator-Semiconductor) structure proposed by d.kahng and s.sze in 1967. The structure is formed by adding a Metal floating gate and an ultrathin tunneling Oxide layer on the basis of a traditional MOSFET (Metal-Oxide-Semiconductor FIELD EFFECT Transistor) so as to store charges by using the Metal floating gate. Based on this, masuoka et al, in 1984, first proposed the concept of Flash Memory (Flash Memory), i.e., to achieve high-speed erase capability by block-wise erase/write (programming), and to eliminate the select tube necessary in EEPROM (Erasable Programmable Read-only Memory) to have a smaller Memory cell size. After the advent of flash memory, it has been rapidly developed with its high writing speed, high integration, and superior performance. Intel corporation proposed an ETOX structure flash memory cell (ETOX: electron Tunneling Oxide device, electron tunneling oxide device) in 1988, which became the basis for the development of most floating gate type flash memory cell structures so far.

However, the floating gate type flash memory has the disadvantages of complicated process, adverse scaling down of process size and cell area due to the increased longitudinal height of the gate structure due to the existence of the floating gate structure in the flash memory cell, and adverse improvement of reliability of the memory due to free movement of stored charges in the floating gate due to the conductivity of the floating gate. In order to solve the problems of complicated process, poor reliability and the like of the floating gate type flash Memory, researchers have proposed a Charge trapping Memory (CTM: charge-Trapping-Memory), also called SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon: silicon-Oxide-Nitride-Oxide-Silicon) flash Memory, which stores charges by using a Silicon Nitride medium. Based on this, eitan et al proposed a two-bit Memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, which uses the non-conductive property of an insulating silicon Nitride Memory medium to realize two Memory bits at the source and drain terminals of a Memory transistor, but the cell structure has the disadvantages that the two Memory bits interfere with each other, and the size of the device cannot be reduced. On the other hand, the existing SONOS flash memory cell generally adopts channel hot electron injection (CHE) physical effect to perform writing operation, adopts band-to-band tunneling hot hole injection (BBHH) physical effect or FN tunneling physical effect to perform erasing operation, and because the physical mechanism adopted by erasing and writing is different, trap electron charge injected in writing operation is inconsistent with trap hole charge injected in erasing operation, i.e. Trap Charge Mismatch Effect (TCME) is easy to generate, resulting in degradation of durability and retention reliability of the flash memory cell.

However, the conventional floating gate ETOX flash memory and SONOS NROM flash memory have problems that the process size cannot be reduced, the cell area is large, the writing power consumption is large, and the array area overhead is large, and high-density integration with a gigabit (Gb) capacity or more cannot be realized.

With the rapid development of applications such as mobile intelligent terminals, wearable devices, intelligent sensor networks and the like, higher requirements are put forward on the power consumption, storage capacity and cost of a flash memory, so that a flash memory technology with the advantages of low power consumption, small unit area, small process size, high array integration density, large capacity and the like is needed.

Disclosure of Invention

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art.

In order to solve the above problems in the prior art, the present disclosure proposes a flash memory cell erasing method.

According to one aspect of the present disclosure, there is provided an erasing method of a flash memory cell including a substrate and a well region provided within the substrate, a memory transistor provided on the well region and configured to store data, and a gate transistor provided on a side of the memory transistor in a horizontal direction on the well region and configured to perform a gate operation on the memory transistor, wherein the gate transistor and the memory transistor are connected in series, wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, a drain region of the gate transistor is connected to a second electrode of the flash memory cell, the erasing method including applying a first erase voltage to the first electrode, applying a second erase voltage to the second electrode, applying a third erase voltage to a gate electrode of the memory transistor, and applying a fourth erase voltage to the gate electrode of the gate transistor, wherein the first erase voltage is higher than a preset voltage, and the second erase voltage is equal to or higher than a second power voltage, and the third erase voltage is lower than the preset voltage, and the second power voltage is lower than the first power source voltage is higher than the preset voltage, and the gate transistor is higher than the first power voltage is set to the gate transistor, and the fourth power voltage is higher than the first power source voltage is higher than the gate transistor, and the gate transistor is set to the gate transistor is higher than the threshold voltage.

According to another aspect of the present disclosure, there is provided a method of erasing a flash memory cell including a substrate and a well region disposed within the substrate; a first storage transistor disposed on the well region and configured to store first data; and a gate transistor disposed between the first memory transistor and the second memory transistor in a horizontal direction on the well region, configured to isolate the first memory transistor and the second memory transistor and perform a gate operation on the first memory transistor and the second memory transistor, wherein the first memory transistor, the gate transistor, and the second memory transistor are sequentially connected in series, wherein a source region of the first memory transistor is connected to a first electrode of the flash memory cell, a drain region of the second memory transistor is connected to a second electrode of the flash memory cell, the erase method includes performing an erase operation by applying a second power voltage to the well region, applying a first erase voltage to the first electrode or the second electrode, applying a second erase voltage to the second electrode or the first electrode, applying a third erase voltage to a gate electrode of the first memory transistor or the second memory transistor, applying a fourth erase voltage to a gate electrode of the gate transistor, and applying a fifth erase voltage to a gate electrode of the second memory transistor in series, wherein the first erase voltage is higher than or equal to a first erase voltage, the second erase voltage is higher than or equal to a second erase voltage, the second erase voltage is higher than or equal to a first erase voltage, the second erase voltage is higher than or equal to a second erase voltage is performed to the first erase voltage, wherein the preset voltage is preset based on a carrier barrier height at an interface between the substrate and gate dielectric stacks of the first and second memory transistors, and wherein, the first, fourth and fifth erase voltages are higher than the second erase voltage such that the first, second and gate transistors are all turned on.

According to the erase method of the present disclosure, an erase voltage applied to a gate electrode of an erased memory transistor is lower than a second power supply voltage, so that channel hot electrons induce a hot hole injection physical effect to attract hot holes in a channel into a memory medium layer to achieve erase, so that a wider hole distribution and higher injection efficiency are provided compared to the existing band-tunneling hot hole (BBHH) erase method, and thus the erase method according to the present disclosure has a higher erase speed (several tens of microseconds), a larger erase window, smaller hot carrier damage, lower leakage current, and higher endurance reliability.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions are to be understood without departing from the spirit and scope of the present disclosure, both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the present disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.

Fig. 1 illustrates a cross-sectional view of a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 illustrates a schematic diagram of performing an erase operation on a first memory transistor by an erase method according to an embodiment of the present disclosure.

Fig. 4 illustrates a schematic diagram of performing an erase operation on a second memory transistor by an erase method according to an embodiment of the present disclosure.

Fig. 5 illustrates a cross-sectional view of a flash memory cell according to another embodiment of the present disclosure.

Fig. 6 illustrates an equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure.

Fig. 7 illustrates a schematic diagram of performing an erase operation on a memory transistor by an erase method according to another embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms, and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the spirit of the present invention.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail in some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise indicated, features, components, modules, layers, films, substrates, regions, and/or aspects, etc. (hereinafter referred to individually or collectively as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the drawings is typically provided to clarify the boundaries between adjacent elements. As such, no particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other property, attribute, shape, etc., whether cross-hatched or not present, is intended to convey or indicate any preference or requirement for the particular material, material property, dimension, proportion, etc., unless otherwise indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments can be implemented in different ways, the particular sequence of processes may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Also, like reference numerals designate like elements.

When an element such as a layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this extent, the term "connected" can refer to physical, electrical, and/or fluid connection with or without intervening elements. Furthermore, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system, such as x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ, for example. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under," "below," "beneath," "lower," "above," "upper," "higher" and "lateral" (e.g., as in "sidewall") and the like, may be used herein for descriptive purposes to describe the relationship between one element and another element as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and are, therefore, utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Embodiments are described herein with reference to cross-sectional and/or exploded views, which are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result, for example, from manufacturing. In this way, the regions illustrated in the figures may be schematic in nature and the shapes of the regions may not reflect the actual shape of the regions of the device and thus, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined as a P-type and the second doping type is defined as an N-type in fig. 1 as an example, it should be recognized by those skilled in the art that the present disclosure is not limited thereto and the first doping type may also be an N-type, in which case the second doping type may be a P-type.

According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

Further, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in this order. The first storage transistor MS110 may be disposed on the well region PW 102 and store the first DATA1. The second storage transistor MD 130 may be disposed on the well region PW 102 and store the second DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS110 and the second memory transistor MD 130 in the horizontal direction DR1 on the well region PW 102 for isolating the first memory transistor MS110 and the second memory transistor MD 130 and performing a gate operation on the first memory transistor MS110 and the second memory transistor MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, and thus the flash memory cell MC 100 can implement a two-bit storage function, i.e., simultaneously store the first DATA1 and the second DATA2.

Further, as shown in fig. 1, the source region of the first memory transistor MS110 is connected to the first electrode S of the flash memory cell MC 100, which may also be referred to as the source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which may also be referred to as the drain D of the flash memory cell MC 100.

Those skilled in the art will recognize that the definition of the source and drain of a flash memory cell is defined herein for ease of description, however the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" are used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117, which are sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. Further, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137, which are sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 stacked in this order in the vertical direction.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, and thus can implement a two-bit memory function.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC 100 for two-bit storage may be composed of three closely arranged transistors, namely a gate transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS110 located at a first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, a flash memory cell MC 100 may be formed on a well region PW 102 within a semiconductor substrate 101. Furthermore, in order to isolate well region PW 102 from substrate 101 in order to apply a voltage to well region PW 102 under certain operating conditions, well region PW 102 may be formed in deep well region DNW 103, as shown in fig. 1.

As shown in fig. 1, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

According to embodiments of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS110 may have the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment in order from bottom to top as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof. The hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicate glass material, or a combination thereof, according to embodiments of the present disclosure.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked from bottom to top in the vertical direction DR 2. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, or the like. According to an embodiment of the present disclosure, the thickness of the first oxide layer (tunnel oxide layer) 113 may be 1 to 6nm.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. Further, in accordance with embodiments of the present disclosure, the storage medium forming the storage medium layer 114 may include a mono-or poly-oxide such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, a mono-or poly-nitride such as silicon nitride, a mono-or poly-oxynitride such as silicon oxynitride, polysilicon or a nanocrystalline material, or a combination of the foregoing.

When the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium according to an embodiment of the present disclosure. At this time, the first memory transistor MS110 may be a SONOS (silicon-oxide-nitride-oxide-silicon) memory transistor.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS110 may be another trap charge-trapping memory transistor having a similar operation mechanism as a SONOS-type memory transistor, which uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, or the like, instead of the silicon nitride material in the SONOS memory as the memory medium layer 114.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS110 may also be a floating gate memory transistor, which uses a polysilicon material instead of a silicon nitride material in a SONOS memory device to form a floating gate for storing charges as the memory medium layer 114.

Furthermore, according to an embodiment of the present disclosure, the first memory transistor MS110 may also be a nano-crystalline memory transistor (nano-crystalline memory), which uses a nano-crystalline material with quantum dots (quantum dots) instead of a silicon nitride material in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by a person skilled in the art that reference herein to "length" means the dimension of the stated object in the first direction DR 1.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS110 and may be manufactured by the same process as the first memory transistor MS110 except that it is disposed at the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for brevity.

The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process dimension of the photolithography process. According to embodiments of the present disclosure, gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. Further, according to embodiments of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.

According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first memory transistor MS110, the second memory transistor MD 130 and the gate transistor MG 120 may each have a first doping type, and the doping concentrations of the channel regions 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second memory transistors MS110 and MD 130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG 120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. Furthermore, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions, according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the flash memory cell MC 100 may further include a first isolation portion 124 disposed between the first memory transistor MS110 and the gate transistor MG 120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120, and a second isolation portion 125 disposed between the gate transistor MG 120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG 120 is provided on both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130, respectively, with a certain isolation gap length. According to an embodiment of the present disclosure, the first and second spacers 124 and 125 may include the same material as the gate dielectric layer 122.

The flash memory cell according to the embodiment of the present disclosure can realize two memory transistors in one flash memory cell, so that the equivalent area of each memory bit can be greatly reduced, thereby achieving lower cost and higher integration density.

In addition, the memory transistor in the flash memory unit according to the embodiment of the disclosure can adopt a SONOS type device structure with a simple structure, and has the advantages of simple process, low gate electrode operation voltage and good data retention reliability.

In addition, in the flash memory cell according to the embodiment of the disclosure, the mutual influence of two storage bits is isolated through the gating transistor, and the distribution width and the lateral diffusion of stored charges are restrained, so that higher stored charge density can be obtained in the silicon nitride storage layer, the problems that the existing NROM storage cell which also adopts two-bit storage is wide in charge distribution, large in mutual interference, incapable of shrinking in gate length and the like are avoided, and the storage window and the data reliability are remarkably improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first memory transistor, the gate transistor, and the second memory transistor. As described above, the gate electrode length of the gate transistor is defined by the process feature size of the photolithographic process, which is typically about equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithographic process, which is typically denoted as F (or CF). In addition, gate electrode lengths of the first memory transistor and the second memory transistor are respectively defined by lengths of the self-aligned sidewall hard mask barrier portions, and thus may be smaller than F in size. Therefore, according to the embodiment of the disclosure, the smaller channel length of the flash memory unit can be obtained under the same process feature size, and the purposes of reducing the area and the manufacturing cost of the flash memory unit are achieved.

In addition, in the flash memory cell array composed of the flash memory cells according to the embodiments of the present disclosure, for the flash memory cells not selected to operate, the gate electrodes of the gate transistor and the first and second memory transistors are grounded, so that the entire serial channels of the flash memory cells are completely turned off, the equivalent channel length is enlarged, and thus, source-drain punch-through of the flash memory cells under high operation voltage can be avoided under smaller process feature sizes, thereby overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced with the reduction of the process feature sizes. Accordingly, the flash memory cell according to the embodiment of the present disclosure has better process miniaturization capability, and thus can obtain smaller cell area and manufacturing cost by shrinking the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as N-type doped channel regions, the threshold voltage of the memory transistor and the gate electrode operating voltage at the time of erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, by increasing the doping concentration of the P-type channel region of the gating transistor, the penetration resistance voltage of the flash memory unit can be increased, and the leakage current between the source electrode and the drain electrode of the unselected flash memory unit can be reduced.

Fig. 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to the embodiment of the present disclosure. Fig. 3 illustrates a schematic diagram of performing an erase operation on the first memory transistor MS 110 by the erase method of the embodiment of the present disclosure. Fig. 4 illustrates a schematic diagram of performing an erase operation on the second memory transistor MD 130 according to an erase method by an embodiment of the present disclosure.

Specifically, as shown in fig. 2, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130, which are sequentially connected in series. The gate transistor MG 120 may isolate the first and second memory transistors MS110 and MD 130 and perform a gate operation on the first and second memory transistors MS110 and MD 130. As shown in fig. 2, by controlling voltages applied to the source region (i.e., the first electrode S) of the first memory transistor MS110, the gate electrode 116 of the first memory transistor MS110, the gate electrode 123 of the gate transistor MG 120, the gate electrode 136 of the second memory transistor MD 130, and the drain region (i.e., the second electrode D) of the second memory transistor MD 130, the erase operation of the first memory transistor MS110 or the second memory transistor MD 130, respectively, can be achieved.

According to an embodiment of the present disclosure, the well PW 102 of the flash memory cell MC 100 may be grounded when an erase operation is performed on the flash memory cell MC 100.

Specifically, according to an embodiment of the present disclosure, as shown in fig. 3, in performing an erase operation on the first memory transistor MS110 of the flash memory cell MC 100, the erase method according to the present disclosure includes applying the second power supply voltage VSS to the well PW 102, applying the first erase voltage VE1 to the first electrode S, applying the second erase voltage VE2 to the second electrode D, applying the third erase voltage VE3 to the gate electrode 116 of the first memory transistor MS110, applying the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and applying the fifth erase voltage VE5 to the gate electrode 136 of the second memory transistor MD 130. For example, the second power supply voltage VSS may be a ground voltage GND, for example, 0V.

According to an embodiment of the present disclosure, the first erase voltage VE1 may be higher than a preset voltage VP, wherein the preset voltage VP is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS 110. For example, in the flash memory cell MC 100 shown in fig. 1, the preset voltage may enable carriers to cross a carrier barrier at an interface between the P-type channel region 111 and the lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the carrier is a hole and the hole barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 may be in a range of 3V to 6V, for example, the first erase voltage VE1 may be 4.6V. According to embodiments of the present disclosure, the first erase voltage VE1 may be provided by an external constant voltage source.

According to an embodiment of the present disclosure, the second erase voltage VE2 may be equal to or higher than the second power supply voltage VSS, which may be the ground voltage GND. For example, according to an embodiment of the present disclosure, the second erase voltage VE2 may be 0.2V.

According to an embodiment of the present disclosure, the third erase voltage VE3 may be equal to or lower than the second power supply voltage VSS. According to an embodiment of the present disclosure, the third erase voltage VE3 may be in the range of-8V to 0V. For example, according to an embodiment of the present disclosure, the third erase voltage VE3 may be-4.8V.

According to embodiments of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the first memory transistor MS110 may cause ionized hot holes (holes represented by open circles in fig. 3) in the depletion region of the first electrode S (source) to be attracted by the negative third erase voltage VE3 to be injected into the storage medium layer 114, e.g., silicon nitride, in the gate dielectric stack 112 of the first memory transistor MS110 (as indicated by open arrows in fig. 3). This hot hole neutralizes electrons stored during a writing (programming) operation of the flash memory cell MC 100 (solid circles in fig. 3 represent electrons) so that the threshold voltage of the first memory transistor MS110 is lowered, thereby enabling erasure of the first memory transistor MS 110.

According to an embodiment of the present disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power supply voltage VDD, which is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to an embodiment of the present disclosure, the fourth erase voltage VE4 may be 1V.

According to an embodiment of the present disclosure, the first, fourth and fifth erase voltages VE1, VE4 and VE5 are higher than the second erase voltage VE2 such that the first, second and gate transistors MS110, MD 130 and MG 120 are all turned on, i.e., the flash memory cell MC 100 is turned on as a whole.

According to an embodiment of the present disclosure, the fifth erase voltage VE5 may be in a range of 3V to 8V. For example, according to an embodiment of the present disclosure, the fifth erase voltage VE5 may be 5V.

Similarly, in performing an erase operation on the second memory transistor MD 130 of the flash memory cell MC 100, according to an embodiment of the present disclosure, as shown in fig. 4, the erase method according to the present disclosure includes applying the second power supply voltage VSS to the well PW 102, the first erase voltage VE1 to the second electrode D, the second erase voltage VE2 to the first electrode S, the fifth erase voltage VE5 to the gate electrode 116 of the first memory transistor MS110, the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and the third erase voltage VE3 to the gate electrode 136 of the second memory transistor MD 130.

As can be seen, due to the symmetrical structure of the flash memory cell MC 100, there is also a symmetrical relationship of the respective erase voltages VE1 to VW5 applied during the erasing of the first memory transistor MS110 and the second memory transistor MD 130. Therefore, for the sake of brevity, the erase voltage applied during the erase of the second memory transistor MD 130 will not be repeatedly described herein.

Specifically, taking the first memory transistor MS110 as an example, when the erase operation is performed on the first memory transistor MS110, the gate electrode 123 of the gate transistor MG 120 is applied with the fourth erase voltage VE4 slightly higher than the threshold voltage thereof, and thus is in a weak on-state, thereby suppressing the on-current (typically in the microampere scale) of the flash memory cell MC 100, so that the voltage difference of the serial channels (121 and 131) of the gate transistor MG 120 and the second memory transistor MD 130 can be greatly reduced. Accordingly, the voltage differences VE1-VE2 between the first electrode S and the second electrode D of the flash memory cell MC 110 are mostly applied to the channel region 111 of the first memory transistor MS110, so that channel hot electron induced thermal hole injection physical effects occur.

In particular, the erase method according to embodiments of the present disclosure is based on the first discovered physical effect of channel hot electron induced hot hole injection (Channel Hot Electron Induced Hot Hole Injection) by the inventors. Specifically, taking the case of erasing the first memory transistor MS110 as an example, when the erasing operation is performed on the first memory transistor MS110, the gate transistor MG 120 and the second memory transistor MD 130 are turned on, while the channel region 111 of the first memory transistor MS110 is fully depleted to form a depletion region due to the first erase voltage VE1 applied to the first electrode 142, the flash memory cell MC 100 is entirely turned on, an electron current is generated in the channel region and hot electrons are formed under the acceleration of the lateral electric field, and electron hole pairs are generated in the depletion region by impact ionization, wherein the hot holes are injected into the memory medium layer 114 of the first memory transistor MS110 under the attraction of the negative third erase voltage VE3 applied to the gate electrode 116 of the first memory transistor MS110, thereby realizing the erasure of the first memory transistor MS 110.

According to the embodiment of the present disclosure, when the erase operation is performed on the first memory transistor MS110, since the fourth erase voltage VE4 applied to the gate electrode 123 of the gate transistor MG 120 and the erase voltage VE5 applied to the gate electrode 136 of the second memory transistor MD 130 are both higher than the second power supply voltage VSS, i.e., the positive voltage, the second memory transistor MD 130 and the gate transistor MG 120 are turned on. Further, according to the embodiment of the present disclosure, when the erase operation is performed on the first memory transistor MS110, although the third erase voltage VE3 applied to the gate electrode 116 of the first memory transistor MS110 is equal to or lower than the second power supply voltage VSS, as described above, the channel region 111 of the first memory transistor MS110 is fully depleted to form a depletion region due to the first erase voltage VE1, so that the first memory transistor MS110 is still turned on. Accordingly, when the erasing method according to the embodiment of the present disclosure is performed, the flash memory cell MC 100 as a whole is turned on.

Although the first doping type is defined as P-type and the second doping type is defined as N-type in the above example, the first memory transistor MS110, the gate transistor MG 120, and the second memory transistor MD 130 are all N-type transistors. Those skilled in the art will recognize that the present disclosure is not so limited and that the first doping type may also be N-type and correspondingly the second doping type may be P-type, where the first memory transistor MS110, the gate transistor MG 120 and the second memory transistor MD 130 are all P-type transistors. In this case, the erase method according to the embodiment of the present disclosure is based on the channel hot hole induced hot electron injection (Channel Hot Hole Induced Hot Electron Injection) physical effect, the basic principle of which is consistent with the channel hot hole induced hot hole injection physical effect described above, and thus will not be described in more detail.

In addition, since the gate electrode length of the first memory transistor MS110 is much smaller than the equivalent channel length of the flash memory cell MC 100, the lateral electric field of the conduction channel of the first memory transistor MS110 and the channel hot hole injection efficiency can be significantly increased.

Those skilled in the art will recognize that although the erase method of the flash memory cell of the present disclosure is described above in connection with the flash memory cell MC 100 shown in fig. 1, the erase method of the flash memory cell of the present disclosure is not limited to the flash memory cell MC 100 shown in fig. 1. It is contemplated by those skilled in the art in light of the teachings of this disclosure that the methods of erasing flash memory cells of this disclosure can be applied to other types of flash memory cells, such as flash memory cells that include only one memory transistor, and all such variations are intended to be within the scope of this disclosure.

Fig. 5 illustrates a cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure. Fig. 6 shows an equivalent circuit diagram of a flash memory cell MC 200 according to another embodiment of the present disclosure.

As shown in fig. 5 and 6, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to fig. 1 and 2 only in that the flash memory cell MC 200 includes only one storage transistor, which may correspond to the first storage transistor MS110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200 shown in fig. 5 and 6, the same components as those of the flash memory cell MC 100 shown in fig. 1 and 2 are denoted by the same reference numerals, and the corresponding detailed description will be omitted.

As shown in fig. 5, a flash memory cell MC 200 according to another embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103. According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

As shown in fig. 5 and 6, according to another embodiment of the present disclosure, a flash memory cell MC 200 includes a memory transistor MS110 and a gate transistor MG 120 connected in series. The storage transistor MS110 may be disposed on the well region PW 102 and store DATA1. The gate transistor MG 120 is disposed on the side of the memory transistor MS110 in the horizontal direction DR1 on the well region PW 102 for performing a gate operation on the memory transistor MS 110.

As shown in fig. 5, according to another embodiment of the present disclosure, a source region of the memory transistor MS110 is connected to a first electrode S of the flash memory cell MC 200, which may also be referred to as a source S of the flash memory cell MC 200, and a drain region of the gate transistor MG 120 is connected to a second electrode D of the flash memory cell MC 200, which may also be referred to as a drain D of the flash memory cell MC 200.

As shown in fig. 5, according to another embodiment of the present disclosure, the memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. When the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO composite storage medium according to an embodiment of the present disclosure. At this time, the memory transistor MS110 may be a SONOS memory transistor

As shown in fig. 5, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top.

As shown in fig. 5, according to another embodiment of the present disclosure, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 200. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

As shown in fig. 5, according to another embodiment of the present disclosure, the flash memory cell MC 200 may further include an isolation portion 124 disposed between the memory transistor MS110 and the gate transistor MG 120 in the horizontal direction DR1 for isolating the gate electrode 116 of the memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120.

Fig. 7 illustrates a schematic diagram of performing an erase operation on the memory transistor MS110 by an erase method according to another embodiment of the present disclosure.

Specifically, as shown in fig. 6, the flash memory cell MC 200 includes a memory transistor MS110 and a gate transistor MG 120 connected in series. The gate transistor MG 120 may perform a gate operation on the memory transistor MS 110. As shown in fig. 6, the erase operation of the memory transistor MS110 may be achieved by controlling voltages applied to the source region (i.e., the first electrode S) of the memory transistor MS110, the gate electrode 116 of the memory transistor MS110, the gate electrode 123 of the gate transistor MG 120, and the drain region (i.e., the second electrode D) of the gate transistor MG 120.

According to another embodiment of the present disclosure, the well PW 102 of the flash memory cell MC 200 may be grounded when an erase operation is performed on the flash memory cell MC 200.

Specifically, according to another embodiment of the present disclosure, as shown in fig. 7, in performing an erase operation on the memory transistor MS110 of the flash memory cell MC 200, the erase method according to the present disclosure includes applying the second power supply voltage VSS to the well PW 102, the first erase voltage VE1 to the first electrode S, the second erase voltage VE2 to the second electrode D, the third erase voltage VE3 to the gate electrode 116 of the memory transistor MS110, and the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120. For example, the second power supply voltage VSS may be a ground voltage GND, for example, 0V.

According to another embodiment of the present disclosure, the first erase voltage VE1 may be higher than a preset voltage VP, wherein the preset voltage VP is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the memory transistor MS 110. For example, in the flash memory cell MC 200 shown in fig. 5, the preset voltage may enable holes to cross a hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 may be in a range of 3V to 6V, for example, the first erase voltage VE1 may be 4.6V. According to embodiments of the present disclosure, the first erase voltage VE1 may be provided by an external constant voltage source.

According to another embodiment of the present disclosure, the second erase voltage VE2 may be equal to or higher than the second power supply voltage VSS, which may be the ground voltage GND. For example, according to an embodiment of the present disclosure, the second erase voltage VE2 may be 0.2V.

According to another embodiment of the present disclosure, the third erase voltage VE3 may be equal to or lower than the second power supply voltage VSS. According to an embodiment of the present disclosure, the third erase voltage VE3 may be in the range of-8V to 0V. For example, according to an embodiment of the present disclosure, the third erase voltage VE3 may be-4.8V.

According to another embodiment of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the memory transistor MS110 may cause ionized hot holes (holes represented by open circles in fig. 7) in the depletion region of the first electrode S (source) to be attracted by the negative third erase voltage VE3 to be injected into the storage medium layer 114, e.g., silicon nitride, in the gate dielectric stack 112 of the memory transistor MS110 (as indicated by open arrows in fig. 3). This hot hole neutralizes electrons stored during the write (program) operation of flash memory cell MC 200 (the solid circles in fig. 7 represent electrons) such that the threshold voltage of memory transistor MS110 drops, thereby enabling the erasure of memory transistor MS 110.

According to an embodiment of the present disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power supply voltage VDD, which is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to an embodiment of the present disclosure, the fourth erase voltage VE4 may be 1V.

According to an embodiment of the present disclosure, the first erase voltage VE1 and the fourth erase voltage VE4 are higher than the second erase voltage VE2 such that both the memory transistor MS110 and the gate transistor MG 120 are turned on, i.e., the flash memory cell MC 200 is turned on as a whole.

The erase method according to another embodiment of the present disclosure is also based on the first discovered physical effect of channel hot electron induced hot hole injection (Channel Hot Electron Induced Hot Hole Injection) by the inventors and therefore, for brevity, will not be described in further detail herein.

The erase method according to the embodiments of the present disclosure has a wider hole distribution and higher injection efficiency than the existing erase method with tunneling hot holes (BBHH) based on the channel hot electron induced hot hole injection physical effect first discovered by the inventors, so that the erase method according to the embodiments of the present disclosure has a higher erase speed (several tens of microseconds), a larger erase window, less hot carrier damage, lower leakage current, and higher endurance reliability.

Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will understand that various modifications and changes may be made thereto without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims (10)

1. A method of erasing a flash memory cell, the flash memory cell comprising:

A substrate and a well region disposed within the substrate;

A memory transistor disposed on the well region and configured to store data, and

A gate transistor disposed on one side of the memory transistor in a horizontal direction on the well region, configured to perform a gate operation for the memory transistor,

Wherein the gating transistor and the memory transistor are connected in series,

Wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, a drain region of the gate transistor is connected to a second electrode of the flash memory cell,

The erasing method comprises the following steps:

Performing an erase operation on the memory transistor by applying a second power supply voltage to the well region, a first erase voltage to the first electrode, a second erase voltage to the second electrode, a third erase voltage to a gate electrode of the memory transistor, and a fourth erase voltage to a gate electrode of the gate transistor,

Wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power voltage, the third erase voltage is equal to or lower than the second power voltage, and the fourth erase voltage is equal to or lower than the first power voltage,

Wherein the first power supply voltage is higher than the second power supply voltage,

Wherein the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the memory transistor, and

Wherein the first erase voltage and the fourth erase voltage are higher than the second erase voltage such that both the memory transistor and the gate transistor are turned on.

2. A method of erasing a flash memory cell, the flash memory cell comprising:

A substrate and a well region disposed within the substrate;

a first storage transistor disposed on the well region and configured to store first data;

a second memory transistor disposed on the well region and configured to store second data, and

A gate transistor disposed between the first memory transistor and the second memory transistor in a horizontal direction on the well region, configured to isolate the first memory transistor and the second memory transistor and perform a gate operation on the first memory transistor and the second memory transistor,

Wherein the first memory transistor, the gating transistor and the second memory transistor are sequentially connected in series,

Wherein a source region of the first memory transistor is connected to a first electrode of the flash memory cell, a drain region of the second memory transistor is connected to a second electrode of the flash memory cell,

The erasing method comprises the following steps:

Performing an erase operation on the first memory transistor or the second memory transistor by applying a second power supply voltage to the well region, a first erase voltage to the first electrode or the second electrode, a second erase voltage to the second electrode or the first electrode, a third erase voltage to a gate electrode of the first memory transistor or the second memory transistor, a fourth erase voltage to a gate electrode of the gate transistor, and a fifth erase voltage to a gate electrode of the second memory transistor or the first memory transistor,

Wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power voltage, the third erase voltage is equal to or lower than the second power voltage, and the fourth erase voltage is equal to or lower than the first power voltage,

Wherein the first power supply voltage is higher than the second power supply voltage,

Wherein the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors, and

Wherein the first, fourth and fifth erase voltages are higher than the second erase voltage such that the first, second and gating transistors are all turned on.

3. The erase method of claim 1 or 2, wherein the erase method is based on channel hot electron induced hot hole injection physical effects.

4. The erase method of claim 1 or 2, wherein the memory transistor is a charge trapping memory transistor having a gate dielectric stack comprising a tunnel oxide layer, a charge storage layer and a blocking oxide layer.

5. The erase method of claim 4, wherein the tunnel oxide layer has a thickness of 1 to 6nm.

6. The erase method of claim 4, wherein the charge storage layer comprises a mono-or poly-oxide, a mono-or poly-nitride, a mono-or poly-oxynitride, a polysilicon or nanocrystalline material, or a combination thereof.

7. The erase method of claim 4, wherein the charge storage layer comprises a high K material rich in charge traps.

8. The erase method of claim 4, wherein the tunnel oxide layer and the blocking oxide layer comprise silicon oxide or aluminum oxide.

9. The erase method of claim 1, wherein,

The first supply voltage is in the range of 0.8V to 5V,

The second power supply voltage is a ground voltage,

The first erase voltage is in the range of 3V to 6V, and

The third erase voltage is in a range of-8V to 0V.

10. The erase method of claim 2, wherein,

The first supply voltage is in the range of 0.8V to 5V,

The second power supply voltage is a ground voltage,

The first erase voltage is in the range of 3V to 6V,

The third erase voltage is in the range of-8V to 0V, and

The fifth erase voltage is in a range of 3V to 8V.