CN119497383A

CN119497383A - Writing method of flash memory unit

Info

Publication number: CN119497383A
Application number: CN202411548110.1A
Authority: CN
Inventors: 请求不公布姓名; 石振东; 蒋家勇
Original assignee: Beijing Pansin Microelectronics Technology Co ltd
Current assignee: Beijing Pansin Microelectronics Technology Co ltd
Priority date: 2024-11-01
Filing date: 2024-11-01
Publication date: 2025-02-21

Abstract

The present disclosure provides a method for writing a flash memory cell. The flash memory cell includes a storage transistor and a gating transistor connected in series. The writing method according to the present disclosure includes applying each writing voltage to each electrode of the flash memory cell and the gate electrode of each transistor, wherein the writing method is based on a channel hot carrier injection mechanism, and in a first writing step, a lower writing voltage is applied to the gate electrode of the storage transistor being written, and in a second writing step, a higher writing voltage is applied to the gate electrode of the storage transistor being written. The writing method of the flash memory cell according to the present disclosure adopts a writing step of a dual channel hot carrier injection mechanism, which can reduce the influence of the trapped charge mismatch effect (TCME) compared with the existing writing method, thereby improving durability and maintaining reliability.

Description

Writing method of flash memory unit

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method of writing a flash memory cell.

Background

Flash memory, abbreviated as flash memory, is a non-volatile memory, i.e. the stored data will not be lost even if the power is turned off, and is especially suitable for the fields of mobile communication and computer storage parts. In addition, some flash memories also have high density storage capability, and are suitable for applications such as mass storage media.

Conventional flash memories employ a floating gate type cell structure. The floating gate type nonvolatile memory originates from MIMIS (Metal-Insulator-Semiconductor) structure proposed by d.kahng and s.sze in 1967. The structure is formed by adding a Metal floating gate and an ultrathin tunneling Oxide layer on the basis of a traditional MOSFET (Metal-Oxide-Semiconductor FIELD EFFECT Transistor) so as to store charges by using the Metal floating gate. Based on this, masuoka et al, in 1984, first proposed the concept of Flash Memory (Flash Memory), i.e., to achieve high-speed erase capability by block-wise erase/write (programming), and to eliminate the select tube necessary in EEPROM (Erasable Programmable Read-only Memory) to have a smaller Memory cell size. After the advent of flash memory, it has been rapidly developed with its high writing speed, high integration, and superior performance. Intel corporation proposed an ETOX structure flash memory cell (ETOX: electron Tunneling Oxide device, electron tunneling oxide device) in 1988, which became the basis for the development of most floating gate type flash memory cell structures so far.

However, the floating gate type flash memory has the disadvantages of complicated process, adverse scaling down of process size and cell area due to the increased longitudinal height of the gate structure due to the existence of the floating gate structure in the flash memory cell, and adverse improvement of reliability of the memory due to free movement of stored charges in the floating gate due to the conductivity of the floating gate. In order to solve the problems of complicated process, poor reliability and the like of the floating gate type flash Memory, researchers have proposed a Charge trapping Memory (CTM: charge-Trapping-Memory), also called SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon: silicon-Oxide-Nitride-Oxide-Silicon) flash Memory, which stores charges by using a Silicon Nitride medium. Based on this, eitan et al proposed a two-bit Memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, which uses the non-conductive property of an insulating silicon Nitride Memory medium to realize two Memory bits at the source and drain terminals of a Memory transistor, but the cell structure has the disadvantages that the two Memory bits interfere with each other, and the size of the device cannot be reduced. On the other hand, the existing SONOS flash memory cell generally adopts channel hot electron injection (CHE) physical effect to perform writing operation, adopts band-to-band tunneling hot hole injection (BBHH) physical effect or FN tunneling physical effect to perform erasing operation, and because the physical mechanism adopted by erasing and writing is different, trap electron charge injected in writing operation is inconsistent with trap hole charge injected in erasing operation, i.e. Trap Charge Mismatch Effect (TCME) is easy to generate, resulting in degradation of durability and retention reliability of the flash memory cell.

However, the conventional floating gate ETOX flash memory and SONOS NROM flash memory have problems that the process size cannot be reduced, the cell area is large, the writing power consumption is large, and the array area overhead is large, and high-density integration with a gigabit (Gb) capacity or more cannot be realized.

With the rapid development of applications such as mobile intelligent terminals, wearable devices, intelligent sensor networks and the like, higher requirements are put forward on the power consumption, storage capacity and cost of a flash memory, so that a flash memory technology with the advantages of low power consumption, small unit area, small process size, high array integration density, large capacity and the like is needed.

Disclosure of Invention

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art.

In order to solve the above problems in the prior art, the present disclosure proposes a writing method, also called a programming method, of a flash memory cell.

According to one aspect of the present disclosure, there is provided a writing method of a flash memory cell including a substrate including a deep well region and a well region provided on the deep well region, a memory transistor provided on the well region and configured to store data, and a gate transistor provided on one side of the memory transistor in a horizontal direction on the well region and configured to perform a gate operation on the memory transistor, wherein the memory transistor and the gate transistor are connected in series, wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, a drain region of the gate transistor is connected to a second electrode of the flash memory cell, the writing method including a first writing step of applying a first writing voltage to the first electrode, applying a second writing voltage to the second electrode, applying a third writing voltage to a gate electrode of the memory transistor, and applying a fourth writing voltage to the gate electrode of the memory transistor, performing a writing operation on the memory transistor, wherein the first writing voltage is higher than or equal to a preset gate voltage, a second writing voltage is applied to the first electrode, the second writing voltage is higher than the preset gate electrode, and the second writing step of applying a second writing voltage is higher than the preset gate voltage to the gate transistor, wherein the first writing voltage is higher than the preset gate electrode is equal to or equal to the preset gate voltage, the first writing voltage is applied to the first writing transistor, the first writing step is applied to the second writing voltage, the gate transistor is applied to the gate electrode is higher than the preset gate voltage, and the fourth writing voltage is applied to the gate transistor is higher than the preset gate voltage, and the gate voltage is applied to the gate transistor is higher than the gate electrode, and the gate transistor is applied to the gate voltage is higher than the gate voltage high, and the gate transistor is applied to the gate voltage is the high writing data and the gate transistor is applied to the gate transistor and the gate transistor is high, wherein the first write voltage and the fourth write voltage are higher than the second write voltage, and wherein the memory transistor and the gating transistor are both turned on during a write operation of the flash memory cell.

According to another aspect of the present disclosure, there is provided a writing method of a flash memory cell including a substrate including a deep well region and a well region disposed on the deep well region, a first storage transistor disposed on the well region and configured to store first data, a second storage transistor disposed on the well region and configured to store second data, and a gate transistor disposed between the first storage transistor and the second storage transistor in a horizontal direction on the well region and configured to isolate the first storage transistor and the second storage transistor and perform a gate operation to the first storage transistor and the second storage transistor, wherein a source region of the first storage transistor is connected to a first electrode of the flash memory cell, a drain region of the second storage transistor is connected to a second electrode of the flash memory cell, the writing method including a first writing step of applying a second writing voltage to the first electrode or the second electrode, applying a second writing voltage to the first electrode or the second storage transistor in a horizontal direction, applying a gate operation to the first storage transistor and performing a gate operation to the first storage transistor and the second storage transistor, wherein the first storage transistor, the gate transistor and the second storage transistor are sequentially connected in series, and the source region of the first storage transistor is connected to the first electrode of the flash memory cell, the drain region is connected to the second electrode of the flash memory cell, the second storage transistor, the writing method includes a fifth writing step of applying a second writing voltage to the first writing transistor or the second writing transistor to the second electrode or the second writing transistor and the second writing transistor to the second writing transistor and the second writing transistor. Applying a fourth write voltage to the gate electrode of the gate transistor and applying a fifth write voltage to the gate electrode of the second memory transistor or the first memory transistor, performing a write operation on the first memory transistor or the second memory transistor, wherein the fourth write voltage is equal to or lower than a first supply voltage, the second write voltage is equal to or higher than a second supply voltage, the first write voltage is higher than a preset voltage, the third write voltage is higher than the first write voltage, wherein the first supply voltage is higher than the second supply voltage, wherein the preset voltage is preset according to a carrier barrier height at an interface between the substrate and gate dielectric stacks of the first memory transistor and the second memory transistor, wherein the first write voltage, the fourth write voltage, and the fifth write voltage are each higher than the second write voltage, and wherein during a write operation of the flash memory cell, the first memory transistor, the second memory transistor, and the gate transistor are all turned on.

According to the writing method of the flash memory unit, the writing step of a double channel hot carrier injection mechanism is adopted, compared with the prior writing method, the writing method can form lower trap charge concentration on the side close to the gating transistor and higher trap charge concentration on the side far away from the gating transistor in the storage medium layer of the storage transistor, so that a storage window can be enlarged, the influence of Trap Charge Mismatch Effect (TCME) can be reduced, and the durability and the reliability can be improved.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions are to be understood without departing from the spirit and scope of the present disclosure, and the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principle of the invention.

Fig. 1 illustrates a cross-sectional view of a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of performing a write operation to a first memory transistor by a first write step of a write method according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of performing a write operation to a first memory transistor by a second write step of a write method according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of performing a write operation to a second memory transistor by a first write step of a write method according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of performing a write operation to a second memory transistor by a second write step of a write method according to an embodiment of the present disclosure.

Fig. 7 illustrates a cross-sectional view of a flash memory cell according to another embodiment of the present disclosure.

Fig. 8 illustrates an equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of performing a write operation to a memory transistor by a first write step of a write method according to another embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of performing a write operation to a memory transistor by a second write step of a write method according to another embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms, and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the spirit of the present invention.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail in some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise indicated, features, components, modules, layers, films, substrates, regions, and/or aspects, etc. (hereinafter referred to individually or collectively as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the drawings is typically provided to clarify the boundaries between adjacent elements. As such, no particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other property, attribute, shape, etc., whether cross-hatched or not present, is intended to convey or indicate any preference or requirement for the particular material, material property, dimension, proportion, etc., unless otherwise indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments can be implemented in different ways, the particular sequence of processes may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Also, like reference numerals designate like elements.

When an element such as a layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this extent, the term "connected" can refer to physical, electrical, and/or fluid connection with or without intervening elements. Furthermore, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system, such as x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ, for example. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under," "below," "beneath," "lower," "above," "upper," "higher" and "lateral" (e.g., as in "sidewall") and the like, may be used herein for descriptive purposes to describe the relationship between one element and another element as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and are, therefore, utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Embodiments are described herein with reference to cross-sectional and/or exploded views, which are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result, for example, from manufacturing. In this way, the regions illustrated in the figures may be schematic in nature and the shapes of the regions may not reflect the actual shape of the regions of the device and thus, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined as a P-type and the second doping type is defined as an N-type in fig. 1 as an example, it should be recognized by those skilled in the art that the present disclosure is not limited thereto and the first doping type may also be an N-type, in which case the second doping type may be a P-type.

According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

Further, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in this order. The first storage transistor MS110 may be disposed on the well region PW 102 and store the first DATA1. The second storage transistor MD 130 may be disposed on the well region PW 102 and store the second DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS110 and the second memory transistor MD 130 in the horizontal direction DR1 on the well region PW 102 for isolating the first memory transistor MS110 and the second memory transistor MD 130 and performing a gate operation on the first memory transistor MS110 and the second memory transistor MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, and thus the flash memory cell MC 100 can implement a two-bit storage function, i.e., simultaneously store the first DATA1 and the second DATA2.

Further, as shown in fig. 1, the source region of the first memory transistor MS110 is connected to the first electrode S of the flash memory cell MC 100, which may also be referred to as the source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which may also be referred to as the drain D of the flash memory cell MC 100.

Those skilled in the art will recognize that the definition of the source and drain of a flash memory cell is defined herein for ease of description, however the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" are used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117, which are sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. Further, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137, which are sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 stacked in this order in the vertical direction.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, and thus can implement a two-bit memory function.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC 100 for two-bit storage may be composed of three closely arranged transistors, namely a gate transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS110 located at a first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, a flash memory cell MC 100 may be formed on a well region PW 102 within a semiconductor substrate 101. Furthermore, in order to isolate well region PW 102 from substrate 101 in order to apply a voltage to well region PW 102 under certain operating conditions, well region PW 102 may be formed in deep well region DNW 103, as shown in fig. 1.

As shown in fig. 1, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

According to embodiments of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS110 may have the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment in order from bottom to top as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof. The hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicate glass material, or a combination thereof, according to embodiments of the present disclosure.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked from bottom to top in the vertical direction DR 2. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, or the like. According to an embodiment of the present disclosure, the thickness of the first oxide layer (tunnel oxide layer) 113 may be 1 to 15nm.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. Further, in accordance with embodiments of the present disclosure, the storage medium forming the storage medium layer 114 may include a mono-or poly-oxide such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, a mono-or poly-nitride such as silicon nitride, a mono-or poly-oxynitride such as silicon oxynitride, polysilicon or a nanocrystalline material, or a combination of the foregoing.

When the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium according to an embodiment of the present disclosure. At this time, the first memory transistor MS110 may be a SONOS (silicon-oxide-nitride-oxide-silicon) memory transistor.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS110 may be another trap charge-trapping memory transistor having a similar operation mechanism as a SONOS-type memory transistor, which uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, or the like, instead of the silicon nitride material in the SONOS memory as the memory medium layer 114.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS110 may also be a floating gate memory transistor, which uses a polysilicon material instead of a silicon nitride material in a SONOS memory device to form a floating gate for storing charges as the memory medium layer 114.

Furthermore, according to an embodiment of the present disclosure, the first memory transistor MS110 may also be a nano-crystalline memory transistor (nano-crystalline memory), which uses a nano-crystalline material with quantum dots (quantum dots) instead of a silicon nitride material in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by a person skilled in the art that reference herein to "length" means the dimension of the stated object in the first direction DR 1.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS110 and may be manufactured by the same process as the first memory transistor MS110 except that it is disposed at the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for brevity.

The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process dimension of the photolithography process. According to embodiments of the present disclosure, gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. Further, according to embodiments of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.

According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first memory transistor MS110, the second memory transistor MD 130 and the gate transistor MG 120 may each have a first doping type, and the doping concentrations of the channel regions 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second memory transistors MS110 and MD 130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG 120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. Furthermore, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions, according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the flash memory cell MC 100 may further include a first isolation portion 124 disposed between the first memory transistor MS110 and the gate transistor MG 120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120, and a second isolation portion 125 disposed between the gate transistor MG 120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG 120 is provided on both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130, respectively, with a certain isolation gap length. According to an embodiment of the present disclosure, the first and second spacers 124 and 125 may include the same material as the gate dielectric layer 122.

The flash memory cell according to the embodiment of the present disclosure can realize two memory transistors in one flash memory cell, so that the equivalent area of each memory bit can be greatly reduced, thereby achieving lower cost and higher integration density.

In addition, the memory transistor in the flash memory unit according to the embodiment of the disclosure can adopt a SONOS type device structure with a simple structure, and has the advantages of simple process, low gate electrode operation voltage and good data retention reliability.

In addition, in the flash memory cell according to the embodiment of the disclosure, the mutual influence of two storage bits is isolated through the gating transistor, and the distribution width and the lateral diffusion of stored charges are restrained, so that higher stored charge density can be obtained in the silicon nitride storage layer, the problems that the existing NROM storage cell which also adopts two-bit storage is wide in charge distribution, large in mutual interference, incapable of shrinking in gate length and the like are avoided, and the storage window and the data reliability are remarkably improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first memory transistor, the gate transistor, and the second memory transistor. As described above, the gate electrode length of the gate transistor is defined by the process feature size of the photolithographic process, which is typically about equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithographic process, which is typically denoted as F (or CF). In addition, gate electrode lengths of the first memory transistor and the second memory transistor are respectively defined by lengths of the self-aligned sidewall hard mask barrier portions, and thus may be smaller than F in size. Therefore, according to the embodiment of the disclosure, the smaller channel length of the flash memory unit can be obtained under the same process feature size, and the purposes of reducing the area and the manufacturing cost of the flash memory unit are achieved.

In addition, in the flash memory cell array composed of the flash memory cells according to the embodiments of the present disclosure, for the flash memory cells not selected to operate, the gate electrodes of the gate transistor and the first and second memory transistors are grounded, so that the entire serial channels of the flash memory cells are completely turned off, the equivalent channel length is enlarged, and thus, source-drain punch-through of the flash memory cells under high operation voltage can be avoided under smaller process feature sizes, thereby overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced with the reduction of the process feature sizes. Accordingly, the flash memory cell according to the embodiment of the present disclosure has better process miniaturization capability, and thus can obtain smaller cell area and manufacturing cost by shrinking the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as N-type doped channel regions, the threshold voltage of the memory transistor and the gate electrode operating voltage at the time of erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, by increasing the doping concentration of the P-type channel region of the gating transistor, the penetration resistance voltage of the flash memory unit can be increased, and the leakage current between the source electrode and the drain electrode of the unselected flash memory unit can be reduced.

Fig. 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to the embodiment of the present disclosure. Fig. 3 shows a schematic diagram of performing a write operation to the first memory transistor MS110 by a first write step of the write method according to an embodiment of the present disclosure. Fig. 4 shows a schematic diagram of performing a write operation to the first memory transistor MS110 by the second write step of the write method according to an embodiment of the present disclosure. In fig. 3 and 4 and fig. 5 and 6 described below, open circles represent holes, and filled circles represent electrons.

Specifically, as shown in fig. 2, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130, which are sequentially connected in series. The gate transistor MG 120 may isolate the first and second memory transistors MS110 and MD 130 and perform a gate operation on the first and second memory transistors MS110 and MD 130. As shown in fig. 2, by controlling voltages applied to the source region (i.e., the first electrode S) of the first memory transistor MS110, the gate electrode 116 of the first memory transistor MS110, the gate electrode 123 of the gate transistor MG 120, the gate electrode 136 of the second memory transistor MD 130, and the drain region (i.e., the second electrode D) of the second memory transistor MD 130, the writing operation to the first memory transistor MS110 or the second memory transistor MD 130, respectively, can be realized.

According to an embodiment of the present disclosure, the writing operation to the first memory transistor MS110 or the second memory transistor MD 130 may be performed by two steps, i.e., a first writing step and a second writing step, which are sequentially performed, respectively.

According to an embodiment of the present disclosure, when a write operation is performed on the flash memory cell MC 100, the P-well 102 of the flash memory cell MC 100 may be grounded or a negative voltage lower than a ground voltage may be applied.

Specifically, according to an embodiment of the present disclosure, as shown in fig. 3, a write operation is first performed on the first memory transistor MS110 of the flash memory cell MC 100 through a first write step. At this time, the first write voltage VW1 is applied to the first electrode S, the second write voltage VW2 is applied to the second electrode D, the third write voltage VW3 is applied to the gate electrode 116 of the first memory transistor MS110, the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120, and the fifth write voltage VW5 is applied to the gate electrode 136 of the second memory transistor MD 130.

According to an embodiment of the present disclosure, the first write voltage VW1 may be higher than a preset voltage, which is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS 110. For example, in the flash memory cell MC 100 shown in fig. 1, the preset voltage may enable electrons to cross an electron barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 may be in the range of 3V to 6V. For example, according to an embodiment of the present disclosure, the first write voltage VW1 may be 4.4V. According to an embodiment of the present disclosure, the first write voltage VW1 may be provided by an external constant voltage source.

According to an embodiment of the present disclosure, the second write voltage VW2 may be equal to or higher than the second power supply voltage VSS, which may be the ground voltage GND. For example, according to an embodiment of the present disclosure, the second write voltage VW2 may be 0.2V. Further, according to an embodiment of the present disclosure, the second write voltage VW2 may be connected to the second power supply voltage VSS through a constant current load.

According to an embodiment of the present disclosure, the third write voltage VW3 may be higher than the first write voltage VW1. According to an embodiment of the present disclosure, the third write voltage VW3 may be in the range of 4V to 10V. For example, according to an embodiment of the present disclosure, the third write voltage VW3 may be 5.4V.

According to an embodiment of the present disclosure, the fourth write voltage VW4 may be equal to or lower than the first power supply voltage VDD, which is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to an embodiment of the present disclosure, the fourth write voltage VW4 may be 1V.

According to an embodiment of the present disclosure, the first, fourth, and fifth write voltages VW1, VW4, and VW5 may be higher than the second write voltage VW2. According to an embodiment of the present disclosure, the fifth write voltage VW5 may be in the range of 3V to 8V. For example, according to an embodiment of the present disclosure, the fifth write voltage VW5 may be 5V.

Further, according to the embodiment of the present disclosure, during the first writing step of the flash memory cell MC 100, the first to fifth writing voltages VW1 to VW5 cause the first memory transistor MS110, the second memory transistor MD 130, and the gate transistor MG 120 to be all turned on.

Subsequently, according to an embodiment of the present disclosure, as shown in fig. 4, a write operation is then performed on the first memory transistor MS110 of the flash memory cell MC 100 through the second write step. At this time, the first write voltage VW1 applied to the first electrode S, the second write voltage VW2 applied to the second electrode D, the fourth write voltage VW4 applied to the gate electrode 123 of the gate transistor MG 120, and the fifth write voltage VW5 applied to the gate electrode 136 of the second memory transistor MD 130 remain unchanged, and the sixth write voltage VW6 is applied to the gate electrode 116 of the first memory transistor MS 110. According to an embodiment of the present disclosure, the sixth write voltage VW6 may be greater than the third write voltage VW3. According to an embodiment of the present disclosure, the sixth write voltage VW6 may be in the range of 5V to 12V. For example, as described above, the third write voltage VW3 may be 5.4V, and the sixth write voltage VW6 may be 6.2V.

Further, according to an embodiment of the present disclosure, during the second writing step of the flash memory cell MC 100, the first, second, sixth, fourth, and fifth writing voltages VW1, VW2, VW6, VW4, and VW5 cause the first memory transistor MS110, the second memory transistor MD 130, and the gate transistor MG 120 to be all turned on.

Fig. 5 shows a schematic diagram of performing a write operation to the second memory transistor MD 130 by a first write step of the write method according to an embodiment of the present disclosure. Fig. 6 shows a schematic diagram of performing a write operation to the second memory transistor MD 130 by the second write step of the write method according to the embodiment of the present disclosure.

Similarly, in performing a write operation to the second memory transistor MD 130 of the flash memory cell MC 100, according to an embodiment of the present disclosure, as shown in fig. 5, the second write voltage VW2 is first applied to the first electrode S, the first write voltage VW1 is applied to the second electrode D, the fifth write voltage VW5 is applied to the gate electrode 116 of the first memory transistor MS110, the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120, and the third write voltage VW3 is applied to the gate electrode 136 of the second memory transistor MD 130 through the first write step.

Subsequently, as shown in fig. 6, a write operation is then performed on the first memory transistor MS110 of the flash memory cell MC 100 by the second write step. At this time, the second write voltage VW2 applied to the first electrode S, the first write voltage VW1 applied to the second electrode D, the fourth write voltage VW4 applied to the gate electrode 123 of the gate transistor MG 120, and the fifth write voltage VW5 applied to the gate electrode 116 of the first memory transistor MS110 remain unchanged, and the sixth write voltage VW6 is applied to the gate electrode 136 of the second memory transistor MD 130.

As can be seen from this, due to the symmetrical structure of the flash memory cell MC 100, there is also a symmetrical relationship in the write operations of the first memory transistor MS110 and the second memory transistor MD 130, i.e., the respective write voltages VW1 to VW5 applied during the execution of the first write step and the second write step. Therefore, for the sake of brevity, the write voltage applied during the write operation of the second memory transistor MD 130 will not be repeatedly described herein.

According to embodiments of the present disclosure, the write operation to the first memory transistor MS110 and the second memory transistor MD 130 described above employs a dual channel hot electron injection mechanism.

Specifically, taking the first memory transistor MS110 as an example, when the write operation is performed on the first memory transistor MS110 through the first write step, the gate electrode 123 of the gate transistor MG 120 is applied with the fourth write voltage VW4 slightly higher than the threshold voltage thereof, and thus is in the weak on-state, thereby suppressing the on-current (typically in microampere magnitude) of the flash memory cell MC 100, so that the voltage difference of the serial channels (121 and 131) of the gate transistor MG 120 and the second memory transistor MD 130 can be greatly reduced. Accordingly, the voltage differences VW1-VW2 between the first electrode S and the second electrode D of the flash memory cell MC 110 are mostly applied to the conductive channel region 111 of the first memory transistor MS110, so that a channel hot electron injection physical effect occurs, and electrons are injected into the memory medium layer 114 under the attraction of the relatively low (e.g., 5.4V) third write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS110, so that the threshold voltage of the first memory transistor MS110 rises.

At this time, as shown in fig. 3, in the first writing step, channel hot electron injection is extended from the gate transistor MG 120 side to the first memory transistor MS110, and electrons are trapped along the entire channel region of the first memory transistor MS110 to be written. However, in the first writing step, electrons may accumulate in the storage medium layer 114 on the side close to the gate transistor MG 120, resulting in difficulty in being effectively erased in a subsequent hot hole erase operation, thereby inducing a Trapped Charge Mismatch Effect (TCME) in an erase-write cycle operation. In particular, the local residual electrons may cause an increase in the threshold voltage of the first memory transistor MS110 and a decrease in the read current, and the recombination of the residual charges may cause a decrease in the retention performance.

In the prior art, simply by decreasing the third writing voltage VW3 in the first writing step, the concentration of electrons accumulated on the side close to the gate transistor MG 120 can be reduced, thereby reducing the influence of TCME, but this causes the threshold voltage window of writing to be small, which has a problem of reduced retention performance.

Thus, according to an embodiment of the present disclosure, a second writing step is introduced after the first writing step. As described above, according to the embodiment of the present disclosure, in the second writing step, the sixth writing voltage VW6 (e.g., 6.2V) higher than the third writing voltage VW3 is applied to the gate electrode 116 of the first memory transistor MS 110. It is to be noted that, in the storage medium layer 114, a small amount of electron charges have been accumulated on the side close to the gate transistor MG 120 by the first writing step, and electrons injected in the second writing step are accumulated only on the side away from the gate transistor MG 120 due to the shielding effect of the electron charges on the longitudinal gate electric field, so that the trap charge concentration of the local region away from the gate transistor MG 120 is increased and the storage window is increased, and the trap electrons of this region are more easily erased effectively in the subsequent hot hole erasing operation.

According to an embodiment of the present disclosure, the lower third write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS110 in the first write step may be used to write (program) the first memory transistor MS110 to a lower threshold voltage to avoid accumulation of excessive electrons on the gate transistor MG 120 side. Subsequently, according to an embodiment of the present disclosure, the higher sixth write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS110 in the second write step may be used to increase the trap electron density near the opposite side (i.e., the first electrode S side) of the gate transistor MG 120 to expand the threshold voltage window of the writing. In particular, for charge trapping memory devices, the charges programmed into the storage medium have localized distribution characteristics, i.e., may have different trap charge concentration distributions along the channel. The Dual channel hot electron writing mechanism (DCHE: dual-CHE) according to the present disclosure can form a lower trap charge concentration on the side close to the gate transistor MG 120 and a higher trap charge concentration on the side far from the gate transistor MG 120, so that a one-sided gaussian distribution of trapped charges can be formed, thereby reducing the influence of TCME, improving durability and maintaining reliability.

In addition, since the gate electrode length of the first memory transistor MS110 is much smaller than the equivalent channel length of the flash memory cell MC 100, the lateral electric field of the on channel of the first memory transistor MS110 and the channel hot electron injection efficiency can be significantly increased. Therefore, the writing method according to the embodiment of the present disclosure has advantages of low operation power consumption and high writing speed compared to the existing channel hot electron injection writing method, and can improve the memory data writing throughput (Write Through-Put) by increasing the number of cells written in parallel.

Accordingly, those skilled in the art will recognize that although the writing method of the flash memory cell of the present disclosure (including the multi-value writing method) is described above in connection with the flash memory cell MC 100 shown in fig. 1, the writing method of the flash memory cell of the present disclosure is not limited to the flash memory cell MC 100 shown in fig. 1. It is contemplated by those skilled in the art in light of the teachings of this disclosure that the methods of writing to flash memory cells of this disclosure may be applied to other types of flash memory cells, such as flash memory cells that include only one memory transistor, and all such variations are intended to be within the scope of this disclosure.

Fig. 7 illustrates a cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure. Fig. 8 shows an equivalent circuit diagram of a flash memory cell MC 200 according to another embodiment of the present disclosure.

As shown in fig. 7 and 8, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to fig. 1 and 2 only in that the flash memory cell MC 200 includes only one storage transistor, which may correspond to the first storage transistor MS110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200 shown in fig. 7 and 8, the same components as those of the flash memory cell MC 100 shown in fig. 1 and 2 are denoted by the same reference numerals, and the corresponding detailed description will be omitted.

As shown in fig. 7, a flash memory cell MC 200 according to another embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103. According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

As shown in fig. 7 and 8, according to another embodiment of the present disclosure, a flash memory cell MC 200 includes a memory transistor MS110 and a gate transistor MG 120 connected in series. The storage transistor MS110 may be disposed on the well region PW 102 and store DATA1. The gate transistor MG 120 is disposed on the side of the memory transistor MS110 in the horizontal direction DR1 on the well region PW 102 for performing a gate operation on the memory transistor MS 110.

As shown in fig. 7, according to another embodiment of the present disclosure, a source region of the memory transistor MS110 is connected to a first electrode S of the flash memory cell MC 200, which may also be referred to as a source S of the flash memory cell MC 200, and a drain region of the gate transistor MG 120 is connected to a second electrode D of the flash memory cell MC 200, which may also be referred to as a drain D of the flash memory cell MC 200.

As shown in fig. 7, according to another embodiment of the present disclosure, the memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. When the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO composite storage medium according to an embodiment of the present disclosure. At this time, the memory transistor MS110 may be a SONOS memory transistor

As shown in fig. 7, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top.

As shown in fig. 7, according to another embodiment of the present disclosure, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 200. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

As shown in fig. 7, according to another embodiment of the present disclosure, the flash memory cell MC 200 may further include an isolation portion 124 disposed between the memory transistor MS110 and the gate transistor MG 120 in the horizontal direction DR1 for isolating the gate electrode 116 of the memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120.

Fig. 9 shows a schematic diagram of performing a write operation to the memory transistor MS110 by a first write step of a write method according to another embodiment of the present disclosure. Fig. 10 shows a schematic diagram of performing a write operation to the memory transistor MS110 by a second write step of the write method according to another embodiment of the present disclosure. In fig. 9 and 10, open circles represent holes, and filled circles represent electrons.

Specifically, as shown in fig. 8, the flash memory cell MC 200 includes a memory transistor MS110 and a gate transistor MG 120 connected in series. The gate transistor MG 120 may perform a gate operation on the memory transistor MS 110. As shown in fig. 8, by controlling voltages applied to the source region (i.e., the first electrode S) of the memory transistor MS110, the gate electrode 116 of the memory transistor MS110, the gate electrode 123 of the gate transistor MG 120, and the drain region (i.e., the second electrode D) of the gate transistor MG 120, a write operation to the memory transistor MS110 can be achieved.

According to another embodiment of the present disclosure, the writing operation to the memory transistor MS110 may be performed through two steps, i.e., a first writing step and a second writing step, which are sequentially performed, respectively.

According to another embodiment of the present disclosure, when a write operation is performed on the flash memory cell MC 200, the P-well 102 of the flash memory cell MC 200 may be grounded or a negative voltage lower than a ground voltage may be applied.

Specifically, according to another embodiment of the present disclosure, as shown in fig. 9, a write operation is first performed on the memory transistor MS110 of the flash memory cell MC 200 through a first write step. At this time, the first write voltage VW1 is applied to the first electrode S, the second write voltage VW2 is applied to the second electrode D, the third write voltage VW3 is applied to the gate electrode 116 of the memory transistor MS110, and the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120.

According to an embodiment of the present disclosure, the first write voltage VW1 may be higher than a preset voltage, which is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the memory transistor MS 110. For example, in the flash memory cell MC 200 shown in fig. 7, the preset voltage may enable electrons to cross an electron barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 may be in the range of 3V to 6V. For example, according to an embodiment of the present disclosure, the first write voltage VW1 may be 4.4V. According to an embodiment of the present disclosure, the first write voltage VW1 may be provided by an external constant voltage source.

According to an embodiment of the present disclosure, the first and fourth write voltages VW1 and VW4 may be higher than the second write voltage VW2.

Further, according to the embodiment of the present disclosure, in the first writing step of the flash memory cell MC 200, the first to fourth writing voltages VW1 to VW4 cause both the memory transistor MS110 and the gate transistor MG 120 to be turned on.

Subsequently, according to an embodiment of the present disclosure, as shown in fig. 4, a write operation is then performed on the memory transistor MS110 of the flash memory cell MC 200 through the second write step. At this time, the first write voltage VW1 applied to the first electrode S, the second write voltage VW2 applied to the second electrode D, and the fourth write voltage VW4 applied to the gate electrode 123 of the gate transistor MG 120 remain unchanged, and the sixth write voltage VW6 is applied to the gate electrode 116 of the memory transistor MS 110. According to an embodiment of the present disclosure, the sixth write voltage VW6 may be greater than the third write voltage VW3. For example, as described above, the third write voltage VW3 may be 5.4V, and the sixth write voltage VW6 may be 6.2V.

Further, according to an embodiment of the present disclosure, during the second writing step of the flash memory cell MC 100, the first, second, sixth, and fourth writing voltages VW1, VW2, VW6, and VW4 cause both the memory transistor MS110 and the gate transistor MG 120 to be turned on.

The writing method according to another embodiment of the present disclosure is also based on a dual channel hot electron writing mechanism, and thus, for brevity, will not be described in further detail herein.

Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will understand that various modifications and changes may be made thereto without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims

1. A method of writing to a flash memory cell, the flash memory cell comprising:

a substrate including a deep well region and a well region disposed on the deep well region;

a memory transistor disposed on the well region and configured to store data, and

A gate transistor disposed on one side of the memory transistor in a horizontal direction on the well region, configured to perform a gate operation on the memory transistor,

Wherein the memory transistor and the gating transistor are connected in series,

Wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, a drain region of the gate transistor is connected to a second electrode of the flash memory cell,

The writing method comprises the following steps:

A first writing step of performing a writing operation on the memory transistor by applying a first writing voltage to the first electrode, a second writing voltage to the second electrode, a third writing voltage to a gate electrode of the memory transistor, and a fourth writing voltage to a gate electrode of the gate transistor, and

A second writing step of performing a writing operation on the memory transistor by applying the first writing voltage to the first electrode, applying the second writing voltage to the second electrode, applying a sixth writing voltage higher than the third writing voltage to a gate electrode of the memory transistor, and applying the fourth writing voltage to a gate electrode of the gate transistor,

Wherein the fourth write voltage is equal to or lower than a first power supply voltage, the second write voltage is equal to or higher than a second power supply voltage, the first write voltage is higher than a preset voltage, the third write voltage is higher than the first write voltage,

Wherein the first power supply voltage is higher than the second power supply voltage,

Wherein the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the memory transistor,

Wherein the first and fourth write voltages are higher than the second write voltage, and

Wherein during a write operation of the flash memory cell, both the storage transistor and the gating transistor are turned on.

2. A method of writing to a flash memory cell, the flash memory cell comprising:

a first storage transistor disposed on the well region and configured to store first data;

A second memory transistor disposed on the well region and configured to store second data, and

A gate transistor disposed between the first memory transistor and the second memory transistor in a horizontal direction on the well region, configured to isolate the first memory transistor and the second memory transistor and perform a gate operation on the first memory transistor and the second memory transistor,

Wherein the first memory transistor, the gating transistor and the second memory transistor are sequentially connected in series,

Wherein a source region of the first memory transistor is connected to a first electrode of the flash memory cell, a drain region of the second memory transistor is connected to a second electrode of the flash memory cell,

The writing method comprises the following steps:

A first writing step of performing a writing operation on the first memory transistor or the second memory transistor by applying a first writing voltage to the first electrode or the second electrode, applying a second writing voltage to the second electrode or the first electrode, applying a third writing voltage to a gate electrode of the first memory transistor or the second memory transistor, applying a fourth writing voltage to a gate electrode of the gate transistor, and applying a fifth writing voltage to a gate electrode of the second memory transistor or the first memory transistor, and

A second writing step of performing a writing operation on the first memory transistor or the second memory transistor by applying the first writing voltage to the first electrode or the second electrode, applying the second writing voltage to the second electrode or the first electrode, applying a sixth writing voltage higher than the third writing voltage to a gate electrode of the first memory transistor or the second memory transistor, applying the fourth writing voltage to a gate electrode of the gate transistor, and applying the fifth writing voltage to a gate electrode of the second memory transistor or the first memory transistor,

Wherein the preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors,

Wherein the first, fourth, and fifth write voltages are higher than the second write voltage, and

Wherein during a write operation of the flash memory cell, the first storage transistor, the second storage transistor, and the gating transistor are all turned on.

3. The writing method according to claim 1, wherein,

The first supply voltage is in the range of 0.8V to 5V,

The second power supply voltage is a ground voltage,

The first write voltage is in the range of 3V to 6V,

The third write voltage is in the range of 4V to 10V, and

The sixth write voltage is in the range of 5V to 12V.

4. The writing method according to claim 2, wherein,

The first supply voltage is in the range of 0.8V to 5V,

The second power supply voltage is a ground voltage,

The first write voltage is in the range of 3V to 6V,

The third write voltage is in the range of 4V to 10V,

The fifth write voltage is in the range of 3V to 8V, and

The sixth write voltage is in the range of 5V to 12V.

5. The writing method according to claim 1 or 2, wherein,

During a write operation of the flash memory cell, the second write voltage is connected to the second power supply voltage through a constant current load, and a current flowing between a first electrode and a second electrode of the flash memory cell is controlled by controlling a current of the constant current load.

6. The writing method according to claim 1 or 2, wherein,

During execution of the first writing step and the second writing step, a writing operation is performed on the first memory transistor or the second memory transistor by a channel hot carrier injection mechanism.

7. The writing method according to claim 1 or 2, wherein,

During a write operation of the flash memory cell, the charge injected into the storage medium layer of the storage transistor has a lower charge concentration on a side closer to the gate transistor and a higher charge concentration on a side farther from the gate transistor in the horizontal direction.

8. The writing method of claim 1 or 2, wherein the memory transistor is a charge trapping memory transistor, the gate dielectric stack of which comprises a tunnel oxide layer, a memory dielectric layer and a blocking oxide layer.

9. The writing method of claim 8, wherein the storage medium layer comprises a mono-or poly-oxide, a mono-or poly-nitride, a mono-or poly-oxynitride, a polysilicon or nanocrystalline material, or a combination thereof.

10. The writing method of claim 8, wherein the storage medium layer comprises a high-K material rich in charge traps.

11. The writing method of claim 8, wherein the tunnel oxide layer has a thickness of 1 to 15nm.

12. The writing method according to claim 1 or 2, further comprising:

a voltage equal to or lower than the second power supply voltage is applied to the well region.