CN118609635A - ONFI TESTCHIP built-in self-test method and device based on LFSR design - Google Patents

Abstract

The present invention discloses an ONFI TESTCHIP built-in self-test method and device based on LFSR design. Combining LFSR circuit and ECC verification method, multiple modes of test data (sequential, fixed, random) are selected based on MUX. LFSR generates a random number test sequence. In the write phase, LFSR generates data and transmits it to CONTROLLER; in the read phase, LFSR generates a comparison sequence to compare with the read-back data. In the sequential number and fixed number verification modes, the read and write data path from SRAMs to NAND FLASH is detected, and if the data is wrong, the error position is recorded. The present invention provides a test sequence with multiple modes to synchronously test the random combination of multiple test branches, realize segmented path detection and multi-path detection, save test cost and time, realize accurate positioning of the error position, and improve the testability and reliability of the system.

Description

ONFI TESTCHIP built-in self-test method and device based on LFSR design

Technical Field

The present invention relates to the field of storage read-write testing, and more specifically to an ONFITESTCHIP built-in self-test method and device based on LFSR design.

Background Art

With the development of various storage technologies, the system integration is improved and the area is increased, and its reliability faces greater and greater challenges. As the influence of factors such as material impurities, the complexity of the manufacturing process, and the temperature and voltage changes during the operation of the chip on reliability is becoming more and more obvious, testing is an important means to ensure the quality and reliability of chip products. At present, system testing has become specialized, and most integrated IP technologies mainly use self-built circuit testing solutions. However, with the rapid development of design, integration and technology, chip testing faces huge challenges such as resource limitations, rising costs, increased power consumption and the emergence of new fault types. For example, as the integration of chips becomes higher and higher, although the number of chip integrated cores continues to increase, the number of its I/O pins rarely increases, making it extremely difficult to access the internal circuit during testing. In addition, test power consumption will have an adverse effect on chip performance and reliability, and excessive power consumption will affect the quality and efficiency of chip testing. Therefore, with the increase in the number of integrated multi-complex IP cores, it is necessary to use a circuit that can save test costs, shorten test time, and improve the testability and reliability of the system to test the integrated IP chip, so as to compensate for the deviation caused by the above factors.

Summary of the invention

The invention overcomes the defects of the prior art and proposes an ONFI TESTCHIP built-in self-test method and device based on LFSR design.

In the present invention, ONFI (Open NAND Flash Interface) is an open NAND flash memory interface, and TESTCHIP (test chip) is a chip used to verify and test circuit design, which includes a logic generator module (Logic Generator), a controller IP (CONTROLLER) and a physical layer IP (PHY, used for communication connection between NAND FLASH and CONTROLLER). The logic circuit component of the present invention is mainly in the secondary module MEM WRAPPER in the submodule ONFI_CTRL_WRAP (same level as the register module ONFI_CTRL_TOP_REG) in the LogicGenerator module of ONFI TESTCHIP. The present invention has the following advantages: supports the generation of test vectors in multiple modes of fixed numbers, sequential numbers, and random numbers; supports synchronous testing of random combinations of multiple test branches; supports polling testing; supports that the test process can be interrupted at any time during fault diagnosis, accurate error reporting and positioning are performed, and the normal function of the circuit can be restarted.

The first aspect of the present invention provides an ONFI TESTCHIP built-in self-test method based on LFSR design, comprising:

S1: Based on the combination of LFSR circuit and ECC check, that is, the combination of LFSR and CRW_MEM_ECC, the test data sequence with different modes of sequential number, fixed number and random number is selected through MUX, and the data sources are DATA_IN and SEED;

S2: Set the seed value SEED and sequence number of the random number;

S3: Start random number LFSR detection to detect the data path of SRAMs-DMA_INTF interface-controller CONTROLLER used for normal read and write functions;

S4: When starting the random number test sequence, the external configuration data_select selects the lfsr random number test mode and inputs SEED. The SRAM used for the verification function selects the same seed value as the SRAM used for normal read and write functions according to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested; a write command is sent, and the controller CONTROLLER receives the instruction and operates. The SRAM that enters the read phase will receive the read signal rd_en sent by the direct access interface, and the corresponding random number test sequence lfsr_gen_data is generated through the LFSR rapid response. At this time, SEED is the seed value of the input LFSR, and rd/wr_en is the read and write enable required by the LFSR; then, the CONTROLLER processes the data mem_data_out based on the DMA_INTF in real time, and generates a write enable signal wr_en for the LFSR used for the verification function, which is used to generate the LFSR rapid response of the read back comparison sequence. The comparison data sequence lfsr_cmp_data is generated in quick response, and lfsr_cmp_data is compared with the data sequence rdbc_data processed in real time by CONTROLLER. The comparison is based on cmp logic. If the data is inconsistent, an error will be reported. The error signal lfsr_error will trigger the internal address generator ex/in_gen_data_addr to generate an address for storing the LFSR random number sequence and store the existing error data rdbc_data to the error SRAM. At the same time, the comparison data sequence lfsr_cmp_data generated by the corresponding SEED will also be written into the SRAM used for verification function to locate the error position of the data sequence. The error reporting process determines the SRAM error location by reading the seed value, and then reads the content of the error SRAM and compares it with the content in the verification SRAM to locate the specific error position. If rdbc_data and lfsr_cmp_data are consistent, the data will not be stored in SRAMs at this time;

S5: The sequential number and fixed number verification modes are used to detect the read and write data path from the normal read and write function SRAMs to the NANDFLASH. The SRAMs of the unwritten data part can be used as an error data storage pool. During the verification, the SRAMs used for normal read and write functions are randomly selected and used in combination and verified at the same time. A part of the SRAMs is used to write data, and a part of the SRAMs is used to store the data reported by the read error. If the verification does not report an error, the correct data is stored in the specified SRAMs for reading back. If the verification reports an error, the data written to the SRAMs is read and compared with the corresponding data stored in the error SRAMs to locate the specific error location;

S6: Start the sequential number/fixed number test sequence, externally configure data_select to select the sequential number/fixed number test mode, and input DATA_IN to the SRAM used for verification function, and externally send the write command and write data with the corresponding SRAMs external mapping first address. After the CONTROLLER receives the instruction operation, the SRAMs entering the read phase will receive the CONTROLLER's read request, take mem_data_out and transmit it to the non-volatile storage medium NAND FLASH through PHY, and the write data phase is completed; then, send a read command with the specified SRAMs external mapping first address. After receiving the instruction operation, the CONTROLLER reads back the data sequence rdbc_data from the NAND FLASH side, generates dam_addr and sends a write request to the specified SRAMs. At this time, the SRAM used for verification function receives a read request, reads out the comparison sequence lfsr_cmp_data stored in the processed read address mem_addr, and compares lfsr_cmp_data with the data from NAND through the cmp logic. The rdbc_data read back by the FLASH side is compared. If the data is inconsistent, an error is reported, and the error signal lfsr_error is reported. The error data is stored in the specified SRAMs. The error position of the data sequence is located by comparing the data read out of the write SRAMs with the corresponding data stored in the error SRAMs.

S7: In the above S4 and S6 processes, based on the user test plan, the ongoing test can be stopped by sending a stop command. If a read or write error occurs, the trigger is set to terminate the test;

S8: Based on the selection of different test modes, the SRAMs of MEM WRAPPER are tested and adapted through random combinations.

In this solution, in S2, the random number corresponding to the DATA_IN value is input from the outside, and the template pattern of the input data can be set.

In this solution, in S3, in the SRAMs-DMA_INTF interface, the DMA interface is used to provide high-speed data transmission between the SRAM and the CONTROLLER.

In this solution, in S4, for the input SEED, different seed values SEED can be selected corresponding to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested.

In this solution, in S6, the lfsr_cmp_data is compared with the rdbc_data read back from the NAND FLASH side through the cmp logic. If the data are inconsistent, an error is reported. If the data are consistent during the comparison process or no comparison is required, the address dma_addr returned by the DMA is selected, and the data is written to the specified SRAMs.

The second aspect of the present invention also provides an ONFI TESTCHIP built-in self-test device based on LFSR design, the device comprises: MEM WRAPPER, SRAM, LFSR circuit, ONFI flash memory interface, TESTCHIP test chip, the chip comprises a logic generation module Logic Generator, controller IP, physical layer IP; the device implements the following steps when running:

S1: Based on the combination of LFSR circuit and ECC check, that is, the combination of LFSR and CRW_MEM_ECC, the test data sequence with different modes of sequential number, fixed number and random number is selected through MUX, and the data sources are DATA_IN and SEED;

S2: Set the seed value SEED and sequence number of the random number;

S3: Start random number LFSR detection to detect the data path of SRAMs-DMA_INTF interface-controller CONTROLLER used for normal read and write functions;

S4: When starting the random number test sequence, the external configuration data_select selects the lfsr random number test mode and inputs SEED. The SRAM used for the verification function selects the same seed value as the SRAM used for normal read and write functions according to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested; a write command is sent, and the controller CONTROLLER receives the instruction and operates. The SRAM that enters the read phase will receive the read signal rd_en sent by the direct access interface, and the corresponding random number test sequence lfsr_gen_data is generated through the LFSR rapid response. At this time, SEED is the seed value of the input LFSR, and rd/wr_en is the read and write enable required by the LFSR; then, the CONTROLLER processes the data mem_data_out based on the DMA_INTF in real time, and generates a write enable signal wr_en for the LFSR used for the verification function, which is used to generate the LFSR rapid response of the read back comparison sequence. The comparison data sequence lfsr_cmp_data is generated in quick response, and lfsr_cmp_data is compared with the data sequence rdbc_data processed in real time by CONTROLLER. The comparison is based on cmp logic. If the data is inconsistent, an error will be reported. The error signal lfsr_error will trigger the internal address generator ex/in_gen_data_addr to generate an address for storing the LFSR random number sequence and store the existing error data rdbc_data to the error SRAM. At the same time, the comparison data sequence lfsr_cmp_data generated by the corresponding SEED will also be written into the SRAM used for verification function to locate the error position of the data sequence. The error reporting process determines the SRAM error location by reading the seed value, and then reads the content of the error SRAM and compares it with the content in the verification SRAM to locate the specific error position. If rdbc_data and lfsr_cmp_data are consistent, the data will not be stored in SRAMs at this time;

S5: The sequential number and fixed number verification modes are used to detect the read and write data path from the normal read and write function SRAMs to the NANDFLASH. The SRAMs of the unwritten data part can be used as an error data storage pool. During the verification, the SRAMs used for normal read and write functions are randomly selected and used in combination and verified at the same time. A part of the SRAMs is used to write data, and a part of the SRAMs is used to store the data reported by the read error. If the verification does not report an error, the correct data is stored in the specified SRAMs for reading back. If the verification reports an error, the data written to the SRAMs is read and compared with the corresponding data stored in the error SRAMs to locate the specific error location;

S6: Start the sequential number/fixed number test sequence, externally configure data_select to select the sequential number/fixed number test mode, and input DATA_IN to the SRAM used for verification function, and externally send the write command and write data with the corresponding SRAMs external mapping first address. After the CONTROLLER receives the instruction operation, the SRAMs entering the read phase will receive the CONTROLLER's read request, take mem_data_out and transmit it to the non-volatile storage medium NAND FLASH through PHY, and the write data phase is completed; then, send a read command with the specified SRAMs external mapping first address. After receiving the instruction operation, the CONTROLLER reads back the data sequence rdbc_data from the NAND FLASH side, generates dam_addr and sends a write request to the specified SRAMs. At this time, the SRAM used for verification function receives a read request, reads out the comparison sequence lfsr_cmp_data stored in the processed read address mem_addr, and compares lfsr_cmp_data with the data from NAND through the cmp logic. The rdbc_data read back by the FLASH side is compared. If the data is inconsistent, an error is reported, and the error signal lfsr_error is reported. The error data is stored in the specified SRAMs. The error position of the data sequence is located by comparing the data read out of the write SRAMs with the corresponding data stored in the error SRAMs.

S7: In the above S4 and S6 processes, based on the user test plan, the ongoing test can be stopped by sending a stop command. If a read or write error occurs, the trigger is set to terminate the test;

S8: Based on the selection of different test modes, the SRAMs of MEM WRAPPER are tested and adapted through random combinations.

The present invention can achieve the following technical effects:

The present invention is based on the combination of LFSR circuit and ECC check, supports the generation of test vectors in multiple modes of fixed numbers, sequential numbers, and random numbers, and effectively improves the test effect;

The present invention supports synchronous testing of random combinations of multiple test branches based on LFSR circuits and SRAM multiplexing, and supports segmented and multi-path testing, and does not require additional verification detection memory as a storage pool to store error data, thereby reducing testing costs;

The present invention designs a verification circuit based on an LFSR circuit and a DMA operation mechanism to support polling testing, thereby effectively improving the test effect;

The present invention supports the design of the fault detection result output circuit based on the LFSR circuit and the DMA operation mechanism, and supports that the test process can be interrupted at any time during fault diagnosis, and accurate error reporting and positioning can be performed, and the normal function of the circuit can be restarted, which effectively improves the test reliability and system adaptability.

The invention discloses an ONFI TESTCHIP built-in self-test method and device based on LFSR design. Combining LFSR circuit and ECC verification method, multiple modes of test data (sequential, fixed, random) are selected based on MUX. LFSR generates a random number test sequence for read and write test between SRAM and CONTROLLER. In the write phase, LFSR generates data and transmits it to CONTROLLER; in the read phase, LFSR generates a comparison sequence to compare with the read-back data. In the sequential number and fixed number verification modes, the read and write data path from SRAMs to NAND FLASH is detected. SRAMs can be used in combination by random selection and verified simultaneously. If the data is wrong, the error position is recorded. The test process supports multiple polling tests, and the test process is controlled by a stop command. The invention provides a test sequence with multiple modes to synchronously test the random combination of multiple test branches, realize segmented path detection and multi-path detection, save test cost and time, realize accurate positioning of error positions, and improve the testability and reliability of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of a built-in self-test device according to the present invention.

DETAILED DESCRIPTION

In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

FIG. 1 shows a schematic diagram of a built-in self-test device according to the present invention.

Integrated circuits can be divided into analog integrated circuits and digital circuits according to the types of signals processed by the circuits. The present invention is mainly used to test digital integrated circuits to verify whether their logic functions and timing meet specific regulations.

The linear feedback shift register (LFSR) is the most basic standard module structure in the internal test circuit, which has the advantages of high speed, small consumption of logic gates, and versatility. The present invention is mainly based on the advantages of LFSR in optimizing test vector compression and shortening test application time, designs and configures the test circuit, provides a multi-mode, low-power and high-speed ONFITESTCHIP built-in self-test method, provides a multi-mode test sequence to synchronously test the random combination of multiple test branches, realizes segmented path detection and multi-path detection, can save test costs, shorten test time, and improve the testability and reliability of the system.

Among them, ONFI (Open NAND Flash Interface) is an open NAND flash memory interface, and TESTCHIP (test chip) is a chip used to verify and test circuit design. The chip includes a logic generation module (Logic Generator), a controller IP (CONTROLLER) and a physical layer IP (PHY, used for communication between NAND FLASH and CONTROLLER). The logic circuit component of the present invention is mainly in the secondary module MEM WRAPPER in the submodule ONFI_CTRL_WRAP (same level as the register module ONFI_CTRL_TOP_REG) in the LogicGenerator module of ONFI TESTCHIP. The present invention has the following advantages: supports generation of test vectors in various modes such as fixed numbers, sequential numbers and random numbers; supports synchronous testing of random combinations of multiple test branches; supports segmented path detection and can meet multi-path detection; supports polling testing; supports interruption of the test process at any time during fault diagnosis, accurate error reporting and positioning, and the normal function of the circuit can be restarted; in addition, this detection circuit does not require additional static read-write memory (SRAM) used for verification function as a storage pool to store error data.

As shown in FIG1 , it is a schematic diagram of a built-in self-test device of the present invention;

The device components of the present invention include instantiating the corresponding LFSR circuit in the packaged MEM WRAPPE (memory package), and making corresponding random sequence generation mechanisms (LFSR) and internal address generators (ex/in_gen_data_addr) according to different functional applications of SRAM. In addition, it is necessary to add a comparison logic circuit and a multiplexer (MUX) as a switch for selecting different data sequence test modes, and to add a circuit design for a mechanism of error reporting and data storage when an error occurs to facilitate error detection, identification and positioning. The test implementation method of the present invention is as follows:

S1: Based on the combination of LFSR circuit and ECC check, that is, the combination of LFSR and CRW_MEM_ECC, the test data sequence with different modes of sequential number, fixed number and random number is selected through MUX, and the data sources are DATA_IN and SEED;

S2: Set the seed value SEED and sequence number of the random number;

S3: Start random number LFSR detection to detect the data path of SRAMs-DMA_INTF interface-controller CONTROLLER used for normal read and write functions;

S4: When starting the random number test sequence, the external configuration data_select selects the lfsr random number test mode and inputs SEED. Different seed values can be selected for the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested. The SRAM used for the verification function selects the same seed value as the SRAM used for normal read and write functions according to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested; a write command is sent, and the controller CONTROLLER receives the instruction and enters the read phase. The SRAM will receive the read signal rd_en sent by the direct access interface. At this time, the corresponding random number test sequence lfsr_gen_data is generated through the LFSR in a rapid response. At this time, SEED is the seed value input to the LFSR, and rd/wr_en is the read and write enable required by the LFSR; then, the CONTROLLER processes the data mem_data_out based on the DMA_INTF in real time, and generates a write signal for the LFSR used for the verification function. Enable signal wr_en, which is used to generate the LFSR read-back comparison sequence, to quickly respond and generate the comparison data sequence lfsr_cmp_data, and compare lfsr_cmp_data with the data sequence rdbc_data processed immediately by CONTROLLER. The comparison is based on cmp logic. If the data is inconsistent, an error will be reported. The error signal lfsr_error will trigger the internal address generator ex/in_gen_data_addr to generate an address for storing the LFSR random number sequence and store the existing error data rdbc_data to the error SRAM. At the same time, the comparison data sequence lfsr_cmp_data generated by the corresponding SEED will also be written into the SRAM used for verification function to locate the error position of the data sequence. The error reporting process determines the SRAM error location by reading the seed value, and then reads the content of the error SRAM and compares it with the content in the verification SRAM to locate the specific error position. If rdbc_data and lfsr_cmp_data are consistent, the data will not be stored in the SRAMs at this time.

S5: The sequential number and fixed number verification modes are used to detect the read and write data path from the normal read and write function SRAMs to the NANDFLASH. The SRAMs of the unwritten data part can be used as an error data storage pool. During the verification, the SRAMs used for normal read and write functions are randomly selected and used in combination and verified at the same time. A part of the SRAMs is used to write data, and a part of the SRAMs is used to store the data reported by the read error. If the verification does not report an error, the correct data is stored in the specified SRAMs for reading back. If the verification reports an error, the data written to the SRAMs is read and compared with the corresponding data stored in the error SRAMs to locate the specific error location;

S6: Start the sequential number/fixed number test sequence, externally configure data_select to select the sequential number/fixed number test mode, and input DATA_IN to the SRAM used for verification function, and externally send the write command and write data with the corresponding SRAMs external mapping first address. After the CONTROLLER receives the instruction operation, the SRAMs entering the read phase will receive the CONTROLLER's read request, take mem_data_out and transmit it to the non-volatile storage medium NAND FLASH through PHY, and the write data phase is completed; then, send a read command with the specified SRAMs external mapping first address. After receiving the instruction operation, the CONTROLLER reads back the data sequence rdbc_data from the NAND FLASH side, generates dam_addr and sends a write request to the specified SRAMs. At this time, the SRAM used for verification function receives a read request, reads out the comparison sequence lfsr_cmp_data stored in the processed read address mem_addr, and compares lfsr_cmp_data with the data from NAND through the cmp logic. The rdbc_data read back by the FLASH side is compared. If the data is inconsistent, an error is reported, the error signal lfsr_error is reported, and the error data is stored in the specified SRAMs. The data written to the SRAMs is read and compared with the corresponding data stored in the error SRAMs to locate the error position of the data sequence. If the data is consistent or no comparison is required, the address dma_addr returned by the DMA is selected, and the data is written to the specified SRAMs.

S7: In the above S4 and S6 processes, based on the user test plan, the ongoing test can be stopped by sending a stop command. If a read or write error occurs, the trigger is set to terminate the test;

S8: Based on the selection of different test modes, the SRAMs of MEM WRAPPER are tested and adapted through random combinations.

It should be noted that the random number corresponding to the DATA_IN value is input from the outside, and the template pattern of the input data can be set.

In the SRAMs-DMA_INTF interface, the DMA interface is used to provide high-speed data transmission between the SRAM and the CONTROLLER.

Sequential and fixed number check modes do not require additional checksum memory as a storage pool to store error data, because when using fixed number/sequential number error detection logic, the SRAMs in the unwritten data portion can be used as an error data storage pool.

In the SRAM input DATA_IN used for verification function, the input data pattern can be selected independently. In the external sending of the write command and write data with the corresponding SRAMs external mapping first address, the corresponding data is consistent with the data template of the SRAM input used for verification function.

In step S7, based on the characteristics of DMA, the test sequence is polled to verify the reliability of the test circuit after multiple reads and writes, thereby increasing the error detection coverage. Moreover, stopping the circuit test operation does not affect the subsequent normal function start of the test circuit.

According to the selection of different test modes, the SRAMs of MEM WRAPPER can be randomly combined, and the circuit reliability of the randomly combined SRAMs to NAND FLASH can be tested at the same time. The SRAMs-DMA_INTF-CONTROLLER data path can also be tested, supporting segmented path detection and meeting multi-path detection. This feasible operation helps to improve detection efficiency and increase detection coverage.

User test plans can selectively stop tests based on user settings.

The seed value (SEED) is input externally and can be changed.

The ONFI TESTCHIP built-in self-test method of the LFSR circuit design of the present invention adopts the characteristics of small logic gates, simple structure and versatility, can meet the test vector generation of multiple modes, and supports flexible combination of random parallel testing of different branch circuits, supports segmented path detection, meets multi-path detection, and does not require additional verification detection memory as a storage pool to store error data, can perform polling test operations, support stopping at any time without affecting the normal function of the circuit and restarting, and supports accurate error reporting and positioning. While meeting the design indicators, the flexible design can save test costs, shorten test time, and improve the testability and reliability of the system circuit.

The second aspect of the present invention provides an ONFI TESTCHIP built-in self-test device based on LFSR design, characterized in that the device includes: MEM WRAPPER, SRAM, LFSR circuit, ONFI flash memory interface, TESTCHIP test chip, the chip includes a logic generation module Logic Generator, controller IP, physical layer IP; when the device is running, the above steps S1 to S8 are implemented.

The invention discloses an ONFI TESTCHIP built-in self-test method and device based on LFSR design. Combining LFSR circuit and ECC verification method, multiple modes of test data (sequential, fixed, random) are selected based on MUX. LFSR generates a random number test sequence for read and write test between SRAM and CONTROLLER. In the write phase, LFSR generates data and transmits it to CONTROLLER; in the read phase, LFSR generates a comparison sequence to compare with the read-back data. In the sequential number and fixed number verification modes, the read and write data path from SRAMs to NAND FLASH is detected. SRAMs can be used in combination by random selection and verified simultaneously. If the data is wrong, the error position is recorded. The test process supports multiple polling tests, and the test process is controlled by a stop command. The invention provides a test sequence with multiple modes to synchronously test the random combination of multiple test branches, realize segmented path detection and multi-path detection, save test cost and time, realize accurate positioning of error positions, and improve the testability and reliability of the system.

In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

A person skilled in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, etc. Various media that can store program codes.

Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims (10)

1. An ONFI TESTCHIP built-in self-test method based on LFSR design, characterized by comprising: S1: Based on the combination of LFSR circuit and ECC check, that is, the combination of LFSR and CRW_MEM_ECC, the test data sequence with different modes of sequential number, fixed number and random number is selected through MUX, and the data sources are DATA_IN and SEED; S2: Set the seed value SEED and sequence number of the random number; S3: Start random number LFSR detection to detect the data path of SRAMs-DMA_INTF interface-controller CONTROLLER used for normal read and write functions; S4: When starting the random number test sequence, the external configuration data_select selects the lfsr random number test mode and inputs SEED. The SRAM used for the verification function selects the same seed value as the SRAM used for normal read and write functions according to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested; a write command is sent, and the controller CONTROLLER receives the instruction and operates. The SRAM that enters the read phase will receive the read signal rd_en sent by the direct access interface, and the corresponding random number test sequence lfsr_gen_data is generated through the LFSR rapid response. At this time, SEED is the seed value of the input LFSR, and rd/wr_en is the read and write enable required by the LFSR; then, the CONTROLLER processes the data mem_data_out based on the DMA_INTF in real time, and generates a write enable signal wr_en for the LFSR used for the verification function, which is used to generate the LFSR rapid response of the read back comparison sequence Generate a comparison data sequence lfsr_cmp_data, compare lfsr_cmp_data with the data sequence rdbc_data processed in real time by CONTROLLER, the comparison is based on cmp logic, if the data is inconsistent, an error will be reported, the error signal lfsr_error will trigger the internal address generator ex/in_gen_data_addr to generate an address for storing the LFSR random number sequence and store the existing error data rdbc_data to the error SRAM, at the same time, the comparison data sequence lfsr_cmp_data generated by the corresponding SEED will also be written into the SRAM used for verification function to locate the error position of the data sequence, the error position of the data sequence is determined by reading the seed value to determine the SRAM error position, and then read the content of the error SRAM and compare it with the content in the verification SRAM to locate the specific error position, if rdbc_data and lfsr_cmp_data are consistent, the data will not be stored in SRAMs at this time; S5: The sequential number and fixed number verification modes are used to detect the read and write data path from the SRAMs with normal read and write functions to the NANDFLASH. The SRAMs with no data written are used as error data storage pools. During verification, the SRAMs used for normal read and write functions are randomly selected and used in combination and verified simultaneously. A part of the SRAMs is used to write data, and a part of the SRAMs is used to store the data reported as errors when reading. If the verification does not report an error, the correct data is stored in the specified SRAMs for reading back. If the verification reports an error, the data written into the SRAMs is read and compared with the corresponding data stored in the error SRAMs for reading back to locate the specific error location. S6: Start the sequential number/fixed number test sequence, externally configure data_select to select the sequential number/fixed number test mode, and input DATA_IN to the SRAM used for verification function, and externally send the write command and write data with the corresponding SRAMs external mapping first address. After the CONTROLLER receives the instruction operation, the SRAMs entering the read phase will receive the CONTROLLER's read request, take mem_data_out and transmit it to the non-volatile storage medium NAND FLASH through PHY, and the write data phase is completed; then, send a read command with the specified SRAMs external mapping first address. After receiving the instruction operation, the CONTROLLER reads back the data sequence rdbc_data from the NAND FLASH side, generates dam_addr and sends a write request to the specified SRAMs. At this time, the SRAM used for verification function receives a read request, reads out the comparison sequence lfsr_cmp_data stored in the processed read address mem_addr, and compares lfsr_cmp_data with the data from NAND through the cmp logic. The rdbc_data read back by the FLASH side is compared. If the data is inconsistent, an error is reported, and the error signal lfsr_error is reported. The error data is stored in the specified SRAMs. The error position of the data sequence is located by comparing the data read out of the write SRAMs with the corresponding data stored in the error SRAMs. S7: In the above S4 and S6 processes, based on the user test plan, the ongoing test is stopped by sending a stop command. If a read or write error occurs, the trigger is set to terminate the test; S8: Based on the selection of different test modes, the SRAMs of MEM WRAPPER are tested and adapted through random combinations. 2. The ONFI TESTCHIP built-in self-test method based on LFSR design according to claim 1, characterized in that, in S2, the random number corresponding to the DATA_IN value is input from the outside, and the template pattern of the input data is set by the user. 3. The ONFI TESTCHIP built-in self-test method based on LFSR design according to claim 1, characterized in that, in S3, in the SRAMs-DMA_INTF interface, the DMA interface is used to provide high-speed data transmission between the SRAM and the CONTROLLER. 4. The ONFI TESTCHIP built-in self-test method based on LFSR design according to claim 1, characterized in that, in S4, for the input SEED, different seed values SEED are preset and selected corresponding to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested. 5. The ONFI TESTCHIP built-in self-test method based on LFSR design according to claim 1, characterized in that, in S6, the lfsr_cmp_data is compared with the rdbc_data read back from the NAND FLASH side through the cmp logic, and if the data are inconsistent, an error is reported; if the data are consistent during the comparison process or no comparison is required, the address dma_addr returned by the DMA is selected, and the data is written into the specified SRAMs. 6. An ONFI TESTCHIP built-in self-test device based on LFSR design, characterized in that the device comprises: MEMWRAPPER, SRAM, LFSR circuit, ONFI flash memory interface, TESTCHIP test chip, the chip includes a logic generator module Logic Generator, controller IP, physical layer IP; the device implements the following steps when running: S1: Based on the combination of LFSR circuit and ECC check, that is, the combination of LFSR and CRW_MEM_ECC, the test data sequence with different modes of sequential number, fixed number and random number is selected through MUX, and the data sources are DATA_IN and SEED; S2: Set the seed value SEED and sequence number of the random number; S3: Start random number LFSR detection to detect the data path of SRAMs-DMA_INTF interface-controller CONTROLLER used for normal read and write functions; S4: When starting the random number test sequence, the external configuration data_select selects the lfsr random number test mode and inputs SEED. The SRAM used for the verification function selects the same seed value as the SRAM used for normal read and write functions according to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested; a write command is sent, and the controller CONTROLLER receives the instruction and operates. The SRAM that enters the read phase will receive the read signal rd_en sent by the direct access interface, and the corresponding random number test sequence lfsr_gen_data is generated through the LFSR rapid response. At this time, SEED is the seed value of the input LFSR, and rd/wr_en is the read and write enable required by the LFSR; then, the CONTROLLER processes the data mem_data_out based on the DMA_INTF in real time, and generates a write enable signal wr_en for the LFSR used for the verification function, which is used to generate the LFSR rapid response of the read back comparison sequence Generate a comparison data sequence lfsr_cmp_data, compare lfsr_cmp_data with the data sequence rdbc_data processed in real time by CONTROLLER, the comparison is based on cmp logic, if the data is inconsistent, an error will be reported, the error signal lfsr_error will trigger the internal address generator ex/in_gen_data_addr to generate an address for storing the LFSR random number sequence and store the existing error data rdbc_data to the error SRAM, at the same time, the comparison data sequence lfsr_cmp_data generated by the corresponding SEED will also be written into the SRAM used for verification function to locate the error position of the data sequence, the error position of the data sequence is determined by reading the seed value to determine the SRAM error position, and then read the content of the error SRAM and compare it with the content in the verification SRAM to locate the specific error position, if rdbc_data and lfsr_cmp_data are consistent, the data will not be stored in SRAMs at this time; S5: The sequential number and fixed number verification modes are used to detect the read and write data path from the SRAMs with normal read and write functions to the NANDFLASH. The SRAMs with no data written are used as error data storage pools. During verification, the SRAMs used for normal read and write functions are randomly selected and used in combination and verified simultaneously. A part of the SRAMs is used to write data, and a part of the SRAMs is used to store the data reported as errors when reading. If the verification does not report an error, the correct data is stored in the specified SRAMs for reading back. If the verification reports an error, the data written into the SRAMs is read and compared with the corresponding data stored in the error SRAMs for reading back to locate the specific error location. S6: Start the sequential number/fixed number test sequence, externally configure data_select to select the sequential number/fixed number test mode, and input DATA_IN to the SRAM used for verification function, and externally send the write command and write data with the corresponding SRAMs external mapping first address. After the CONTROLLER receives the instruction operation, the SRAMs entering the read phase will receive the CONTROLLER's read request, take mem_data_out and transmit it to the non-volatile storage medium NAND FLASH through PHY, and the write data phase is completed; then, send a read command with the specified SRAMs external mapping first address. After receiving the instruction operation, the CONTROLLER reads back the data sequence rdbc_data from the NAND FLASH side, generates dam_addr and sends a write request to the specified SRAMs. At this time, the SRAM used for verification function receives a read request, reads out the comparison sequence lfsr_cmp_data stored in the processed read address mem_addr, and compares lfsr_cmp_data with the data from NAND through the cmp logic. The rdbc_data read back by the FLASH side is compared. If the data is inconsistent, an error is reported, and the error signal lfsr_error is reported. The error data is stored in the specified SRAMs. The error position of the data sequence is located by comparing the data read out of the write SRAMs with the corresponding data stored in the error SRAMs. S7: In the above S4 and S6 processes, based on the user test plan, the ongoing test is stopped by sending a stop command. If a read or write error occurs, the trigger is set to terminate the test; S8: Based on the selection of different test modes, the SRAMs of MEM WRAPPER are tested and adapted through random combinations. 7. The ONFI TESTCHIP built-in self-test device based on LFSR design according to claim 6, characterized in that, in S2, the random number corresponding to the DATA_IN value is input from the outside, and the template pattern of the input data is set by the user. 8. The ONFI TESTCHIP built-in self-test device based on LFSR design according to claim 6, characterized in that, in S3, in the SRAMs-DMA_INTF interface, the DMA interface is used to provide high-speed data transmission between the SRAM and the CONTROLLER. 9. The ONFI TESTCHIP built-in self-test device based on LFSR design according to claim 6, characterized in that, in S4, for the input SEED, different seed values SEED are preset and selected corresponding to the SRAM-DMA_INTF interface-controller CONTROLLER path to be tested. 10. The ONFI TESTCHIP built-in self-test device based on LFSR design according to claim 6, characterized in that, in S6, the lfsr_cmp_data is compared with the rdbc_data read back from the NAND FLASH side through the cmp logic, and if the data are inconsistent, an error is reported; if the data are consistent during the comparison process or no comparison is required, the address dma_addr returned by the DMA is selected, and the data is written into the specified SRAMs.