CN118099152A - GaN device packaging structure and packaging method thereof - Google Patents
GaN device packaging structure and packaging method thereof Download PDFInfo
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- CN118099152A CN118099152A CN202211493013.8A CN202211493013A CN118099152A CN 118099152 A CN118099152 A CN 118099152A CN 202211493013 A CN202211493013 A CN 202211493013A CN 118099152 A CN118099152 A CN 118099152A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 172
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000003466 welding Methods 0.000 claims abstract description 71
- 238000000605 extraction Methods 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- 229910052709 silver Inorganic materials 0.000 claims description 16
- 239000004332 silver Substances 0.000 claims description 16
- 238000012546 transfer Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 239000000919 ceramic Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011133 lead Substances 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 25
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 85
- 229910002601 GaN Inorganic materials 0.000 description 83
- 239000000463 material Substances 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 20
- 238000010586 diagram Methods 0.000 description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 13
- 239000004020 conductor Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000012858 packaging process Methods 0.000 description 12
- 229910052759 nickel Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
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- 230000000694 effects Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for individual devices of subclass H10D
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L2224/81 - H01L2224/86
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a GaN device packaging structure and a packaging method thereof, wherein the GaN device packaging structure comprises a packaging substrate, a chip layer, a conductive clamping piece, a welding layer and a packaging layer, wherein the packaging substrate comprises a dielectric layer, a conductive layer and a conductive column, and the conductive layer positioned on the upper surface of the dielectric layer comprises a first grid electrode region, a source electrode region, a drain electrode region, a second grid electrode region and a cascade electrode region; the chip layer is positioned above the packaging substrate and comprises a GaN HEMT chip and a MOS chip which are arranged at intervals, and the front surfaces of the GaN HEMT chip and the MOS chip are respectively provided with a first grid electrode, a first source electrode, a first drain electrode, a second grid electrode and a second source electrode which are respectively and electrically connected with the corresponding electrode areas of the conducting layer through welding layers; the conductive clamping piece is electrically connected with the cascade electrode area and the second drain electrode through the welding layer; the encapsulation layer covers the exposed surface of the chip layer. According to the invention, the device electrode is led out through the combination of the packaging substrate and the conductive clamping piece, so that the heat dissipation capacity and the current capacity of the packaging structure are improved.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a GaN device packaging structure and a packaging method thereof.
Background
The power semiconductor is a core device for power electronic and electric energy conversion and circuit control, and in recent years, power devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and the like rapidly develop towards the direction of high power density, but silicon-based devices have the upper limit, and the third-generation semiconductor gallium nitride (GaN) has wide application prospect in the fields of high-temperature, high-voltage, high-frequency and high-power electronic power devices because the third-generation semiconductor gallium nitride (GaN) has the characteristics of high breakdown electric field, high saturated electron velocity, high thermal conductivity, high electron density, high mobility and the like.
The GaN High Electron Mobility Transistor (HEMT) device is one of the future development directions of replacing silicon-based MOSFETs because of high electric energy conversion efficiency, and has two development directions of an enhanced GaN HEMT and a depletion GaN HEMT at present, wherein the enhanced GaN HEMT has a low threshold Value (VTH), and can be started by mistake and has low reliability in actual use, while the depletion GaN HEMT has high reliability, but is a normally-on device, can not be used in an actual circuit, and needs to be matched with a low-voltage silicon-based MOSFET (MOS for short) to form a GaN device with a common-source common-gate cascade structure (Cascode), so that the GaN device meets the actual use.
At present, the packaging of the GaN device with the Cascode structure (Cascode) is generally packaged by adopting a wire bonding packaging method, as shown in fig. 1, the packaging structure of the GaN device is schematically shown in the wire bonding packaging, and the GaN device comprises a substrate 01, a dielectric layer 011, a conductive layer 012, a chip layer 02, a GaN HEMT chip 021, a MOS chip 022 and a metal lead 03, but in the packaging process, the precision of the wire bonding process is low, the requirement of some high-reliability application environments is not met, the packaging resistance of the packaged packaging structure is high, the packaged structure is not suitable for a high-current use environment, the heat dissipation performance is poor, and the heat dissipation requirement of a high-power device is not met. In addition, the packaging structure of the lead bonding package has high inductance and mutual inductance due to the fact that the metal leads are more and distributed densely, and cannot be used at high frequency, so that the working efficiency of the whole machine is affected.
Therefore, there is an urgent need to find a GaN device package structure that improves the reliability of the package structure and reduces the package resistance, inductance, and mutual inductance of the package structure.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a GaN device packaging structure and a packaging method thereof, which are used for solving the problems of low process precision, high packaging resistance, and high inductance and mutual inductance of the GaN device packaging structure in the prior art.
To achieve the above and other related objects, the present invention provides a GaN device package structure comprising:
The packaging substrate comprises a dielectric layer, a conductive layer positioned on the upper surface and the lower surface of the dielectric layer and a conductive column penetrating through the dielectric layer and electrically connected with the conductive layer, wherein the conductive layer positioned on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region and a cascade electrode region;
The chip layer is positioned above the packaging substrate and comprises at least one GaN HEMT chip and at least one MOS chip which are arranged at intervals, the front surface of the GaN HEMT chip is provided with a first grid electrode positioned above the first grid electrode region, a first source electrode positioned above the cascade electrode region and a first drain electrode positioned above the drain electrode region, the front surface of the MOS chip is provided with a second grid electrode positioned above the second grid electrode region and a second source electrode positioned above the source electrode region, and the back surface of the MOS chip is provided with a second drain electrode;
A conductive clip, two ends of which are positioned above the second drain electrode and the cascade electrode region;
The welding layer is respectively positioned between the first grid electrode region and the first grid electrode, between the cascade electrode region and the first source electrode, between the first drain electrode and the drain electrode region, between the second grid electrode region and the second grid electrode, between the source electrode region and the second source electrode, between the second drain electrode and the conductive clamping piece, and between the conductive clamping piece and the cascade electrode region, and forms an electric connection structure;
And the packaging layer covers the chip layer and the exposed surface of the packaging substrate.
Optionally, the package substrate includes a direct copper-coated ceramic substrate, a direct copper-coated ceramic substrate.
Optionally, the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region, and a third electrode region.
Optionally, the first gate region is electrically connected to the first electrode region through the conductive pillar, the source region is electrically connected to the first electrode region through the conductive pillar, the first drain region is electrically connected to the second electrode region through the conductive pillar, and the second gate region is electrically connected to the third electrode region through the conductive pillar.
Optionally, the material of the soldering layer includes at least one of gold, silver, tin, lead, and indium.
Optionally, an integrated passive device and an extraction electrode for extracting the passive device are also arranged in the GaN HEMT chip; and a transfer electrode area is also arranged in the conductive layer on the upper surface of the dielectric layer.
Optionally, the upper surface of the switching electrode region is provided with the welding layer, the conductive clamping piece is located above the welding layer on the switching electrode region, the extraction electrode is located above the welding layer on the switching electrode region, and the conductive clamping piece and the extraction electrode form an electrical connection structure through the welding layer and the switching electrode region.
The invention also provides a packaging method of the GaN device packaging structure, which comprises the following steps:
Providing a packaging substrate, wherein the packaging substrate comprises a dielectric layer, a conductive layer positioned on the upper surface and the lower surface of the dielectric layer and a conductive column penetrating through the dielectric layer and electrically connected with the conductive layer, and the conductive layer positioned on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region and a cascade electrode region;
Providing a chip layer, wherein the chip layer comprises at least one GaN HEMT chip and at least one MOS chip, the front surface of the GaN HEMT chip is provided with a first grid, a first source electrode and a first drain electrode, the front surface of the MOS chip is provided with a second grid and a second source electrode, and the back surface of the MOS chip is provided with a second drain electrode;
Forming a welding layer on the upper surfaces of the first grid electrode region, the source electrode region, the drain electrode region, the second grid electrode region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode;
The GaN HEMT chip and the MOS chip are arranged on the upper surface of the packaging substrate at intervals, the first grid electrode is arranged above the welding layer on the first grid electrode region, the first source electrode is arranged above the welding layer on the cascade electrode region, the first drain electrode is arranged above the welding layer on the drain electrode region, the second grid electrode is arranged above the welding layer on the second grid electrode region, and the second source electrode is arranged above the welding layer on the source electrode region;
Forming a conductive clamping piece with two ends respectively positioned above the second drain electrode and the welding layer on the cascade electrode zone above the MOS chip, and processing the packaging structure after the conductive clamping piece is formed to form an electric connection structure;
forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer.
Optionally, the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region and a third electrode region, where the first gate region is electrically connected to the first electrode region through the conductive pillar, the source region is electrically connected to the first electrode region through the conductive pillar, the drain region is electrically connected to the second electrode region through the conductive pillar, and the second gate region is electrically connected to the third electrode region through the conductive pillar.
Optionally, an integrated passive device and an extraction electrode for extracting the passive device are also arranged in the GaN HEMT chip; and a transfer electrode region is further arranged in the conductive layer on the upper surface of the dielectric layer, the upper surface of the transfer electrode region is provided with the welding layer, the conductive clamping piece is contacted with the upper surface of the welding layer on the transfer electrode region, the extraction electrode is contacted with the upper surface of the welding layer on the transfer electrode region, and the conductive clamping piece forms an electric connection structure with the extraction electrode through the welding layer and the transfer electrode region.
As described above, the GaN device packaging structure and the packaging method thereof lead out the electrode of the packaging structure through the combination of the packaging substrate and the conductive clamping piece, and the conductive clamping piece is utilized to replace the metal lead, so that the problems of bonding damage and cold joint caused by the wire bonding packaging process are avoided, the packaging resistance of the packaging structure is reduced, the current capacity and the reliability of the device are improved, meanwhile, the densely-distributed metal lead is not required to be welded, the inductance and the mutual inductance of the packaging structure are reduced, the application frequency of the packaging structure is improved, the packaging structure meets the working requirement of a high-frequency application end, the working efficiency of the application end is improved, and the heat conductivity coefficients of the conductive layer and the dielectric layer are higher than those of the packaging layer, so that the heat dissipation capacity of the packaging structure is improved. In addition, in the packaging process, the welding layer is formed on the exposed surface of each electrode of the chip layer and the upper surfaces of the first grid electrode region, the source electrode region, the drain electrode region, the second grid electrode region and the cascade electrode region respectively, the welding layer is utilized to achieve the effect of automatic alignment after solidification, high-precision packaging is achieved, the welding layer is respectively formed by utilizing two contact surfaces at the electric connection position, welding cavities in the welding layer solidification process are reduced, packaging stress in the packaging process is reduced, and as the packaging substrate guides the electrode of the packaging structure to the lower surface of the packaging substrate through the conductive column, the packaging substrate can be compatible with patch type packaging, the size of the packaging structure can be adjusted according to the requirements of clients and the positions of the electrode positioned on the lower surface of the packaging substrate, the requirements of the clients are met, and the packaging substrate has high industrial utilization value.
Drawings
Fig. 1 shows a schematic diagram of a GaN device package structure of a wire-bond package.
Fig. 2 is a process flow diagram of a packaging method of the GaN device packaging structure of the present invention.
Fig. 3 is a schematic perspective view of a package substrate of a packaging method of the GaN device package structure of the present invention.
Fig. 4 is a schematic cross-sectional view of a package substrate along the Y-direction of the packaging method of the GaN device package structure of the invention.
Fig. 5 is a schematic structural diagram of a dielectric layer of a packaging method of the GaN device packaging structure of the present invention.
Fig. 6 is a schematic structural diagram of the upper surface of a package substrate of the packaging method of the GaN device package structure of the present invention.
Fig. 7 is a schematic view showing the structure of the lower surface of the package substrate of the packaging method of the GaN device package structure of the invention.
Fig. 8 is a schematic structural diagram of a packaging method of the GaN device packaging structure according to the present invention after forming a solder layer on the upper surface of a package substrate.
Fig. 9 is a schematic cross-sectional view of a GaN device package according to the present invention after a solder layer is formed on an upper surface of a package substrate.
Fig. 10 is a schematic structural diagram of a packaging method of the GaN device packaging structure according to the present invention after a solder layer is formed on the exposed surface of the second drain electrode.
Fig. 11 is a schematic cross-sectional structure diagram of the packaging method of the GaN device packaging structure according to the present invention along the Y direction after forming a solder layer on the exposed surface of the second drain.
Fig. 12 is a schematic structural diagram of a packaging method of the GaN device packaging structure of the present invention after forming the conductive clip.
Fig. 13 is a schematic cross-sectional view of the packaging method of the GaN device packaging structure according to the present invention along the Y direction after forming the conductive clip.
Fig. 14 is a schematic cross-sectional structure of the GaN device package structure according to the present invention along the X direction after forming the conductive clip.
Fig. 15 is a schematic structural diagram of a packaging method of the GaN device packaging structure of the present invention after forming a packaging layer.
Description of the reference numerals
01. Substrate board
011. Dielectric layer
012. Conductive layer
02. Chip layer
021 GaN HEMT chip
022 MOS chip
03. Metal lead
1. Packaging substrate
11. Dielectric layer
12. Conductive layer
121. First gate region
122. Source region
123. Drain region
124. Second gate region
125. Cascade electrode region
13. Conductive column
14. Through hole
15. A first electrode region
16. A second electrode region
17. A third electrode region
18. Switching electrode region
2. Chip layer
21 GaN HEMT chip
22 MOS chip
3. Conductive clamping piece
4. Welding layer
5. Encapsulation layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to 15. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a packaging method of a GaN device packaging structure, as shown in fig. 2, which is a process flow chart of the packaging method of the GaN device packaging structure, and includes the following steps:
S1: providing a packaging substrate, wherein the packaging substrate comprises a dielectric layer, a conductive layer positioned on the upper surface and the lower surface of the dielectric layer and a conductive column penetrating through the dielectric layer and electrically connected with the conductive layer, and the conductive layer positioned on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region and a cascade electrode region;
S2: providing a chip layer, wherein the chip layer comprises at least one GaN HEMT chip and at least one MOS chip, the front surface of the GaN HEMT chip is provided with a first grid, a first source electrode and a first drain electrode, the front surface of the MOS chip is provided with a second grid and a second source electrode, and the back surface of the MOS chip is provided with a second drain electrode;
S3: forming a welding layer on the upper surfaces of the first grid electrode region, the source electrode region, the drain electrode region, the second grid electrode region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode;
S4: the GaN HEMT chip and the MOS chip are arranged on the upper surface of the packaging substrate at intervals, the first grid electrode is arranged above the welding layer on the first grid electrode region, the first source electrode is arranged above the welding layer on the cascade electrode region, the first drain electrode is arranged above the welding layer on the drain electrode region, the second grid electrode is arranged above the welding layer on the second grid electrode region, and the second source electrode is arranged above the welding layer on the source electrode region;
s5: forming conductive clamping pieces with opposite ends respectively positioned above the second drain electrode and the welding layer on the cascade electrode region above the MOS chip, and processing the packaging structure after the conductive clamping pieces are formed to form an electric connection structure;
S6: forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer.
Referring to fig. 3 to 7, the steps S1 and S2 are performed: providing a package substrate 1, wherein the package substrate 1 comprises a dielectric layer 11, a conductive layer 12 located on the upper surface and the lower surface of the dielectric layer 11, and a conductive post penetrating through the dielectric layer 11 and electrically connected with the conductive layer 12, and the conductive layer 12 located on the upper surface of the dielectric layer 11 comprises a first gate region 121, a source region 122, a drain region 123, a second gate region 124, and a cascade electrode region 125; a chip layer is provided, the chip layer includes at least one GaN HEMT chip 21 and at least one MOS chip 22, the front surface of the GaN HEMT chip 21 is provided with a first gate, a first source and a first drain, the front surface of the MOS chip 22 is provided with a second gate and a second source, and the back surface of the MOS chip 22 is provided with a second drain.
Specifically, as shown in fig. 3 and fig. 4, the schematic three-dimensional structure of the package substrate 4 and the schematic cross-sectional structure of the package substrate 1 along the Y direction are respectively shown, and the package substrate 1 includes a direct copper-coated ceramic substrate, or other suitable substrates.
Specifically, as shown in fig. 5, the dielectric layer 11 is schematically shown in the structure, and the material of the dielectric layer 11 includes ceramic or other suitable dielectric material.
Specifically, as shown in fig. 6 and fig. 7, the material of the conductive layer 12 includes copper, gold, silver, titanium or other suitable conductive materials, that is, the material of the first gate region 121 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the source region 122 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the drain region 123 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the second gate region 124 includes copper, gold, silver, titanium or other suitable conductive materials, and the material of the cascade electrode region 125 includes copper, gold, silver, titanium or other suitable conductive materials. In this embodiment, a copper layer is used as the conductive layer 12.
As an example, the conductive layer 12 on the lower surface of the dielectric layer 11 includes a first electrode region 15, a second electrode region 16, and a third electrode region 17, the first gate region 121 is electrically connected to the first electrode region 15 through the conductive pillar 13, the source region 122 is electrically connected to the first electrode region 15 through the conductive pillar 13, the drain region 123 is electrically connected to the second electrode region 16 through the conductive pillar 13, and the second gate region 124 is electrically connected to the third electrode region 17 through the conductive pillar 13.
Specifically, under the condition of ensuring the performance of the package structure, the number of the conductive pillars 13 electrically connecting the first electrode region 15 and the first gate region 121 may be selected according to practical situations, which is not limited herein; the number of the conductive pillars 13 electrically connecting the source region 122 and the first electrode region 15 may be selected according to practical situations, and is not limited herein; the number of the conductive pillars 13 electrically connecting the second electrode region 16 and the drain region 123 may be selected according to practical situations, and is not limited herein; the number of the conductive pillars 13 electrically connecting the third electrode region 17 and the second gate region 124 may be selected according to practical situations, and is not limited herein.
Specifically, the size and shape of the lateral cross section of the conductive pillar 13 may be selected according to the practical situation, while ensuring the performance of the package structure, which is not limited herein. The lateral cross section here refers to a cross section parallel to the lower surface of the dielectric layer.
Specifically, the material of the first gate includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the first source electrode comprises gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the first drain electrode comprises gold, titanium, nickel, silver, copper or other suitable conductive materials.
Specifically, the material of the second gate includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the second source electrode comprises gold, titanium, nickel, silver, copper or other suitable conductive materials; the second drain electrode is made of gold, titanium, nickel, silver, copper or other suitable conductive materials.
Referring to fig. 8 to 14, the steps S3, S4 and S5 are performed: forming a bonding layer 4 on the upper surfaces of the first gate region 121, the source region 122, the drain region 123, the second gate region 124 and the tandem electrode region 125, and forming the bonding layer 4 on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain; the GaN HEMT chip 21 and the MOS chip 22 are arranged on the upper surface of the packaging substrate 1 at intervals, the first grid electrode is positioned above the welding layer 4 on the first grid electrode region 121, the first source electrode is positioned above the welding layer 4 on the cascade electrode region 125, the first drain electrode is positioned above the welding layer 4 on the drain electrode region 123, the second grid electrode is positioned above the welding layer 4 on the second grid electrode region 124, and the second source electrode is positioned above the welding layer 4 on the source electrode region 122; a conductive clip 3 is formed above the MOS chip 22, and the two ends of the conductive clip 3 are respectively located above the second drain electrode and the solder layer 4 on the cascade electrode region 125, and the package structure after the conductive clip 3 is formed is processed to form an electrical connection structure.
Specifically, before the solder layer 4 is formed on the package substrate 1, the package substrate 1 needs to be placed in a dedicated jig to facilitate the process operation.
Specifically, as shown in fig. 8 and 9, the structure schematic after the solder layer 4 is formed on the package substrate 1 and the cross-sectional structure schematic along the Y direction after the solder layer 4 is formed on the package substrate 1 are respectively shown, and the method for forming the solder layer 4 includes coating or other suitable methods.
Specifically, as shown in fig. 10 and 11, the structure schematic after the formation of the solder layer 4 on the second drain exposed surface and the cross-sectional structure schematic along the Y direction after the formation of the solder layer 4 on the second drain exposed surface are respectively shown, and the forming of the solder layer 4 includes the following steps: forming the bonding layer 4 on the upper surfaces of the first gate region 121, the source region 122, the drain region 123, the second gate region 124, and the cascade electrode region 125; the solder layers 4 are respectively formed on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source, and the second drain, and the GaN HEMT chip 21 and the MOS chip 22 are respectively disposed at the corresponding positions of the package substrate 1.
Specifically, the method for placing the GaN HEMT chip 21 on the package substrate 1 includes manual placement, machine placement, or other suitable placement methods; the method of placing the MOS chip 22 on the package substrate 1 includes manual placement, machine placement, or other suitable placement method.
Specifically, as shown in fig. 12, 13 and 14, the method of placing the conductive clip 3 above the solder layer 4 on the second drain electrode and the cascade electrode region 125 includes manual placement, machine placement or other suitable placement methods, which are respectively a schematic structural diagram after the conductive clip 3 is formed, a schematic sectional structural diagram along the Y direction after the conductive clip 3 is formed, and a schematic sectional structural diagram along the X direction after the conductive clip 3 is formed.
Specifically, since the solder layer 4 is formed on the upper surfaces of the first gate region 121, the source region 122, the drain region 123, the second gate region 124, and the cascade electrode region 125, the solder layer 4 is also formed on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source, and the second drain, that is, the solder layer 4 is formed on the conductive layer 12, the GaN HEMT chip 21, and the MOS chip 22, and the chip layer 2 (that is, the GaN HEMT chip 21, and the MOS chip 22) is placed at the corresponding positions of the package substrate 1 and the solder layer 4 is cured, so that the self-aligned effect can be achieved, and high-precision packaging can be achieved.
As an example, the GaN HEMT chip 21 is further provided with an integrated passive device (not shown) and an extraction electrode (not shown) for extracting the passive device; and a switching electrode region 18 is further arranged in the conductive layer 12 on the upper surface of the dielectric layer 11, the upper surface of the switching electrode region 18 is provided with the welding layer 4, the conductive clamping piece 3 is contacted with the upper surface of the welding layer 4 on the switching electrode region 18, the extraction electrode is contacted with the upper surface of the welding layer 4 on the switching electrode region 18, and the conductive clamping piece 3 and the extraction electrode form an electric connection structure through the welding layer 4 and the switching electrode region 18.
Specifically, after the bonding layer 4 is formed on the upper surface of the switching electrode region 18 and the exposed surface of the extraction electrode, the GaN HEMT chip 21 is placed on the package substrate 1.
Specifically, the switching electrode region 18 is spaced from the cascade electrode region 125 by a predetermined distance, and the distance between the switching electrode region 18 and the cascade electrode region 125 may be selected according to practical situations while ensuring the performance of the packaged device, which is not limited.
Specifically, the switching electrode region 18 and the cascade electrode region 125 are only attached to the upper surface of the dielectric layer 11, and are not electrically connected to the conductive layer 12 on the lower surface of the dielectric layer 11.
By way of example, the method of processing the package structure after forming the conductive clip 3 may include reflow soldering, curing, or other suitable method.
Specifically, the package structure after the conductive clip 3 is formed is processed, so that the first gate forms a firm electrical connection structure with the first gate region 121 through the bonding layer 4, the first source forms a firm electrical connection structure with the cascade electrode region 125 through the bonding layer 4, the first drain forms a firm electrical connection structure with the drain region 123 through the bonding layer 4, the second gate forms a firm electrical connection structure with the second gate region 124 through the bonding layer 4, the second source forms a firm electrical connection structure with the source region 122 through the bonding layer 4, and the conductive clip 3 forms a firm electrical connection structure with the second drain and the cascade electrode region 125 through the bonding layer 4.
Referring to fig. 15, the step S6 is performed: forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer 2.
In particular, the method of forming the encapsulation layer 5 includes coating or other suitable methods.
Specifically, the exposed surface of the dielectric layer 11 is further provided with a through hole 14 penetrating through the dielectric layer 11, that is, the through hole 14 is located in an uncovered area of the chip layer 2, the conductive layer 12 and the conductive clip 3.
Specifically, the size and shape of the opening of the through hole 14 may be selected according to the practical situation, while ensuring the performance of the package structure, which is not limited herein.
Specifically, the encapsulation layer 5 covering the upper surface of the encapsulation substrate and the exposed surface of the chip layer 2 is formed, and at the same time, since the encapsulation layer 5 is in a flowing liquid state, the encapsulation layer 5 fills the through hole 14 and flows into the gap between the lower surface of the encapsulation substrate 1 and the process platform through the through hole 14, that is, the encapsulation layer 5 covers the exposed surface of the lower surface of the dielectric layer 11, and the encapsulation layer 5 integrally connected is formed through two surfaces, thereby improving the tightness and reliability of encapsulation.
Specifically, after forming the encapsulation layer 5, a curing step is further included.
Specifically, after the encapsulation layer 5 is cured, an anti-oxidation layer (not shown) is formed on the exposed surface of the conductive layer 12 located on the lower surface of the dielectric layer 11, so as to prevent the exposed conductive layer 12 from being oxidized, affect the performance of the encapsulation structure, and facilitate the soldering of the client.
Specifically, dicing and trimming the appearance of the package structure after the oxidation-preventing layer is formed, so that the package structure is divided into single GaN device package structures, and trimming the appearance to remove appearance problems caused in the dicing or packaging process. In this embodiment, the excess encapsulation layer 5 in the GaN device encapsulation structure is mainly removed.
Specifically, the method of forming the oxidation preventing layer includes tin plating or a suitable method thereof.
Specifically, the dicing method for forming the encapsulation structure of the oxidation preventing layer includes mechanical dicing, laser dicing or other suitable method.
Specifically, the method further comprises the steps of testing the GaN device packaging structure and packaging the GaN device packaging structure passing the test after the GaN device packaging structure is formed.
Specifically, since the testing of the package structure and the packaging of the package structure passing the test are conventional process steps, the description thereof will not be repeated here.
Specifically, since the thermal conductivity of the dielectric layer 11 is higher, the thermal conductivity of the conductive layer 12 is also higher, and the heat-generating region of the chip layer 2 is closely attached to the conductive layer 11, so that the heat dissipation capability of the package structure is improved.
Specifically, in the packaging process, the welding layer 4 is formed by using two contact surfaces at the electric connection position, so that welding cavities in the curing process of the welding layer 4 are reduced, and packaging stress in the packaging process is reduced.
Specifically, the package substrate 1 guides the electrode of the package structure to the lower surface of the package substrate 1 through the conductive column 13, so that the chip package is compatible, and the size of the package structure can be adjusted according to the position of the electrode on the lower surface of the package substrate and the requirement of the client, thereby meeting the requirement of the client.
According to the packaging method of the GaN device packaging structure, the heat conduction coefficients of the dielectric layer 11 and the conductive layer 12 in the packaging substrate 1 are high, and the heating area of the chip layer 2 is tightly attached to the conductive layer 12, so that the heat dissipation capacity of the packaging structure is improved; forming a welded layer 4 on the exposed surfaces of the electrodes of the GaN HEMT chip 21 and the MOS chip 22, forming the welded layer 4 on the upper surfaces of the first grid region 121, the source region 122, the drain region 123, the second grid region 124 and the cascade electrode region 125, realizing high-precision packaging by utilizing the effect of automatic alignment after the welded layer 4 is solidified, and simultaneously forming the welded layer 4 by utilizing two contact surfaces at the electric connection part, thereby reducing welding cavities in the solidification process of the welded layer 4 and reducing packaging stress in the packaging process; because the package substrate 1 leads the electrode of the package structure to the lower surface of the package substrate 1 through the conductive column 13, the chip package is compatible, and the size of the package structure can be adjusted according to the position of the electrode on the lower surface of the package substrate and the requirements of clients, thereby meeting the requirements of the clients.
Example two
The embodiment provides a GaN device packaging structure, as shown in fig. 12 and 15, which are a schematic structure diagram of the GaN device packaging structure without a packaging layer and a schematic cross-sectional structure diagram of the GaN device packaging structure, respectively, including a packaging substrate 1, a chip layer 2, a conductive clip 3, a soldering layer 4 and a packaging layer 5, wherein the packaging substrate includes a dielectric layer 11, a conductive layer 12 located on the upper and lower surfaces of the dielectric layer 11, and a conductive post 13 penetrating the dielectric layer 11 and electrically connected to the conductive layer 12, and the conductive layer 12 located on the upper surface of the dielectric layer 11 includes a first gate region 121, a source region 122, a drain region 123, a second gate region 124, and a cascade electrode region 125; the chip layer 2 is located above the package substrate 1, and includes at least one GaN HEMT chip 21 and at least one MOS chip 22 that are disposed at intervals, the front surface of the GaN HEMT chip 21 is provided with a first gate (not shown) located above the first gate region 121, a first source (not shown) located above the cascade electrode region 125, and a first drain (not shown) located above the drain region 123, the front surface of the MOS chip 22 is provided with a second gate (not shown) located above the second gate region 124, a second source (not shown) located above the source region 122, and the back surface of the MOS chip 22 is provided with a second drain (not shown); two ends of the conductive clip 3 are located above the second drain and the cascade electrode region 125; the bonding layer 4 is respectively located between the first gate region 121 and the first gate, the cascade electrode region 125 and the first source, the first drain and the drain region 123, the second gate region 124 and the second gate, the source region 122 and the second source, and the second drain and the conductive clip 3, and the conductive clip 4 and the cascade electrode region 125, and forms an electrical connection structure; the encapsulation layer 5 covers the exposed surface of the chip layer 2 and the encapsulation substrate 1.
By way of example, the package substrate 1 comprises a direct copper coated ceramic substrate, or other suitable substrate.
Specifically, the thickness of the dielectric layer 11 may be selected according to practical situations, without limitation, while ensuring the performance of the package structure.
Specifically, the thickness of the conductive layer 12 may be selected according to practical situations, while ensuring the performance of the package structure, which is not limited.
Specifically, in the case of ensuring that the first gate electrode is located above the first gate region 121 and packaging the device, the size and shape of the first gate region 121 may be selected according to practical situations, which is not limited herein.
Specifically, the size and shape of the second source region 122 may be selected according to practical situations, and are not limited herein, while ensuring that the second source is located above the source region 122 and that the device is packaged.
Specifically, the size and shape of the drain region 124 may be selected according to practical situations, and are not limited herein, while ensuring that the first drain is located above the drain region 124 and that the device is packaged.
Specifically, in the case of ensuring that the second gate electrode is located above the second gate region 123 and packaging the device, the size and shape of the second gate region 123 may be selected according to practical situations, which is not limited herein.
Specifically, in the case where the first source electrode is located above the tandem electrode region 125 and a part of the tandem electrode region 125 is exposed, the size and shape of the tandem electrode region 125 may be selected according to practical situations, which is not limited herein.
Specifically, under the condition of ensuring the performance of the package structure and the correspondence between the chip layer 2 and the conductive layer 12, the number and the size of the GaN HEMT chips 21 in the chip layer 2 may be selected according to practical situations, which is not limited herein; the number and size of the MOS chips 22 in the chip layer 2 may be selected according to practical situations, and are not limited herein.
Specifically, under the condition that the first gate, the first source and the first drain are located on the front surface of the GaN HEMT chip 21 and the performance of the package structure, the size and the position of the first gate may be selected according to the actual situation, which is not limited herein; the size and position of the first source electrode can be selected according to practical situations, and are not limited here; the size and position of the first drain electrode may be selected according to practical situations, and are not limited herein.
Specifically, in the case that the second gate and the second source are located on the front side of the MOS chip 22, and the second drain is located on the back side of the MOS chip 22 and the performance of the package structure, the size and the position of the second gate may be selected according to the actual situation, which is not limited herein; the size and position of the second source electrode can be selected according to practical situations, and are not limited here; the size and position of the second drain electrode can be selected according to practical situations, and are not limited
As an example, the conductive layer 12 located on the lower surface of the dielectric layer 11 includes a first electrode region 15, a second electrode region 16, and a third electrode region 17.
As an example, the first gate region 121 is electrically connected to the first electrode region 15 through the conductive pillar 13, the source region 122 is electrically connected to the first electrode region 15 through the conductive pillar 13, the first drain region 123 is electrically connected to the second electrode region 16 through the conductive pillar 13, and the second gate region 124 is electrically connected to the third electrode region 17 through the conductive pillar 13.
Specifically, since the first gate region 121 and the source region 122 are electrically connected to the first electrode region 15 through the conductive pillar 13, the first gate and the second source are electrically connected to the conductive layer 12 through the conductive pillar 13, that is, the gate of the GaN HEMT chip 21 is electrically connected to the source of the MOS chip 22.
Specifically, the first electrode region 15, the second electrode region 16, and the third electrode region 17 are used for connecting an external circuit to supply power to the package structure.
Specifically, under the condition of ensuring the performance of the package structure, the thickness, shape, size and position of the first electrode region 15 may be selected according to practical situations, which are not limited herein; the thickness, shape, size and position of the second electrode region 16 may be selected according to practical situations, and are not limited herein; the thickness, shape, size and position of the third electrode region 17 may be selected according to practical situations, and are not limited herein.
Specifically, since the lower surface of the dielectric layer 11 has only the first electrode region 15, the second electrode region 16 and the third electrode region 17, the lead frame can be set according to the requirements of the application end of the customer and the size of the package structure, so as to meet the requirements of the customer.
As an example, the material of the soldering layer 4 includes at least one of gold, silver, tin, lead, and indium, and may be other suitable soldering materials.
Specifically, under the condition of ensuring the performance of the packaged device, the thickness, the size and the material of the solder layer 4 may be selected according to the actual situation, and are not limited herein, that is, the materials of the solder layer 4 located between the first gate region 121 and the first gate, between the cascade electrode region 125 and the first source, between the first drain and the drain region 123, between the second gate region 124 and the second gate, between the source region 122 and the second source, between the second drain and the conductive clip 3, and between the conductive clip 3 and the cascade electrode region 125 may be different or the same.
Specifically, the first gate region 121 is electrically connected to the first gate through the bonding layer 4, the cascade electrode region 125 is electrically connected to the first source through the bonding layer 4, the first drain is electrically connected to the drain region 123 through the bonding layer 4, the second gate region 124 is electrically connected to the second gate through the bonding layer 4, the source region 122 is electrically connected to the second source through the bonding layer 4, the second drain is electrically connected to the conductive clip 3 through the bonding layer 4, and the conductive clip 3 is electrically connected to the cascade electrode region 125 through the bonding layer 4.
Specifically, the material of the conductive clip 3 includes gold, silver, copper, aluminum, titanium or other suitable conductive materials.
As an example, the GaN HEMT chip 21 is further provided with an integrated passive device (not shown) and an extraction electrode (not shown) for extracting the passive device; a switching electrode region 18 is also provided in the conductive layer 12 on the upper surface of the dielectric layer 11.
Specifically, the passive devices integrated in the GaN HEMT chip 21 include capacitors, inductors, resistors, or other suitable passive devices. In this embodiment, the passive device integrated in the GaN HEMT chip 21 is a resistor, and the resistance is set according to actual needs.
Specifically, in the GaN HEMT chip 21, the passive device is electrically connected to the first gate, that is, the terminal integrated in the passive device is electrically connected to the first electrode region 15 through the first gate, so as to protect the GaN HEMT chip 21 and prevent the GaN HEMT chip 21 from being burned.
As an example, the bonding layer 4 is disposed on the upper surface of the transit electrode region 18, the conductive clip 3 is located above the bonding layer 4 on the transit electrode region 18, the extraction electrode is located above the bonding layer 4 on the transit electrode region 18, and the conductive clip 3 and the extraction electrode form an electrical connection structure through the bonding layer 4 and the transit electrode region 18, that is, the conductive clip 3 is electrically connected with the extraction electrode through the transit electrode region 18.
Specifically, in the case of ensuring the performance of the package structure and that the extraction electrode and the conductive clip 3 are located above the switching electrode region 18, the position, size and shape of the switching electrode region 18 may be selected according to practical situations, and are not limited herein.
Specifically, the conductive clip 3 is located above the second drain electrode, the cascade electrode region 125 and the switching electrode region 18, and is electrically connected to the second drain electrode, the cascade electrode region 125 and the switching electrode region 18 through the pad layer 4, i.e. the second drain electrode, the first source electrode and the extraction electrode are electrically connected through the conductive clip 3.
Specifically, in the case of ensuring that the conductive clip 3 forms an electrical connection with the second drain electrode, the cascade electrode region 125 and the switching electrode region 18, respectively, and the performance of the package structure, the shape, size and thickness of the conductive clip 3 may be selected according to practical situations, which are not limited.
Specifically, the material of the encapsulation layer 5 includes epoxy resin, polyimide, silica gel, polymaleimide triazine resin, polyphenylene oxide, polytetrafluoroethylene or other suitable dielectric materials. In this embodiment, an epoxy resin layer is used as the encapsulation layer 5.
Specifically, the thickness of the encapsulation layer 5 may be selected according to practical situations, without limitation, while ensuring the performance of the encapsulated device.
Specifically, at least one through hole 14 penetrating through the dielectric layer 11 is further provided in the dielectric layer 11, the packaging layer 5 fills the through hole 14, and the packaging layer 5 also covers the exposed surface of the lower surface of the dielectric layer 11.
Specifically, the encapsulation layer 5 on the lower surface of the dielectric layer 11 and the encapsulation layer 5 on the upper surface of the dielectric layer 11 are connected together by the arrangement of the through holes 14, so as to form the enhanced tightness and reliability of the encapsulation structure.
Specifically, since the current capability of the conductive clip 3 is stronger than that of the metal lead in the wire bonding package, the conductive clip 3 electrically connecting the second drain and the first source is disposed on the back of the MOS chip 22, so that the current capability of the package structure is improved, and meanwhile, the electrode of the package structure is led out by using the combination of the conductive layer 12 and the conductive post 13, so that the problems of bonding damage and cold welding caused by the wire bonding process are avoided, and the reliability and performance of the package structure are improved.
Specifically, an oxidation preventing layer (not shown) is further disposed on the exposed surface of the conductive layer 12 on the lower surface of the dielectric layer 11 to prevent oxidation of the conductive layer 12.
Specifically, the material of the oxidation preventing layer includes tin or other suitable oxidation preventing materials.
Specifically, during the operation of the package structure, the MOS chip 22 biases the GaN HEMT chip 21 to control the turn-off of the GaN HEMT chip 21, the MOS chip 22 is used as a switch management of the whole device, and the GaN HEMT chip 21 is used as a main operation device.
Specifically, the conductive clamping piece 3 is used for replacing a metal lead in the wire bonding package, and the package substrate 1 is used for being combined with the conductive clamping piece for packaging, so that the distribution of the metal leads with dense packaging structure is avoided, the inductance and mutual inductance of the packaging structure are reduced, the frequency of application of the packaging structure is improved, the packaging structure meets the working requirement of a high-frequency application end, and the working efficiency of the application end is improved.
According to the GaN device packaging structure, the conductive clamping piece 3 replaces a metal lead in wire bonding packaging and is combined with the packaging substrate 1, the current capacity of the conductive clamping piece 3 is higher than that of the metal lead, so that the current capacity of the packaging structure is improved, meanwhile, the dense metal lead is prevented from being distributed in the packaging structure, the inductance and mutual inductance of the packaging structure are reduced, the application frequency of the packaging structure is improved, the packaging structure meets the working requirement of a high-frequency application end, and the working efficiency of the application end is improved; the electrode of the packaging structure is led out through the combination of the conductive layer 12 and the conductive column 13, so that the problems of bonding damage and cold joint caused by the wire bonding packaging process are avoided, the packaging resistance of the packaging structure is reduced, and the reliability and performance of the device are improved.
In summary, the GaN device packaging structure and the packaging method thereof lead out the electrode of the packaging structure through the combination of the packaging substrate and the conductive clamping piece, so that the packaging method of wire bonding is avoided, the problems of bonding damage and virtual welding caused by the wire bonding packaging process are avoided, the packaging resistance of the packaging structure is reduced, the reliability and the performance of the device are improved, and the heat-generating area of the chip layer is clung to the conductive layer, the heat conductivity coefficients of the conductive layer and the dielectric layer are higher than those of the packaging layer, and the heat dissipation capacity of the packaging structure is improved; the conductive clamping piece is utilized to replace a metal lead, so that the current capacity of the packaging structure is improved, the densely distributed metal lead is not required to be welded, the inductance and mutual inductance of the packaging structure are reduced, the application frequency of the packaging structure is improved, the packaging structure meets the working requirement of a high-frequency application end, and the working efficiency of the application end is improved. In addition, in the packaging process, welding layers are respectively formed on the exposed surfaces of the electrodes of the chip layer and the upper surfaces of the first grid electrode region, the source electrode region, the drain electrode region, the second grid electrode region and the cascade electrode region, the effect of automatic alignment is achieved after the welding layers are solidified, high-precision packaging is achieved, the welding layers are respectively formed on the two contact surfaces of the electric connection part, welding cavities in the solidifying process of the welding layers are reduced, and meanwhile packaging stress in the packaging process is reduced; the packaging substrate leads the electrode of the packaging structure to the lower surface of the packaging substrate through the conductive column, so that the packaging substrate can be compatible with patch packaging, the size of the packaging structure can be adjusted according to the requirements of clients according to the positions of the electrode positioned on the lower surface of the packaging substrate, and the requirements of the clients are met. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A GaN device package structure, comprising:
The packaging substrate comprises a dielectric layer, a conductive layer positioned on the upper surface and the lower surface of the dielectric layer and a conductive column penetrating through the dielectric layer and electrically connected with the conductive layer, wherein the conductive layer positioned on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region and a cascade electrode region;
The chip layer is positioned above the packaging substrate and comprises at least one GaN HEMT chip and at least one MOS chip which are arranged at intervals, the front surface of the GaN HEMT chip is provided with a first grid electrode positioned above the first grid electrode region, a first source electrode positioned above the cascade electrode region and a first drain electrode positioned above the drain electrode region, the front surface of the MOS chip is provided with a second grid electrode positioned above the second grid electrode region and a second source electrode positioned above the source electrode region, and the back surface of the MOS chip is provided with a second drain electrode;
A conductive clip, two ends of which are positioned above the second drain electrode and the cascade electrode region;
The welding layer is respectively positioned between the first grid electrode region and the first grid electrode, between the cascade electrode region and the first source electrode, between the first drain electrode and the drain electrode region, between the second grid electrode region and the second grid electrode, between the source electrode region and the second source electrode, between the second drain electrode and the conductive clamping piece, and between the conductive clamping piece and the cascade electrode region, and forms an electric connection structure;
And the packaging layer covers the chip layer and the exposed surface of the packaging substrate.
2. The GaN device package of claim 1, wherein: the package substrate comprises a direct copper-coated ceramic substrate and a direct copper-coated ceramic substrate.
3. The GaN device package of claim 1, wherein: the conductive layer positioned on the lower surface of the dielectric layer comprises a first electrode region, a second electrode region and a third electrode region.
4. The GaN device package of claim 3, wherein: the first gate region is electrically connected with the first electrode region through the conductive pillar, the source region is electrically connected with the first electrode region through the conductive pillar, the first drain region is electrically connected with the second electrode region through the conductive pillar, and the second gate region is electrically connected with the third electrode region through the conductive pillar.
5. The GaN device package of claim 1, wherein: the welding layer is made of at least one of gold, silver, tin, lead and indium.
6. The GaN device package of claim 1, wherein: an integrated passive device and an extraction electrode for extracting the passive device are also arranged in the GaN HEMT chip; and a transfer electrode area is also arranged in the conductive layer on the upper surface of the dielectric layer.
7. The GaN device package of claim 6, wherein: the upper surface of the switching electrode area is provided with the welding layer, the conductive clamping piece is positioned above the welding layer on the switching electrode area, the extraction electrode is positioned above the welding layer on the switching electrode area, and the conductive clamping piece and the extraction electrode form an electric connection structure through the welding layer and the switching electrode area.
8. The packaging method of the GaN device packaging structure is characterized by comprising the following steps of:
Providing a packaging substrate, wherein the packaging substrate comprises a dielectric layer, a conductive layer positioned on the upper surface and the lower surface of the dielectric layer and a conductive column penetrating through the dielectric layer and electrically connected with the conductive layer, and the conductive layer positioned on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region and a cascade electrode region;
Providing a chip layer, wherein the chip layer comprises at least one GaN HEMT chip and at least one MOS chip, the front surface of the GaN HEMT chip is provided with a first grid, a first source electrode and a first drain electrode, the front surface of the MOS chip is provided with a second grid and a second source electrode, and the back surface of the MOS chip is provided with a second drain electrode;
Forming a welding layer on the upper surfaces of the first grid electrode region, the source electrode region, the drain electrode region, the second grid electrode region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode;
The GaN HEMT chip and the MOS chip are arranged on the upper surface of the packaging substrate at intervals, the first grid electrode is arranged above the welding layer on the first grid electrode region, the first source electrode is arranged above the welding layer on the cascade electrode region, the first drain electrode is arranged above the welding layer on the drain electrode region, the second grid electrode is arranged above the welding layer on the second grid electrode region, and the second source electrode is arranged above the welding layer on the source electrode region;
Forming a conductive clamping piece with two ends respectively positioned above the second drain electrode and the welding layer on the cascade electrode zone above the MOS chip, and processing the packaging structure after the conductive clamping piece is formed to form an electric connection structure;
forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer.
9. The packaging method of the GaN device packaging structure according to claim 8, characterized in that: the conductive layer positioned on the lower surface of the dielectric layer comprises a first electrode region, a second electrode region and a third electrode region, wherein the first electrode region is electrically connected with the first electrode region through the conductive column, the source region is electrically connected with the first electrode region through the conductive column, the drain region is electrically connected with the second electrode region through the conductive column, and the second electrode region is electrically connected with the third electrode region through the conductive column.
10. The packaging method of the GaN device packaging structure according to claim 8, characterized in that: an integrated passive device and an extraction electrode for extracting the passive device are also arranged in the GaN HEMT chip; and a transfer electrode region is further arranged in the conductive layer on the upper surface of the dielectric layer, the upper surface of the transfer electrode region is provided with the welding layer, the conductive clamping piece is contacted with the upper surface of the welding layer on the transfer electrode region, the extraction electrode is contacted with the upper surface of the welding layer on the transfer electrode region, and the conductive clamping piece forms an electric connection structure with the extraction electrode through the welding layer and the transfer electrode region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211493013.8A CN118099152A (en) | 2022-11-25 | 2022-11-25 | GaN device packaging structure and packaging method thereof |
| PCT/CN2023/126707 WO2024109434A1 (en) | 2022-11-25 | 2023-10-26 | Gan device packaging structure and packaging method therefor |
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| CN202211493013.8A CN118099152A (en) | 2022-11-25 | 2022-11-25 | GaN device packaging structure and packaging method thereof |
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| CN202211493013.8A Pending CN118099152A (en) | 2022-11-25 | 2022-11-25 | GaN device packaging structure and packaging method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8680627B2 (en) * | 2011-01-14 | 2014-03-25 | International Rectifier Corporation | Stacked half-bridge package with a common conductive clip |
| US8916968B2 (en) * | 2012-03-27 | 2014-12-23 | Infineon Technologies Ag | Multichip power semiconductor device |
| US9905500B2 (en) * | 2015-07-24 | 2018-02-27 | Semiconductor Components Industries, Llc | Semiconductor component and method of manufacture |
| CN110444524B (en) * | 2019-08-26 | 2022-11-18 | 珠海镓旦科技有限公司 | Low parasitic parameter packaging structure for cascade enhancement type GaN HEMT device and packaging method thereof |
| CN111430335B (en) * | 2020-03-22 | 2025-02-25 | 华南理工大学 | A stacked structure cascaded GaN-based power device and packaging method thereof |
| US11587852B2 (en) * | 2020-10-12 | 2023-02-21 | Nxp Usa, Inc. | Power amplifier modules with flip-chip and non-flip-chip power transistor dies |
| EP4044225B1 (en) * | 2021-02-16 | 2024-06-26 | Nexperia B.V. | A semiconductor device and a method of manufacturing a semiconductor device |
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