CN118038831A

CN118038831A - Driving circuit and display device

Info

Publication number: CN118038831A
Application number: CN202410378214.6A
Authority: CN
Inventors: 黄顾; 叶利丹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2024-03-28
Filing date: 2024-03-28
Publication date: 2024-05-14

Abstract

The application provides a driving circuit and a display device. The driving circuit comprises a plurality of sampling driving units, wherein each sampling driving unit comprises a trigger control end, a scanning input end and a scanning output end. And each sampling driving unit further comprises a trigger input end, wherein the trigger control end is connected with the gating signal, and the trigger input end is connected with the acquisition starting signal and is used for respectively outputting front K rows of acquisition scanning signals when the gating signal is at an acquisition effective level. The other acquisition driving units are respectively cascaded with the first K sampling driving units, and the acquisition scanning signals output by the mth acquisition driving unit are used as triggering signals of the (m+K) th acquisition driving unit. The driving circuit sequentially outputs acquisition scanning signals row by row in a pixel voltage acquisition stage of the display panel; the strobe signal is configured to capture an active level in an extinction region of each frame of the image signal of the display panel. The driving circuit can reduce the number of time sequence chips and the process cost.

Description

Driving circuit and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a driving circuit and a display device.

Background

With the development of the display technology field, the application of the display device is more and more widespread, and the requirement on the display device is more and more high. Among them, the Liquid crystal display device (Liquid CRISTAL DISPLAY, LCD) has the characteristics of small volume, low power consumption, no radiation, relatively low manufacturing cost, and the like, and is dominant in the market of the display field.

In general, in a liquid crystal display device, due to the impedance of a data line and the effect of coupling capacitance with other wirings, delay in charging a liquid crystal cell is easily caused, and color cast problem occurs in a panel. Therefore, the pixel voltage needs to be collected to adjust the subsequent pixel voltage according to the collected pixel voltage.

However, in order to collect the pixel voltage, a timing chip required for collecting the pixel voltage needs to be added to the binding area of the display panel, and the number of chips and the process cost are increased.

Disclosure of Invention

The application provides a driving circuit and a display device, and aims to solve the problems that in the prior art, for collecting pixel voltage, time sequence chips required by collecting the pixel voltage are required to be added, so that the number of chips and the process cost are increased in a binding area of a display panel.

In order to solve the technical problems, the first technical scheme provided by the application is as follows: a driving circuit is provided. The driving circuit comprises a trigger control end, a scanning input end and a scanning output end, wherein the trigger control end is connected with a trigger signal, and the scanning input end is connected with a corresponding scanning clock signal; the sampling driving unit is used for being conducted when the trigger signal is of an effective level so as to output the scanning clock signal as an acquisition scanning signal of a corresponding row at the scanning output end.

Each sampling driving unit further comprises a trigger input end, the trigger control end is connected with a gating signal, the trigger input end is connected with an acquisition starting signal, and the sampling driving units are used for respectively outputting front K rows of acquisition scanning signals at the scanning output end when the gating signal is an acquisition effective level; wherein K is an integer greater than 0;

the other sampling driving units are respectively cascaded with the first K sampling driving units, and the acquisition scanning signals output by the mth sampling driving unit are used as the trigger signals of the (m+K) th sampling driving unit, so that a plurality of sampling driving units sequentially output the acquisition scanning signals row by row; wherein M is a positive integer less than M, and M is the number of the sampling driving units;

The driving circuit is used for a display panel, the display panel comprises a plurality of sub-pixel units, and at least part of the sub-pixel units comprise a voltage acquisition unit; in the pixel voltage acquisition stage of the display panel, the driving circuit sequentially outputs the acquisition scanning signals row by row so as to drive the voltage acquisition module to be started row by row; and the strobe signal is configured as the capture active level in a vanishing region of each frame of the image signal of the display panel.

Each sampling driving unit comprises a triggering unit, an output unit and a pull-down unit; wherein the number of the scanning clock signals is 2K, and among the first K sampling driving units,

Each trigger unit comprises a first transistor, wherein the grid electrode of the first transistor is used as the trigger control end, and the source electrode of the first transistor is used as the trigger input end;

each output unit comprises a second transistor and a bootstrap capacitor, wherein the grid electrode of the second transistor is electrically connected with the drain electrode of the first transistor, the source electrode is used as the scanning input end, and the drain electrode is used as the scanning output end; two ends of the bootstrap capacitor are respectively and electrically connected with the grid electrode and the drain electrode of the second transistor;

Each pull-down unit comprises a third transistor and a fourth transistor, wherein the source electrode of the third transistor and the source electrode of the fourth transistor are respectively and electrically connected with the grid electrode and the drain electrode of the second transistor, the drain electrode of the third transistor and the drain electrode of the fourth transistor are commonly connected with a low-level signal, and the grid electrode of the third transistor and the grid electrode of the fourth transistor are commonly connected with the acquisition scanning signal output by the sampling driving unit of the next stage.

In each sampling driving unit after the kth sampling driving unit, each triggering unit comprises a fifth transistor, a gate and a source of the fifth transistor are connected and serve as the triggering control end, and a drain of the fifth transistor is electrically connected to the scanning control end of the output unit.

In order to solve the technical problems, a second technical scheme provided by the application is as follows: a display device is provided. The display device includes:

The display panel comprises a plurality of data lines, a plurality of image scanning lines, a plurality of acquisition scanning lines and a plurality of sub-pixel units which are arranged in a matrix; the sub-pixel unit comprises a driving unit and a liquid crystal unit, and a connecting node is arranged between the driving unit and the liquid crystal unit; the sub-pixel units at least comprise a voltage acquisition unit, wherein a first connection end of the voltage acquisition unit is electrically connected with the connection node, a control end of the voltage acquisition unit is electrically connected with the acquisition scanning line of the corresponding row, and a second connection end of the voltage acquisition unit is used as a pixel voltage acquisition end;

The driving circuit is the driving circuit related to the technical scheme, and a plurality of scanning output ends of the driving circuit are correspondingly connected with the acquisition scanning lines so as to sequentially output acquisition scanning signals to a plurality of acquisition scanning lines row by row in a shadow eliminating area of each frame of image signals, so that the voltage acquisition units are sequentially turned on row by row, and corresponding pixel voltages are output at the pixel voltage acquisition ends.

The driving circuit is further used as a grid driving module and used for transmitting image scanning signals to the plurality of sub-pixel units;

The first K sampling driving units of the driving circuit further comprise a first gating switch, wherein the first gating switch comprises a first gating control end, a first access end, a second access end and a first output end; the first gating control end is used as a triggering control end to access a gating signal, the first access end is used as a first triggering input end to access a frame starting signal, and the second access end is used as a second triggering input end to access an acquisition starting signal;

Each sampling driving unit also comprises a second gating switch and a third gating switch; the second gating switch comprises a second gating control end, a scanning receiving end, a first scanning output end and a second scanning output end; the second gating control end is connected with the gating signal, the scanning receiving end is connected with the scanning output end, the first scanning output end is connected with the corresponding image scanning line, the second scanning output end is connected with the corresponding acquisition scanning line, and the first scanning output end, the second scanning output end and the triggering control end of the sampling driving unit in the next cascade are connected with each other;

The third gating switch comprises a third gating control end, a first pull-down end, a second pull-down end and a pull-down access end, wherein the third gating control end is connected with the gating signal, the first pull-down end is connected with the image scanning signal output by the driving unit at the next stage, the second pull-down end is connected with the acquisition scanning signal output by the sampling driving unit at the next stage, and the pull-down access end is connected with the pull-down unit.

Wherein the strobe signal is configured to be high level in a display area of each frame of the image signal and low level in a blanking area;

When the gating signal is in a high level, the first gating switch conducts a first access end and a first output end, and the second gating switch conducts the scanning receiving end and the first scanning output end, so that the sampling driving units at all stages sequentially output the image scanning signal line by line; the third gating switch conducts the first pull-down end and the pull-down access end so as to close the image scanning signal output by the sampling driving unit at the current stage when the sampling driving unit at the next stage outputs the image scanning signal;

When the gating signal is in a low level, the first gating switch conducts the second access end and the first output end, and the second gating switch conducts the scanning receiving end and the second scanning output end, so that the sampling driving units at all stages sequentially output the acquisition scanning signal line by line; the third gating switch conducts the second pull-down end and the pull-down access end so as to close the acquisition scanning signal output by the sampling driving unit at the current stage when the sampling driving unit at the next stage outputs the acquisition scanning signal.

The first gating switch comprises a sixth transistor and a seventh transistor, wherein the sixth transistor is an N-type transistor, and the seventh transistor is a P-type transistor; the grid electrode of the sixth transistor is connected with the first gating control end, the source electrode of the sixth transistor is connected with the first access end, and the drain electrode of the sixth transistor is connected with the first output end; the grid electrode of the seventh transistor is connected with the first gating control end, the source electrode of the seventh transistor is connected with the second access end, and the drain electrode of the seventh transistor is connected with the first output end;

The second gating switch comprises an eighth transistor and a ninth transistor, wherein the eighth transistor is an N-type transistor, and the ninth transistor is a P-type transistor; the grid electrode of the eighth transistor is connected with the second gating control end, the source electrode of the eighth transistor is connected with the scanning receiving end, and the drain electrode of the eighth transistor is connected with the first scanning output end; the grid electrode of the ninth transistor is connected with the second gating control end, the source electrode of the ninth transistor is connected with the scanning receiving end, and the drain electrode of the ninth transistor is connected with the second scanning output end;

The third gating switch comprises a first pull-down transistor and a second pull-down transistor, wherein the first pull-down transistor is an N-type transistor, and the second pull-down transistor is a P-type transistor; the grid electrode of the first pull-down transistor is connected with the third gating control end, the source electrode of the first pull-down transistor is connected with the first pull-down end, and the drain electrode of the first pull-down transistor is connected with the pull-down access end; and a grid electrode of the second pull-down transistor is connected with the third gating control end, a source electrode of the second pull-down transistor is connected with the second pull-down end, and a drain electrode of the second pull-down transistor is connected with the pull-down access end.

When the gating signal is at a high level, the sixth transistor, the eighth transistor and the first pull-down transistor are turned on, and the driving circuit is used as the gate driving module and is used for outputting the image scanning signal to the plurality of sub-pixel units row by row in sequence in the display area of each frame of image signal;

When the gating signal is at a low level, the seventh transistor, the ninth transistor and the second pull-down transistor are turned on, and the driving circuit is used as an acquisition driving module and is used for outputting the acquisition scanning signal to a plurality of sub-pixel units row by row in sequence in the vanishing area of each frame of image signal.

Wherein, in the driving circuit, K is equal to 1; the driving circuit is arranged on one side of the display panel and is used for outputting the image scanning signals and/or the acquisition scanning signals to the display panel.

Wherein, in the driving circuit, K is equal to 2;

The 1 st sampling driving unit and the sampling driving unit which are sequentially cascaded later are arranged on a first side of the display panel, the 2 nd sampling driving unit and the sampling driving unit which are sequentially cascaded later are arranged on a second side of the display panel, and the first side is opposite to the second side;

The 1 st sampling driving unit and the later sequentially cascaded sampling driving units are used for outputting the image scanning signals and/or the acquisition scanning signals of the odd lines, and the 2 nd sampling driving unit and the later sequentially cascaded sampling driving units are used for outputting the image scanning signals and/or the acquisition scanning signals of the even lines.

The application has the beneficial effects that: unlike the prior art, the present application provides a driving circuit, i.e., a display device, which includes a plurality of sampling driving units; among the first K sampling driving units, each sampling driving unit comprises a trigger control end, a trigger input end, a scanning input end and a scanning output end, the trigger control end is connected with a gating signal, the trigger input end is connected with an acquisition starting signal, and the scanning input end is connected with a corresponding scanning clock signal, so that the first K sampling driving units can respectively output front K rows of acquisition scanning signals at the scanning output end when the gating signal is at an acquisition effective level. Meanwhile, the sampling driving units after the Kth sampling driving unit are respectively cascaded with the first K sampling driving units, each sampling driving unit after the Kth sampling driving unit comprises a trigger control end, a scanning input end and a scanning output end, the trigger control end is connected with a corresponding scanning clock signal, the scanning input end is connected with a corresponding scanning clock signal, and the acquisition scanning signal output by the mth sampling driving unit is used as a triggering signal of the (m+K) th sampling driving unit, so that a plurality of sampling driving units can sequentially output acquisition scanning signals line by line, and time sequence scanning signals required by acquiring pixel voltages are realized. Further, the gate signal is configured to acquire an effective level in the vanishing area of each frame of image signals of the display panel, so that the driving circuit outputs acquisition scanning signals in the vanishing area of each frame of image signals line by line, the voltage acquisition module is turned on line by line in the vanishing area period, the acquisition of pixel voltages is realized, and the driving circuit outputs the acquisition scanning signals in the vanishing area period of each frame of image signals without influencing the image display of the display panel; meanwhile, the structure of the driving circuit is similar to that of the grid driving module, the required acquisition starting signal is identical to the time sequence of the reset signal required by the sub-pixel units of the display panel, and the required gating signal and the required scanning clock signal are identical to those of the grid driving module, so that the driving circuit can be prepared together with the grid driving module, and an acquisition time sequence chip is not required to be additionally designed and prepared, so that the number of chips in a binding area of the display panel and the process cost can be effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without any inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of the driving circuit provided in the embodiment of FIG. 1;

FIG. 3 is a timing diagram of the operation of the driving circuit provided in the embodiment of FIG. 2;

Fig. 4 is a schematic structural diagram of a display device according to a second embodiment of the present application;

FIG. 5 is a schematic diagram of the driving circuit provided in the embodiment of FIG. 4;

FIG. 6 is a timing diagram of the operation of the driving circuit provided in the embodiment of FIG. 5;

Fig. 7 is a schematic diagram of a driving circuit according to a third embodiment of the present application;

Fig. 8 is a schematic structural diagram of a display device according to a fourth embodiment of the present application;

FIG. 9 is a schematic diagram of an embodiment of the driving circuit of FIG. 8;

FIG. 10 is a schematic diagram of another embodiment of the driving circuit of FIG. 8;

Fig. 11 is a schematic structural view of a display device according to a fifth embodiment of the present application;

fig. 12 is a schematic diagram of the structure of the driving circuit provided in the embodiment of fig. 10.

Reference numerals:

100-a display device; 10-a display panel; 11-sub-pixel units; 20-a data driving module; 30-a timing control module; a 40-gate drive module; 41-a first gate drive module; 42-a second gate drive module; a 50-drive circuit; 501-a first driving circuit; 502-a second driving circuit; 51-a sampling drive unit; 511-a trigger unit; 512-an output unit; 513-a pull-down unit; 514-a first gating switch; 515-a second gating switch; 516-a third gating switch;

Q1-a drive transistor; m1-a switching transistor; t1-a first transistor; t2-second transistor; t3-a third transistor; t4-fourth transistor; t5-fifth transistor; t6-sixth transistor; t7-seventh transistor; t8-eighth transistor; t9-ninth transistors; t11-first pull-down transistor; t12-a second pull-down transistor; c-bootstrap capacitance; q (1) -Q (M) -scan control signals; s (1) -S (M) -image scan lines; g (1) -G (M) -image scanning signals; em (1) -Em (M) -collecting scanning signals; e (1) -E (M) -collecting scanning signals; ABK-strobe signal; STV-frame start signal; RESET-acquisition initiation signal; EK. EK (1) -EK (2K) -scan clock signal; VSS-low signal.

Detailed Description

The following describes embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The application will now be described in detail with reference to the drawings and examples.

Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application. In the present embodiment, a display device 100 is provided, and the display device 100 includes a display panel 10, a gate driving module 40, a driving circuit 50, a data driving module 20, and a timing control module 30. The gate driving module 40 and the driving circuit 50 are disposed on opposite sides of the display panel 10, respectively.

The display panel 10 includes a plurality of image scan lines S (1) to S (M), a plurality of acquisition scan lines Em (1) to Em (M), a plurality of data lines, and a plurality of sub-pixel units 11 arranged in a matrix. The plurality of image scanning lines S (1) to S (M) extend along a first direction and are arranged at intervals along a second direction, and are used for transmitting image scanning signals G (1) to G (M) to the sub-pixel unit 11; the acquisition scanning lines Em (1) to Em (M) are arranged at intervals and in an insulating manner with the image scanning lines S (1) to S (M), and the acquisition scanning lines Em (1) to Em (M) extend along a first direction and are arranged at intervals along a second direction and are used for transmitting acquisition scanning signals E (1) to E (M) to the sub-pixel unit 11; the data lines extend along the second direction and are arranged at intervals along the first direction, form a grid shape with the image scanning lines S (1) to S (M), define areas of the sub-pixel units 11, each grid area is provided with one sub-pixel unit 11, and the data lines are used for transmitting data signals to the sub-pixel units 11; in the embodiment of the present application, the row direction of the matrix formed by the sub-pixel units 11 is defined as the first direction, and the column direction of the matrix is defined as the second direction, so as to describe the embodiment of the present application, and in other embodiments, the first direction and the second direction may be defined according to the arrangement design of the sub-pixel units 11.

Each sub-pixel unit 11 includes a driving unit and a liquid crystal unit, the driving unit includes a driving transistor Q1, a gate of the driving transistor Q1 is electrically connected to a corresponding image scanning line G (i), a source is electrically connected to a data line, a drain is electrically connected to the liquid crystal unit, and specifically, is electrically connected to a pixel electrode of the liquid crystal unit. The liquid crystal unit comprises a pixel electrode, a liquid crystal layer common electrode and a color film layer (not shown), wherein the pixel electrode, the liquid crystal layer and the common electrode form a liquid crystal capacitor for driving liquid crystal molecules in the liquid crystal layer to deflect so as to control the light transmission quantity, and the color film layer is used for filtering light rays into color light with corresponding colors. Wherein, a connection node N1 is arranged between the driving unit and the liquid crystal unit.

Wherein, at least part of the sub-pixel units 11 further comprise a voltage acquisition unit, the control end of the voltage acquisition unit is electrically connected to the corresponding acquisition scanning line Em (i), the first connection end is electrically connected to the connection node N1, and the second connection end is electrically connected to the data driving module 20 as a pixel voltage acquisition end, so that the acquisition scanning signals E (1) to E (M) are transmitted through the acquisition scanning lines Em (1) to Em (M) to control the voltage acquisition unit to be conducted, thereby realizing the acquisition of the pixel voltage at the connection node N1 of the sub-pixel units 11. Specifically, the voltage acquisition unit includes a switching transistor M1, the gate of the switching transistor M1 is electrically connected to the corresponding acquisition scan line Em (i) as a control end, the source is electrically connected to the connection node N1 as a first connection end, and the drain is electrically connected to the data driving module 20 as a second connection end.

The gate driving module 40 includes a plurality of scanning signal terminals (not shown), the plurality of scanning signal terminals are respectively electrically connected to the plurality of image scanning lines S (1) to S (M), and the gate driving module 40 is configured to sequentially output the image scanning signals line by line at the plurality of scanning signal terminals in a display area stage of each frame of the image signal; g (1) -G (M) to turn on the driving transistors Q1 of the sub-pixel units 11 row by row in order to enable the data voltages transmitted by the data lines to be applied to the liquid crystal units, thereby displaying images.

The driving circuit 50 includes a plurality of scan output terminals (not shown), and the plurality of scan output terminals are respectively and electrically connected with a plurality of acquisition scan lines Em (1) to Em (M), and in a stage of an image signal extinction area of each frame, the driving circuit 50 is configured to sequentially output the acquisition scan signals E (1) to E (M) row by row at the plurality of scan output terminals, so that the voltage acquisition units in the sub-pixel units 11 are sequentially turned on row by row, so that the pixel voltages of the sub-pixel units 11 are transmitted to the pixel voltage acquisition terminals through the voltage acquisition units, so as to realize acquisition of the pixel voltages. Specifically, the specific structure of the driving circuit 50 is described below.

Referring to fig. 2, fig. 2 is a schematic diagram of a driving circuit provided in the embodiment of fig. 1. In the present embodiment, a driving circuit 50 is provided, and the driving circuit 50 is used for transmitting the acquisition scanning signals E (1) to E (M) to the acquisition scanning lines Em (1) to Em (M) of the display panel 10, so as to realize the acquisition of the pixel voltages.

Specifically, the driving circuit 50 includes a plurality of sampling driving units 51, the sampling driving units 51 include a trigger control terminal, a scan input terminal and a scan output terminal, the trigger control terminal is connected to the trigger control terminal and the scan input terminal is connected to the corresponding scan clock signal EK (j); the sampling driving unit 51 is configured to be turned on when the trigger signal is at an active level, so as to output the scan clock signal EK (j) as the acquisition scan signal E (i) of the corresponding row at the scan output terminal.

The first sampling driving unit 51 further includes a trigger input end, and the trigger control end of the first sampling driving unit is connected to the strobe signal ABK, the trigger input end is connected to the acquisition start signal RESET, the scan input end is connected to the corresponding scan clock signal EK (j), and the first sampling driving unit 51 is configured to output the first row of acquisition scan signals E (1) at the scan output end when the strobe signal ABK is at the acquisition valid level.

Further, the other sampling driving units 51 are sequentially cascaded with the first sampling driving unit 51, and the acquisition scanning signal E (M) output by the mth sampling driving unit 51 is used as a trigger signal of the (m+1) th sampling driving unit 51, so that the plurality of sampling driving units 51 sequentially output the acquisition scanning signals E (2) to (M) row by row. Where M is a positive integer less than M, and M is the number of sampling driving units 51.

Specifically, the gate signal ABK is used to control the on-time of the gate driving module 40 and the on-time of the driving circuit 50, and the gate signal ABK is configured to display an active level in a display area of each frame of the image signal and to capture an active level in a blanking area (blank area) of each frame of the image signal. In a specific embodiment, the display active level may be a high level, and the acquisition active level may be a low level; or the effective level is displayed as low level, the effective level is collected as high level, and the effective level can be specifically set according to the types of trigger devices in the gate driving module 40 and the driving circuit 50; in the embodiment of the application, the display effective level is taken as a high level, and the acquisition effective level is taken as a low level for illustration; that is, in the embodiment of the present application, the strobe signal ABK is configured to be high in the display area of each frame image signal and low in the blanking area of each frame image signal, so that the embodiment will be described.

The effective level is high level, and the acquisition of the effective level is low level for example; that is, in the embodiment of the present application, the strobe signal ABK is configured to be high in the display area of each frame image signal and low in the blanking area of each frame image signal, so that the embodiment will be described.

Through the above arrangement, the gate driving module 40 outputs the image scanning signals G (1) to G (M) in the display area stage of each frame of the image signal by controlling the gate signal ABK, so that the driving circuit 50 outputs the acquisition scanning signals E (1) to E (M) in the blanking area of each frame of the image signal, and the voltage acquisition stage is not required to be additionally added in each frame of the image signal, thereby avoiding reducing the refresh rate of the display panel 10, and acquiring the pixel voltages by outputting the acquisition scanning signals E (1) to E (M) in the blanking area, so that the image display of the display panel 10 is not affected. Meanwhile, through the above arrangement, the structure of the driving circuit 50 is similar to that of the gate driving module 40, and the driving circuit 50 and the gate driving module 40 can share the scan clock signal EK and the acquisition start signal RESET, and the RESET signal of the display panel 10 can be used as the acquisition start signal RESET, so that the driving circuit 50 can be prepared together with the gate driving module 40, and an additional design and preparation of acquisition time sequence chips are not needed, thereby effectively reducing the number of chips in the bonding area of the display panel 10 and the process cost.

Specifically, each sampling driving unit includes a triggering unit 511, an output unit 512, and a pull-down unit 513; wherein the number of scan clock signals EK is 2. Wherein, in the first sampling driving unit 51:

the triggering unit 511 is mainly used for controlling the on time of the output unit 512, so as to realize progressive scanning of the display panel 10. Specifically, the trigger unit 511 includes a first transistor T1, where a gate of the first transistor T1 is connected to the strobe signal ABK as a trigger control terminal, a source is connected to the acquisition start signal RESET as a trigger control terminal, and when the strobe signal ABK is at an acquisition active level, the first transistor T1 is turned on to output the first row scan control signal Q (1) at a drain.

The output unit 512 is mainly configured to output the corresponding first scan clock signal EK (1) as the first line acquisition scan signal E (1). Specifically, the output unit 512 includes a second transistor T2 and a bootstrap capacitor C, where a gate of the second transistor T2 is electrically connected to a drain of the first transistor T1, a source is connected to the first scan clock signal EK (1) as a scan input end, and a drain is connected to the first row acquisition scan line Em (1) as a scan output end, and is configured to generate and output an acquisition scan signal E (1) of the first row; the two ends of the bootstrap capacitor C are electrically connected to the gate and the drain of the second transistor T2, respectively, for charging when the first row scan control signal Q (1) is at a high level, storing the voltage at the gate drain of the second transistor T2, and when the first sampling driving unit 51 outputs the first row scan signal E (1), raising the voltage at the gate of the second transistor T2 for the second time, that is, when the first scan clock signal EK (1) is at a high level, the potential of the first row scan control signal Q (1) is raised under the coupling effect of the bootstrap capacitor C, so as to ensure that the second transistor T2 can be reliably turned on and output the first row scan signal E (1).

The pull-down unit 513 is configured to pull down the gate potential and the drain potential of the second transistor T2 to low potential immediately, i.e. turn off the acquisition scan signal E (1) of the first row. Specifically, the pull-down unit 513 includes a third transistor T3 and a fourth transistor T4, where a source of the third transistor T3 and a source of the fourth transistor T4 are electrically connected to a gate and a drain of the second transistor T2, respectively, a drain of the third transistor T3 and a drain of the fourth transistor T4 are commonly connected to the low level signal VSS, and a gate of the third transistor T3 and a gate of the fourth transistor T4 are commonly connected to the acquisition scan signal E (2) output by the next stage sampling driving unit 51. Wherein the third transistor T3 is for pulling down the potential of the scan control signal Q (1) of the first row so as to turn off the second transistor T2; the fourth transistor T4 acts on the acquisition scan line Em (1) of the first row for pulling down the potential of the acquisition scan signal E (1) of the first row.

Each sample driving unit 51 after the first sample driving unit 51:

First, it should be noted that the symbol k appearing hereinafter is a positive integer greater than 0, specifically, (k+1) denotes the number of the current stage sampling driving unit 51, k denotes the number of the previous stage sampling driving unit 51, and (k+2) denotes the number of the next stage sampling driving unit 51.

Each trigger unit 511 includes a fifth transistor T5, where a gate and a source of the fifth transistor T5 are connected and serve as trigger control terminals, and are connected to the scan output terminal of the previous stage sampling driving unit 51, and a drain of the fifth transistor T5 is electrically connected to the scan control terminal of the output unit 512. That is, the acquisition scan signal E (k) output from the previous stage sampling driving unit 51 serves as a trigger signal of the current stage sampling driving unit 51, and when the acquisition scan signal E (k) is at a high level, the fifth transistor T5 is turned on to output the (k+1) th row scan control signal Q (k+1) at the drain for controlling the turn-on time of the current stage output unit 512.

Each output unit 512 is mainly configured to output the scan clock signal EK (j) corresponding to the current stage as the acquisition scan signal E (k+1) corresponding to the row. Specifically, the structure and function of each output unit 512 are similar to those of the output unit 512 of the first sampling driving unit 51, each output unit 512 also includes a second transistor T2 and a bootstrap capacitor C, the gate of the second transistor T2 is electrically connected to the drain of the first transistor T1, the source is connected to the scan clock signal EK (j) corresponding to the current stage as a scan input terminal, the drain is connected to the acquisition scan line Em (k+1) corresponding to the row as a scan output terminal, and the drain is used for generating and outputting the acquisition scan signal E (k+1) corresponding to the row; the two ends of the bootstrap capacitor C are electrically connected to the gate and the drain of the second transistor T2, respectively, and are used for charging when the current line scan control signal Q (k+1) is at a high level, storing the voltage at the gate drain of the second transistor T2, and when the current level sampling driving unit 51 outputs the current line acquisition scan signal E (k+1), raising the voltage of the gate of the second transistor T2 for the second time, that is, when the corresponding scan clock signal EK (j) of the current level is at a high level, the potential of the current level scan control signal Q (k+1) is raised under the coupling effect of the bootstrap capacitor C, so as to ensure that the second transistor T2 can be reliably turned on and output the current line acquisition scan signal E (k+1).

Each pull-down unit 513 is configured to pull down the gate potential and the drain potential of the second transistor T2 of the current stage to low potential immediately, i.e., turn off the acquisition scan signal E (k+1) of the corresponding row. Specifically, similar to the pull-down unit 513 in the first sampling driving unit 51, the pull-down unit 513 of this stage also includes a third transistor T3 and a fourth transistor T4, the source of the third transistor T3 and the source of the fourth transistor T4 are electrically connected to the gate and the drain of the second transistor T2, respectively, the drain of the third transistor T3 and the drain of the fourth transistor T4 are commonly connected to the low level signal VSS, and the gate of the third transistor T3 and the gate of the fourth transistor T4 are commonly connected to the acquisition scan signal E (k+2) output by the next stage sampling driving unit 51. Wherein the third transistor T3 is used to pull down the scan control signal Q (k+1) of the present row so as to turn off the second transistor T2; the fourth transistor T4 acts on the acquisition scan line Em (k+1) of the corresponding row for pulling down the potential of the acquisition scan signal E (k+1) of the present row.

Referring to fig. 3, fig. 3 is a timing chart illustrating the operation of the driving circuit provided in the embodiment of fig. 2. Specifically, the number of the scan clock signals EK in the present embodiment is 2, and the first scan clock signal EK (1) and the second scan clock signal EK (2) alternately output high levels in sequence.

In the display area stage, the strobe signal ABK is at a high level, and in the initial stage of the stage, the frame start signal STV is at a high level to trigger the gate driving module 40, so that the gate driving module 40 sequentially outputs the image scan signals G (1) to G (M) row by row based on the two scan clock signals EK (1) and EK (2).

In the period of the vanishing area, the strobe signal ABK is at a low level, and in the initial stage of the period, the acquisition start signal RESET is at a high level to trigger the first stage sampling driving unit 51 to output the first scan clock signal EK (1) as the first line acquisition scan signal E (1), and after the first line acquisition scan signal E (1) is output, the sampling driving units 51 at each stage sequentially output the acquisition scan signals E (2) to E (M) of the corresponding line by line. Where M is the number of sampling driving units 51.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a display device according to a second embodiment of the application. In the display device 100 provided in this embodiment, the gate driving module 40 includes a first gate driving module 41 and a second gate driving module 42, which are respectively disposed on two opposite sides of the display panel 10; the driving circuit 50 includes a first driving circuit 501 and a second driving circuit 502, which are disposed on opposite sides of the display panel 10, respectively, and are disposed adjacent to the first gate driving module 41 and the second gate driving module 42, respectively.

The first gate driving module 41 includes a plurality of scan signal terminals electrically connected to a plurality of odd-numbered image scan lines, respectively, for outputting odd-numbered image scan signals G (2 i-1). The second gate driving module 42 includes a plurality of scan signal terminals electrically connected to a plurality of even numbered image scan lines, respectively, for outputting even numbered image scan signals G (2 i). Wherein i is a positive integer greater than 0.

Referring to fig. 5 in combination, fig. 5 is a schematic structural diagram of the driving circuit provided in the embodiment of fig. 4. In the driving circuit 50, the first two sampling driving units 51, i.e., the first stage sampling driving unit 51 and the second stage sampling driving unit 51, have similar structures to the first sampling driving unit 51 in the embodiment of fig. 2, except that the scan input end of the first stage sampling driving unit 51 in the embodiment is connected to the first scan clock signal EK (1), and the scan input end of the second stage sampling driving unit 51 is connected to the second scan clock signal EK (2), so that the first stage sampling driving unit 51 outputs the first row acquisition scan signal E (1), and the second stage sampling driving unit 51 outputs the second row acquisition scan signal E (2).

Further, in this embodiment, the sampling driving units 51 with odd numbers are sequentially cascaded to form a first driving circuit 501 for outputting an odd-numbered line acquisition scanning signal E (2 i-1); the sampling driving units 51 with even serial numbers are sequentially cascaded to form a second driving circuit 502 for outputting an even line acquisition scanning signal E (2 i). The first driving circuit 501 is disposed on a first side of the display panel 10 and adjacent to the first gate driving module 41, and the second driving circuit 502 is disposed on a second side of the display panel 10 and adjacent to the second gate driving module 42, and the first side is opposite to the second side.

Specifically, the acquisition scan signal E (m) output by the mth stage sampling driving unit 51 is used as a trigger signal of the (m+2) th stage sampling driving unit 51, and the pull-down unit 513 in the current stage sampling driving unit 51 accesses the acquisition scan signal E (m+1) output by the next stage sampling driving unit 51, so that when the acquisition scan signal E (m+1) output by the next stage sampling driving unit 51 is at a high level, the acquisition scan signal E (m) of the current stage is immediately turned off.

Referring to fig. 6, fig. 6 is a timing diagram illustrating the operation of the driving circuit provided in the embodiment of fig. 5. Specifically, the number of the scan clock signals EK in the present embodiment is 4, and the first scan clock signal EK (1), the second scan clock signal EK (2), the third scan clock signal EK (3), and the fourth clock signal EK (4) are sequentially and alternately output as high levels.

In the display area stage, the strobe signal ABK is at a high level, and in the initial stage of the stage, the frame start signal STV is at a high level to trigger the gate driving module 40, so that the gate driving module 40 sequentially outputs the image scan signals G (1) to G (M) row by row based on the four scan clock signals EK (1) to EK (4).

In the period of the blanking area, the strobe signal ABK is low, the acquisition start signal RESET is high in the initial stage of the period, and in the period of the acquisition start signal RESET being high, the first stage sampling driving unit 51 and the second stage sampling driving unit 51 sequentially output the high level of the first line acquisition scan signal E (1) and the high level of the second line acquisition scan signal E (2), and after the first two lines acquisition scan signals E (1) to E (2) are output, the respective stages of sampling driving units 51 sequentially output the acquisition scan signals E (3) to E (M) of the corresponding lines line by line.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a driving circuit according to a third embodiment of the present application. In the driving circuit 50 provided in this embodiment, the first K sampling driving units 51, that is, the 1 st to the K-th sampling driving units 51 are similar to the first sampling driving unit 51 in the embodiment of fig. 2, except that the scan input ends in the first to the K-th sampling driving units 51 in this embodiment are respectively connected to the first to the K-th scan clock signals EK (1) to EK (K) so that the first K-th sampling driving units 51 sequentially output the acquisition scan signals E (1) to E (K) line by line. Wherein K is an integer greater than 0. In this embodiment, the number of the scan clock signals EK is 2K.

Further, in the present embodiment, the sampling driving units 51 having the sequence number (m+i·k) are sequentially cascaded to output the acquisition scan signals E (m+i·k) having the sequence number (m+i·k) of the rows. Wherein M is a positive integer greater than 0 and less than or equal to K, i is a natural number, and (m+i.K) is less than or equal to M.

Specifically, the acquisition scan signal E (m) output by the mth stage sampling driving unit 51 is used as a trigger signal of the (m+k) th stage sampling driving unit 51, and the pull-down unit 513 in the current stage sampling driving unit 51 accesses the acquisition scan signal E (m+1) output by the next stage sampling driving unit 51, so that when the acquisition scan signal E (m+1) output by the next stage sampling driving unit 51 is at a high level, the acquisition scan signal E (m) of the current stage is immediately turned off.

Referring to fig. 8 and 9, fig. 8 is a schematic structural diagram of a display device according to a fourth embodiment of the present application, and fig. 9 is a schematic structural diagram of an embodiment of the driving circuit in fig. 8. In this embodiment, the driving circuit 50 also serves as a gate driving module 40 for transmitting the image scanning signals G (1) to G (M) to the plurality of sub-pixel units 11. In general, the gate driving module 40 and the driving circuit 50 mainly include opaque materials made of metal, semiconductor, etc., so a black shielding layer is usually disposed to shield the gate driving module 40 and the driving circuit 50, which is also a reason for the frame of the display device 100. In the present embodiment, by multiplexing the driving circuit 50 as the gate driving module 40, the area of the frame region is reduced, and thus the frame width and length of the display device 100 can be reduced.

Specifically, the first K sampling driving units 51 of the driving circuit 50 further include a first gate switch 514, where the first gate switch 514 includes a first gate control terminal, a first access terminal, a second access terminal, and a first output terminal; the first gating control end is used as a trigger control end to access the gating signal ABK, the first access end is used as a first trigger input end to access the frame start signal STV, and the second access end is used as a second trigger input end to access the acquisition start signal RESET.

Each sample driving unit 51 further includes a second gate switch 515 and a third gate switch 516. The second gate switch 515 includes a second gate control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal; the second gating control end is connected with a gating signal ABK, the scanning receiving end is connected with the scanning output end, the first scanning output end is connected with a corresponding image scanning line, the second scanning output end is connected with a corresponding acquisition scanning line, and the first scanning output end and the second scanning output end are connected with the trigger control end of the next cascaded sampling driving unit 51; the third gate switch 516 includes a third gate control end, a first pull-down end, a second pull-down end, and a pull-down access end, where the third gate control end is connected to the gate signal ABK, the first pull-down end is connected to the image scanning signal output by the next-stage sampling driving unit 51, the second pull-down end is connected to the acquisition scanning signal output by the next-stage sampling driving unit 51, and the pull-down access end is connected to the pull-down unit 513.

The strobe signal ABK is configured to be high in the display region of each frame of the image signal and low in the blanking region.

When the strobe signal ABK is at a high level, the first strobe switch 514 turns on the first access terminal and the first output terminal, and the second strobe switch 515 turns on the scan receiving terminal and the first scan output terminal, so that the sampling driving units 51 of each stage sequentially output the image scan signal line by line. Meanwhile, the third gate switch 516 turns on the first pull-down terminal and the pull-down access terminal to turn off the image scanning signal output from the current stage sampling driving unit 51 when the next stage sampling driving unit 51 outputs the image scanning signal.

When the strobe signal ABK is at a low level, the first strobe switch 514 turns on the second access terminal and the first output terminal, and the second strobe switch 515 turns on the scan receiving terminal and the second scan output terminal, so that the sampling driving units 51 at each stage sequentially output the acquisition scan signals G (1) to G (M) line by line. Meanwhile, the third gate switch 516 turns on the second pull-down terminal and the pull-down access terminal to close the acquisition scan signals E (1) to E (M) output by the current stage sampling driving unit 51 when the next stage sampling driving unit 51 outputs the acquisition scan signal.

In the present embodiment, taking k=1 as an example, the driving circuit 50 is provided on one side of the display panel 10, and is configured to output image scanning signals G (1) to G (M) to the display panel 10 in the display area of each frame of image signals, and to output acquisition scanning signals E (1) to E (M) to the display panel 10 in the blanking area of each frame of image signals.

In the present embodiment, the operation timing of the driving circuit 50 is the same as that of fig. 3, and referring to fig. 3, the number of the scan clock signals EK is 2, and the first scan clock signals EK (1) and the second scan clock signals EK (2) alternately output high levels in turn.

In the display area stage, the gate signal ABK is at a high level to control the driving circuit 50 to turn on the first access terminal and the first output terminal of the first gate switch 514 and turn on the scan receiving terminal and the first scan output terminal of the second gate switch 515, so as to obtain that the driving circuit 50 is turned on with the image scan lines S (1) to S (M) as a gate driving unit; in the initial stage of this stage, the frame start signal STV is high to trigger the driving circuit 50 to sequentially output the image scanning signals G (1) to G (M) row by row.

In the vanishing area stage, the gate signal ABK is at a low level to control the driving circuit 50 to turn on the second access terminal and the first output terminal, and to turn on the scan receiving terminal and the second scan output terminal of the second gate switch 515, so that the driving circuit 50 is turned on with the acquisition scan lines Em (1) to Em (M); in the initial stage of this stage, the acquisition start signal RESET is at a high level to trigger the sampling driving units 51 at each stage to sequentially output the acquisition scan signals E (1) to E (M) of the corresponding row by row. Where M is the number of sampling driving units 51.

Referring to fig. 10, fig. 10 is a schematic diagram of another embodiment of the driving circuit in fig. 8. In this embodiment, the first gating switch 514 includes a sixth transistor T6 and a seventh transistor T7, the sixth transistor T6 is an N-type transistor, and the seventh transistor T7 is a P-type transistor; the grid electrode of the sixth transistor T6 is connected with the first gating control end, the source electrode is connected with the first access end, and the drain electrode is connected with the first output end; the gate of the seventh transistor T7 is connected to the first gate control terminal, the source is connected to the second access terminal, and the drain is connected to the first output terminal.

The second gate switch 515 includes an eighth transistor T8 and a ninth transistor T9, the eighth transistor T8 being an N-type transistor, the ninth transistor T9 being a P-type transistor; the grid electrode of the eighth transistor T8 is connected with the second gating control end, the source electrode is connected with the scanning receiving end, and the drain electrode is connected with the first scanning output end; the gate of the ninth transistor T9 is connected to the second gate control terminal, the source is connected to the scan receiving terminal, and the drain is connected to the second scan output terminal.

The third gating switch 516 includes a first pull-down transistor T11 and a second pull-down transistor T12, the first pull-down transistor T11 being an N-type transistor and the second pull-down transistor T12 being a P-type transistor; the grid electrode of the first pull-down transistor T11 is connected with the third gating control end, the source electrode is connected with the first pull-down end, and the drain electrode is connected with the pull-down access end; the gate of the second pull-down transistor T12 is connected to the third gate control terminal, the source is connected to the second pull-down terminal, and the drain is connected to the pull-down access terminal.

Specifically, when the gate signal ABK is at a high level, the sixth transistor T6, the eighth transistor T8, and the first pull-down transistor T11 are turned on, and the driving circuit 50 serves as the gate driving module 40 for sequentially outputting the image scanning signals G (1) to G (M) to the plurality of sub-pixel units 11 row by row in the display area of each frame of the image signal.

When the gate signal ABK is at a low level, the seventh transistor T7, the ninth transistor T9, and the second pull-down transistor T12 are turned on, and the driving circuit 50 is used as an acquisition driving module for sequentially outputting acquisition scan signals E (1) to E (M) to the plurality of sub-pixel units 11 row by row in a blanking area of each frame of image signals.

Referring to fig. 11 and 12, fig. 11 is a schematic structural diagram of a display device according to a fifth embodiment of the present application, and fig. 12 is a schematic structural diagram of a driving circuit according to the embodiment of fig. 11. In the present embodiment, k=2, similarly to the embodiment of fig. 4 and 5, the driving circuit 50 includes a first driving circuit 501 and a second driving circuit 502, except that in the present embodiment, the first driving circuit 501 also serves as the first gate driving module 41 for transmitting the odd-line image scanning signal G (2 i-1) to the display panel 10 at the display area stage of each frame image signal, and the second driving circuit 502 also serves as the second gate driving module 42 for transmitting the even-line image scanning signal G (2 i) to the display panel 10 at the display area stage of each frame image signal; wherein i is a natural number.

The first two sampling driving units 51 of the driving circuit 50 also include a first gate switch 514, and the first gate switch 514 includes a first gate control terminal, a first access terminal, a second access terminal, and a first output terminal, as in the embodiment of fig. 8; the first gating control end is used as a trigger control end to access the gating signal ABK, the first access end is used as a first trigger input end to access the frame start signal STV, and the second access end is used as a second trigger input end to access the acquisition start signal RESET.

Each sampling driving unit 51 further includes a second gate switch 515 and a third gate switch 516, the second gate switch 515 including a second gate control terminal, a scan receiving terminal, a first scan output terminal, and a second scan output terminal; the second gating control end is connected to the gating signal ABK, the scanning receiving end is connected to the scanning output end, the first scanning output end is connected to the corresponding image scanning line S (M), the second scanning output end is connected to the corresponding acquisition scanning line Em (M), and the first scanning output end and the second scanning output end are connected to the trigger control end of the next cascade sampling driving unit 51 so as to transmit trigger signals to the next cascade sampling driving unit 51, so that the driving circuit 50 outputs the image scanning signals G (1) to G (M) and E (1) to E (M) line by line.

The foregoing is only the embodiments of the present application, and therefore, the patent protection scope of the present application is not limited thereto, and all equivalent structures or equivalent flow changes made by the content of the present specification and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. The driving circuit comprises a plurality of sampling driving units, wherein each sampling driving unit comprises a trigger control end, a scanning input end and a scanning output end, the trigger control end is connected with a trigger signal, and the scanning input end is connected with a corresponding scanning clock signal; the sampling driving unit is used for being conducted when the trigger signal is of an effective level so as to output the scanning clock signal as an acquisition scanning signal of a corresponding row at the scanning output end;

The sampling driving unit is characterized in that each sampling driving unit further comprises a trigger input end, the trigger control end is connected with a gating signal, the trigger input end is connected with an acquisition starting signal, and the sampling driving unit is used for respectively outputting front K rows of acquisition scanning signals at the scanning output end when the gating signal is at an acquisition effective level; wherein K is an integer greater than 0;

2. The drive circuit of claim 1, wherein each of the sampling drive units comprises a trigger unit, an output unit, and a pull-down unit; wherein the number of the scanning clock signals is 2K, and among the first K sampling driving units,

3. The drive circuit according to claim 2, wherein in each of the sampling drive units subsequent to the kth sampling drive unit,

Each trigger unit comprises a fifth transistor, wherein the grid electrode and the source electrode of the fifth transistor are connected and serve as the trigger control end, and the drain electrode of the fifth transistor is electrically connected to the scanning control end of the output unit.

4. A display device, comprising:

The driving circuit is a driving circuit as claimed in any one of claims 1-3, wherein a plurality of scanning output ends of the driving circuit are correspondingly connected with the acquisition scanning lines, so as to sequentially output acquisition scanning signals to a plurality of acquisition scanning lines in a vanishing area of each frame of image signals line by line, so that the voltage acquisition units are sequentially turned on line by line, and corresponding pixel voltages are output at the pixel voltage acquisition ends.

5. The display device according to claim 4, wherein the driving circuit further transmits an image scanning signal to the plurality of sub-pixel units as a gate driving module;

The third gating switch comprises a third gating control end, a first pull-down end, a second pull-down end and a pull-down access end, wherein the third gating control end is connected with the gating signal, the first pull-down end is connected with the image scanning signal output by the sampling driving unit at the next stage, the second pull-down end is connected with the acquisition scanning signal output by the sampling driving unit at the next stage, and the pull-down access end is connected with the pull-down unit.

6. The display device according to claim 5, wherein the gate signal is configured to be high in a display area of each frame of the image signal and low in a blanking area;

7. The display device according to claim 6, wherein the first gate switch includes a sixth transistor and a seventh transistor, wherein the sixth transistor is an N-type transistor, and wherein the seventh transistor is a P-type transistor; the grid electrode of the sixth transistor is connected with the first gating control end, the source electrode of the sixth transistor is connected with the first access end, and the drain electrode of the sixth transistor is connected with the first output end; the grid electrode of the seventh transistor is connected with the first gating control end, the source electrode of the seventh transistor is connected with the second access end, and the drain electrode of the seventh transistor is connected with the first output end;

8. The display device of claim 7, wherein the display device comprises a display device,

9. A display device according to claim 4 or 6, wherein in the driving circuit, K is equal to 1; the driving circuit is arranged on one side of the display panel and is used for outputting the image scanning signals and/or the acquisition scanning signals to the display panel.

10. A display device according to claim 4 or 6, wherein in the driving circuit, K is equal to 2;