CN118012505A - Artificial intelligence processors, integrated circuit chips, boards, electronic devices - Google Patents

Abstract

The present disclosure discloses a computing device, an integrated circuit chip, a board card, an electronic apparatus, and a method of performing arithmetic operations using the foregoing computing device. Wherein the computing device may be included in a combined processing device that may also include a universal interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operation designated by the user. The combined processing means may further comprise storage means connected to the device and the other processing means, respectively, for storing data of the device and the other processing means. The scheme disclosed by the invention can improve the operation efficiency of operation in various data processing fields including the artificial intelligence field, so that the overall cost and the cost of operation are reduced.

Description

Artificial intelligence processors, integrated circuit chips, boards, electronic devices

This application is a divisional application of the patent application with application number 202010619460.8, application date June 30, 2020, and invention name “Computing device, integrated circuit chip, board, electronic device and computing method”.

Technical Field

The present disclosure generally relates to the field of computing. More specifically, the present disclosure relates to a computing device, an integrated circuit chip, a board, an electronic device, and a computing method.

Background technique

In a computing system, an instruction set is a set of instructions for performing calculations and controlling the computing system, and plays a key role in improving the performance of computing chips (such as processors) in computing systems. Current computing chips (especially chips in the field of artificial intelligence) use associated instruction sets to complete various general or specific control operations and data processing operations. However, the current instruction set still has many defects. For example, the existing instruction set is limited by the hardware architecture and has poor flexibility. Furthermore, many instructions can only complete a single operation, while the execution of multiple operations usually requires multiple instructions, which potentially leads to an increase in the on-chip I/O data throughput. In addition, the current instructions still have room for improvement in terms of execution speed, execution efficiency, and power consumption caused to the chip.

In addition, the operation instructions of traditional processor CPUs are designed to perform basic single-data scalar operations. Here, single-data operations refer to each operand of the instruction being a scalar data. However, in tasks such as image processing and pattern recognition, the operands are often multi-dimensional vectors (i.e., tensor data) data types, and using only scalar operations cannot enable the hardware to efficiently complete the operation tasks. Therefore, how to efficiently perform multi-dimensional tensor operations is also a problem that needs to be solved in the current computing field.

Summary of the invention

In order to at least solve the problems existing in the above-mentioned prior art, the present disclosure provides a solution of a hardware architecture platform and related instructions. Utilizing the solution disclosed in the present disclosure, the flexibility of instructions can be increased, the efficiency of instruction execution can be improved, and the computing cost and overhead can be reduced. Furthermore, the solution disclosed in the present disclosure supports efficient memory access and processing of tensor data on the basis of the aforementioned hardware architecture, thereby accelerating tensor operations and reducing the computing overhead caused by tensor operations when multi-dimensional vector operands are included in the computing instructions.

In a first aspect, the present disclosure discloses a computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

The main processing circuit is configured to perform main computing operations in response to main instructions,

The slave processing circuit is configured to perform slave computing operations in response to slave instructions,

The master operation includes a pre-processing operation and/or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The master processing circuit and/or the slave processing circuit are configured to execute respective corresponding master computing operations and/or slave processing operations according to the storage address.

In a second aspect, the present disclosure discloses an integrated circuit chip, which includes the computing device mentioned in the previous aspect and described in a plurality of embodiments later.

In a third aspect, the present disclosure discloses a board comprising the integrated circuit chip mentioned in the previous aspect and described in a plurality of embodiments later.

In a fourth aspect, the present disclosure discloses an electronic device, which includes the integrated circuit chip mentioned in the previous aspect and described in the later embodiments.

In a fifth aspect, the present disclosure discloses a method of performing a computing operation using the aforementioned computing device, wherein the computing device comprises a master processing circuit and at least one slave processing circuit, the method comprising:

configuring the main processing circuit to perform main computing operations in response to main instructions,

configuring the slave processing circuit to perform slave computing operations in response to slave instructions,

The master operation includes a pre-processing operation and/or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The method further includes configuring the master processing circuit and/or the slave processing circuit to execute respective corresponding master computing operations and/or slave processing operations according to the storage address.

By using the computing device, integrated circuit chip, board, electronic device and method disclosed in the present disclosure, the master instructions and slave instructions related to the master operation and the slave operation can be efficiently executed, thereby accelerating the execution of the operation. Further, due to the combination of the master operation and the slave operation, the computing device disclosed in the present disclosure can support more types of operations and operations. In addition, based on the pipeline operation arrangement of the computing device disclosed in the present disclosure, the computing instructions can be flexibly configured to meet the requirements of the calculation.

BRIEF DESCRIPTION OF THE DRAWINGS

By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

FIG. 1a is a schematic diagram showing a computing device according to an embodiment of the present disclosure;

FIG1b is a schematic diagram showing a data storage space according to an embodiment of the present disclosure;

FIG2 is a block diagram illustrating a computing device according to an embodiment of the present disclosure;

3 is a block diagram showing a main processing circuit of a computing device according to an embodiment of the present disclosure;

4a, 4b and 4c are schematic diagrams showing matrix conversion performed by a data conversion circuit according to an embodiment of the present disclosure;

5 is a block diagram showing a slave processing circuit of a computing device according to an embodiment of the present disclosure;

FIG6 is a structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

FIG. 7 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure.

Detailed ways

The scheme disclosed herein utilizes the hardware architecture of the main processing circuit and at least one slave processing circuit to perform associated data operations, so that relatively flexible and simplified calculation instructions can be used to complete relatively complex operations. Specifically, the scheme disclosed herein utilizes the main instructions and slave instructions obtained from the calculation instruction parsing, and the main processing circuit is made to execute the main instruction to implement the main operation, and the slave processing circuit is made to execute the slave instruction to implement the slave operation, so as to implement various complex operations including, for example, vector operations. Here, the main operation operation may include a pre-processing operation and/or a post-processing operation for the slave operation. In one embodiment, the pre-processing operation may be, for example, a data conversion operation and/or a data splicing operation. In another embodiment, the post-processing operation may be, for example, an arithmetic operation on the output result of the slave processing circuit. In some scenarios, when the operand of the calculation instruction includes a descriptor for indicating the shape of a tensor, the scheme disclosed herein utilizes the descriptor to determine the storage address of the operand corresponding data. Based on this, the main processing circuit and/or the slave processing circuit may be configured to perform the respective corresponding main operation and/or slave operation according to the storage address, wherein the main operation and/or the slave operation may involve various types of operation operations of tensor data. In addition, depending on the different computing circuits or operators in the main processing circuit, the computing instructions disclosed herein support flexible and personalized configurations to meet different application scenarios.

The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1a is a schematic diagram showing a computing device 100 according to an embodiment of the present disclosure. As shown in FIG. 1a, the computing device 100 may include a master processing circuit 102 and slave processing circuits, such as the slave processing circuits 104, 106, and 108 shown in the figure. Although three slave processing circuits are shown here, it will be appreciated by those skilled in the art that the computing device 100 of the present disclosure may include any suitable number of slave processing circuits, and multiple slave processing circuits and multiple slave processing circuits and the master processing circuit may be connected in different ways, and the present disclosure does not impose any limitation. In one or more embodiments, the multiple slave processing circuits of the present disclosure may execute various types of slave instructions (e.g., obtained by parsing computing instructions) in parallel to improve the processing efficiency of the computing device.

In the context of the present disclosure, a computing instruction may be an instruction in an instruction system of an interactive interface between software and hardware, which may be a machine language in binary or other forms for hardware such as a processor (or processing circuit) to receive and process. The computing instruction may include an opcode and an operand for indicating the operation of the processor. Depending on different application scenarios, the computing instruction may include one or more opcodes, and when the aforementioned computing instruction includes an opcode, the opcode may be used to indicate multiple operations of the processor. In addition, the computing instruction may also include one or more operands. According to the scheme of the present disclosure, an operand may include a descriptor for indicating the shape of a tensor, which may be used to determine the storage address of the data corresponding to the operand.

In one embodiment, the master instruction and the slave instruction can be obtained by parsing the calculation instruction received by the computing device. In operation, the master processing circuit can be configured to perform the master operation in response to the master instruction, and the slave processing circuit can be configured to perform the slave operation in response to the slave instruction. According to the scheme disclosed herein, the aforementioned master instruction or slave instruction can be a microinstruction or control signal running inside the processor, and can include (or indicate) one or more operations. When the operand of the calculation instruction includes a descriptor as described above, the master processing circuit and/or the slave processing circuit can be configured to access the tensor according to the storage address obtained based on the descriptor. Through the memory access mechanism based on the descriptor, the scheme disclosed herein can significantly improve the reading and storage speed of tensor data in the execution of tensor operations, thereby accelerating the calculation and reducing the calculation overhead.

In one embodiment, the aforementioned main operation may include a pre-processing operation and/or a post-processing operation for the slave operation. Specifically, for the main instruction executed by the main processing circuit, it may include, for example, a pre-processing operation of data conversion and/or data splicing for the data to be involved in the operation. In some application scenarios, the main instruction may also include a pre-processing operation of only selective reading of data, such as reading out the data stored in a dedicated or private buffer and sending it to the slave processing circuit, or generating a corresponding random number for the operation of the slave processing circuit. In some other application scenarios, depending on the type and number of operators included in the main processing circuit, the main instruction may include one or more post-processing operations associated with the functions of the operator. For example, the main instruction may include adding, multiplying, looking up, comparing, averaging, filtering, and other types of operations on the intermediate operation results or final operation results obtained after the slave processing circuit executes the slave instruction. In some application scenarios, the aforementioned intermediate operation results or final operation results may be the aforementioned tensors, and their storage addresses may be obtained according to the descriptors disclosed herein.

In order to facilitate the identification of pre-processing operations and/or post-processing operations, in some application scenarios, the main instruction may include an identification bit for identifying the pre-processing operation and/or post-processing operation. Thus, when the main instruction is obtained, the main processing circuit can determine whether to perform a pre-processing operation or a post-processing operation on the operation data according to the identification bit. Additionally or alternatively, the pre-processing operation and the post-processing operation in the main instruction can be matched by the preset position (or instruction domain segment) of the calculation instruction. For example, when a preset position including (main instruction + slave instruction) is set in the calculation instruction, it can be determined that the main instruction in this calculation instruction involves a pre-processing operation for the slave operation. For another example, when a preset position including (slave instruction + main instruction) is set in the calculation instruction, it can be determined that the main instruction in this calculation instruction involves a post-processing operation for the slave operation. For ease of understanding, assuming that the computing instruction has a length of three segments with predetermined bit widths (i.e., the preset positions mentioned above), the instructions located in the first segment with the predetermined bit width can be designated as the main instructions for pre-processing operations, the instructions located in the second segment with the predetermined bit width in the middle position can be designated as slave instructions for slave operations, and the instructions located in the third segment with the predetermined bit width in the last position can be designated as the main instructions for post-processing operations.

For slave instructions executed by the slave processing circuit, it may include one or more operations associated with the functions of one or more computing circuits in the slave processing circuit. The slave instruction may include an operation of performing operations on data after the master processing circuit performs pre-processing operations. In some application scenarios, the slave instruction may include various operations such as arithmetic operations, logical operations, data type conversion, etc. For example, the slave instruction may include performing various vector-related multiplication and addition operations on the data after the pre-processing operations, including, for example, convolution operations. In other application scenarios, when the aforementioned calculation instructions do not include master instructions regarding pre-processing operations, the slave processing circuit may also directly perform slave operations on the input data according to the slave instructions.

In one or more embodiments, the main processing circuit 102 may be configured to obtain a computing instruction and parse it, thereby obtaining the aforementioned master instruction and slave instruction, and sending the slave instruction to the slave processing circuit. Specifically, the main processing circuit may include one or more decoding circuits (or decoders) for parsing the computing instruction. Through the internal decoding circuit, the main processing circuit may parse the received computing instruction into one or more master instructions and/or slave instructions, and send the corresponding slave instruction to the slave processing circuit so that the slave processing circuit performs the slave operation. Here, depending on the application scenario, the slave instruction can be sent to the slave processing circuit in a variety of ways. For example, when a storage circuit is included in the computing device, the main processing circuit may send the slave instruction to the storage circuit, and send it to the slave processing circuit via the storage circuit. For another example, when multiple slave processing circuits perform parallel operations, the main processing circuit may broadcast the same slave instruction to multiple slave processing circuits. Additionally or optionally, in some hardware architecture scenarios, the computing device may also include a separate circuit, unit or module dedicated to parsing the computing instruction received by the computing device, such as the architecture described later in conjunction with FIG. 2.

In one or more embodiments, the slave processing circuit of the present disclosure may include multiple operation circuits for performing slave operation, wherein the multiple operation circuits may be connected and configured to perform multi-stage pipeline operation. Depending on the operation scenario, the operation circuit may include one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit for performing at least vector operations. In one embodiment, when the computing device of the present disclosure is applied to calculations in the field of artificial intelligence, the slave processing circuit may perform multidimensional convolution operations in a neural network according to slave instructions.

As mentioned above, the main operation and/or slave operation disclosed in the present invention may also include various types of operations on tensor data. For this purpose, the scheme disclosed in the present invention proposes to use descriptors to obtain information related to the shape of the tensor in order to determine the storage address of the tensor data, thereby obtaining and saving the tensor data through the aforementioned storage address.

In one possible implementation, a descriptor can be used to indicate the shape of N-dimensional tensor data, where N is a positive integer, such as N = 1, 2 or 3, or zero. Among them, a tensor can contain multiple forms of data composition, and a tensor can be of different dimensions. For example, a scalar can be regarded as a 0-dimensional tensor, a vector can be regarded as a 1-dimensional tensor, and a matrix can be a tensor of 2 dimensions or more. The shape of a tensor includes information such as the dimension of the tensor and the size of each dimension of the tensor. For example, for a tensor:

The shape of the tensor can be described by the descriptor as (2, 4), that is, the two parameters indicate that the tensor is a two-dimensional tensor, and the size of the first dimension (column) of the tensor is 2, and the size of the second dimension (row) is 4. It should be noted that the present application does not limit the way in which the descriptor indicates the shape of the tensor.

In one possible implementation, the value of N can be determined according to the dimension (order) of the tensor data, or it can be set according to the usage requirements of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor can be used to indicate the shape of the three-dimensional tensor data in three dimensions (e.g., offset, size, etc.). It should be understood that those skilled in the art can set the value of N according to actual needs, and this disclosure does not limit this.

In a possible implementation, the descriptor may include an identifier of the descriptor and/or content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be a number for it; the content of the descriptor may include at least one shape parameter representing the shape of the tensor data. For example, the tensor data is 3D data, and among the three dimensions of the tensor data, the shape parameters of two dimensions are fixed, and the content of its descriptor may include the shape parameter representing another dimension of the tensor data.

In one possible implementation, the identifier and/or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, an on-chip SRAM, or other media cache. The tensor data indicated by the descriptor may be stored in a data storage space (internal memory or external memory), such as an on-chip cache or an off-chip memory. The present disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

In one possible implementation, the identifier, content, and tensor data indicated by the descriptor of the descriptor can be stored in the same area of the internal memory. For example, a continuous area of the on-chip cache can be used to store the relevant content of the descriptor, and its address is ADDR0-ADDR1023. Among them, the address ADDR0-ADDR63 can be used as a descriptor storage space to store the identifier and content of the descriptor, and the address ADDR64-ADDR1023 can be used as a data storage space to store the tensor data indicated by the descriptor. In the descriptor storage space, the identifier of the descriptor can be stored at the address ADDR0-ADDR31, and the content of the descriptor can be stored at the address ADDR32-ADDR63. It should be understood that the address ADDR is not limited to 1 bit or one byte. It is used here to represent an address and is an address unit. Those skilled in the art can determine the descriptor storage space, data storage space, and their specific addresses according to actual conditions, and this disclosure is not limited to this.

In one possible implementation, the identifier and content of the descriptor and the tensor data indicated by the descriptor can be stored in different areas of the internal memory. For example, a register can be used as a descriptor storage space to store the identifier and content of the descriptor, and an on-chip cache can be used as a data storage space to store the tensor data indicated by the descriptor.

In one possible implementation, when a register is used to store the identifier and content of a descriptor, the identifier of the descriptor may be represented by the register number. For example, when the register number is 0, the identifier of the descriptor stored therein is set to 0. When the descriptor in the register is valid, an area may be allocated in the cache space for storing the tensor data according to the size of the tensor data indicated by the descriptor.

In one possible implementation, the identifier and content of the descriptor may be stored in an internal memory, and the tensor data indicated by the descriptor may be stored in an external memory. For example, the identifier and content of the descriptor may be stored on-chip, and the tensor data indicated by the descriptor may be stored off-chip.

In one possible implementation, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, a separate data storage space may be divided for tensor data, and the starting address of each tensor data in the data storage space corresponds to the descriptor one by one. In this case, the control circuit can determine the data address of the data corresponding to the operand in the data storage space according to the descriptor.

In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor may also include at least one address parameter representing the address of the tensor data. For example, the tensor data is 3D data, and when the descriptor points to the address of the tensor data, the content of the descriptor may include an address parameter representing the address of the tensor data, such as the starting physical address of the tensor data, or may include multiple address parameters of the address of the tensor data, such as the starting address + address offset of the tensor data, or the address parameters of the tensor data based on each dimension. Those skilled in the art can set the address parameters according to actual needs, and this disclosure is not limited to this.

In a possible implementation, the address parameter of the tensor data may include a reference address of the data reference point of the descriptor in the data storage space of the tensor data. The reference address may be different according to the change of the data reference point. The present disclosure does not limit the selection of the data reference point.

In a possible implementation, the reference address may include the starting address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is other data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

In a possible implementation, the shape parameters of the tensor data include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address. The data description position is the mapping position of the point or area in the tensor data indicated by the descriptor. For example, when the tensor data is 3D data, the descriptor can use three-dimensional space coordinates (x, y, z) to represent the shape of the tensor data, and the data description position of the tensor data can be the position of the point or area mapped in the three-dimensional space represented by the three-dimensional space coordinates (x, y, z).

It should be understood that those skilled in the art can select shape parameters representing tensor data according to actual conditions, and this disclosure does not limit this. By using descriptors in the data access process, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

In one possible implementation, the content of the descriptor of the tensor data can be determined based on a reference address of a data reference point of the descriptor in the data storage space of the tensor data, a size of the data storage space in at least one of the N dimensional directions, a size of the storage area in at least one of the N dimensional directions, and/or an offset of the storage area in at least one of the N dimensional directions.

FIG1b shows a schematic diagram of a data storage space according to an embodiment of the present disclosure. As shown in FIG1b , the data storage space 21 stores a two-dimensional data in a row-first manner, which can be represented by (x, y) (wherein the X axis is horizontal to the right and the Y axis is vertically downward), the size in the X axis direction (the size of each row) is ori_x (not shown in the figure), the size in the Y axis direction (the total number of rows) is ori_y (not shown in the figure), and the starting address PA_start (reference address) of the data storage space 21 is the physical address of the first data block 22. The data block 23 is part of the data in the data storage space 21, and its offset 25 in the X axis direction is represented as offset_x, the offset 24 in the Y axis direction is represented as offset_y, the size in the X axis direction is represented as size_x, and the size in the Y axis direction is represented as size_y.

In a possible implementation, when a descriptor is used to define the data block 23, the data reference point of the descriptor can use the first data block of the data storage space 21, and the reference address of the descriptor can be agreed to be the starting address PA start of the data storage space 21. Then, the content of the descriptor of the data block 23 can be determined by combining the size ori_x of the data storage space 21 on the X axis, the size ori_y on the Y axis, and the offset offset_y of the data block 23 in the Y axis direction, the offset offset_x in the X axis direction, the size size_x in the X axis direction, and the size size_y in the Y axis direction.

In a possible implementation, the following formula (1) may be used to represent the content of the descriptor:

It should be understood that although in the above examples, the content of the descriptor represents a two-dimensional space, those skilled in the art may set the specific dimension represented by the content of the descriptor according to actual conditions, and the present disclosure does not limit this.

In one possible implementation, a reference address of the data reference point of the descriptor in the data storage space can be agreed upon, and based on the reference address, the content of the descriptor of the tensor data is determined according to the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point.

For example, the reference address PA_base of the data reference point of the descriptor in the data storage space can be agreed upon. For example, a data (for example, data at position (2, 2)) can be selected in the data storage space 21 as the data reference point, and the physical address of the data in the data storage space can be used as the reference address PA_base. The content of the descriptor of the data block 23 in FIG. 1b can be determined according to the positions of the two vertices at the diagonal positions relative to the data reference point. First, the positions of at least two vertices at the diagonal positions of the data block 23 relative to the data reference point are determined, for example, the positions of the vertices at the diagonal positions in the direction from the upper left to the lower right relative to the data reference point, wherein the relative position of the upper left vertex is (x_min, y_min), and the relative position of the lower right vertex is (x_max, y_max), and then the content of the descriptor of the data block 23 can be determined according to the reference address PA_base, the relative position of the upper left vertex (x_min, y_min), and the relative position of the lower right vertex (x_max, y_max).

In a possible implementation, the following formula (2) may be used to represent the content of the descriptor (the base address is PA_base):

It should be understood that although the above example uses the vertices at the upper left corner and the lower right corner to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two vertices at the diagonal positions according to actual needs, and the present disclosure does not limit this.

In a possible implementation, the content of the descriptor of the tensor data can be determined according to the reference address of the data reference point of the descriptor in the data storage space and the mapping relationship between the data description position and the data address of the tensor data indicated by the descriptor. The mapping relationship between the data description position and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional space data, the function f(x, y, z) can be used to define the mapping relationship between the data description position and the data address.

In a possible implementation, the following formula (3) may be used to represent the content of the descriptor:

In a possible implementation, the descriptor is also used to indicate the address of the N-dimensional tensor data, wherein the content of the descriptor also includes at least one address parameter representing the address of the tensor data, for example, the content of the descriptor may be:

Wherein PA is an address parameter. The address parameter can be a logical address or a physical address. The descriptor parsing circuit can use PA as any vertex, middle point or preset point of the vector shape, and combine the shape parameters in the X direction and the Y direction to obtain the corresponding data address.

In a possible implementation, the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address includes a starting address of the data storage space.

In a possible implementation, the descriptor may further include at least one address parameter representing the address of the tensor data. For example, the content of the descriptor may be:

Among them, PA_start is the reference address parameter and will not be repeated here.

It should be understood that those skilled in the art can set the mapping relationship between the data description location and the data address according to actual conditions, and this disclosure does not limit this.

In a possible implementation, an agreed reference address can be set in a task, and the descriptors in the instructions under this task all use this reference address, and the descriptor content may include shape parameters based on this reference address. This reference address can be determined by setting the environmental parameters of this task. The relevant description and use of the reference address can be found in the above embodiment. In this implementation, the content of the descriptor can be mapped to a data address more quickly.

In a possible implementation, the reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the method of setting a common reference address using environmental parameters, each descriptor in this method can describe data more flexibly and use a larger data address space.

In a possible implementation, the data address of the data corresponding to the operand of the processing instruction in the data storage space can be determined according to the content of the descriptor. The calculation of the data address is automatically completed by hardware, and the calculation method of the data address will be different when the content of the descriptor is expressed in different ways. The present disclosure does not limit the specific calculation method of the data address.

For example, the content of the descriptor in the operand is expressed using formula (1), the offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, and the size is size_x*size_y. Then, the starting data address PA1 _{(x, y)} of the tensor data indicated by the descriptor in the data storage space can be determined using the following formula (4):

PA1 _(x,y) = PA_start + (offset_y-1)*ori_x + offset_x (4)

According to the data starting address PA1 _{(x, y)} determined by the above formula (4), combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of the tensor data indicated by the descriptor in the data storage space can be determined.

In one possible implementation, when the operand also includes a data description position for the descriptor, the data address of the data corresponding to the operand in the data storage space can be determined according to the content of the descriptor and the data description position. In this way, part of the data (e.g., one or more data) in the tensor data indicated by the descriptor can be processed.

For example, the content of the descriptor in the operand is expressed using formula (1), the offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, the size is size_x*size_y, and the data description position for the descriptor included in the operand is ( _xq , _yq ), then the data address PA2 _{(x, y)} of the tensor data indicated by the descriptor in the data storage space can be determined using the following formula (5):

PA2 _{(x, y)} = PA_start + (offset_y + _yq - 1) * ori_x + (offset_x + _xq ) (5)

The computing device disclosed in the present invention is described above in conjunction with FIG. 1a and FIG. 1b. By utilizing the computing device disclosed in the present invention and the master instruction and the slave instruction, multiple operations can be completed using one computing instruction, which reduces the data handling required for each instruction caused by multiple operations being completed by multiple instructions, solves the IO bottleneck problem of the computing device, and effectively improves the efficiency of computing and reduces the overhead of computing. In addition, the scheme disclosed in the present invention can also flexibly set the type and number of operations included in the computing instruction according to the type of arithmetic unit configured in the main processing circuit, the function of the arithmetic circuit configured in the slave processing circuit, and through the collaboration of the main processing circuit and the slave processing circuit, so that the computing device can perform various types of computing operations, thereby expanding and enriching the application scenarios of the computing device and meeting different computing needs.

In addition, since the main processing circuit and the slave processing circuit can be configured to support multi-stage pipeline operations, the execution efficiency of the operators in the main processing circuit and the slave processing circuit is improved, and the calculation time is further shortened. According to the above description, those skilled in the art can understand that the hardware architecture shown in Figure 1a is only exemplary and not restrictive. Under the disclosure and teaching of the present disclosure, those skilled in the art can also add new circuits or devices based on the architecture to achieve more functions or operations. For example, a storage circuit can be added to the architecture shown in Figure 1a to store various instructions and data (such as tensor data). Furthermore, the main processing circuit and the slave processing circuit can also be arranged in different physical or logical positions, and the two can be connected through various data interfaces or interconnection units, so as to complete the above main operation and slave operation through the interaction between the two, including various operations on the tensors described in conjunction with Figure 1b.

FIG2 is a block diagram of a computing device 200 according to an embodiment of the present disclosure. It is understood that the computing device 200 shown in FIG2 is a specific implementation of the computing device 100 shown in FIG1a, and therefore the details of the master processing circuit and the slave processing circuit of the computing device 100 described in conjunction with FIG1a are also applicable to the computing device 200 shown in FIG2.

As shown in FIG2 , the computing device 200 according to the present disclosure includes a master processing circuit 202 and a plurality of slave processing circuits 204, 206, and 208. Since the operations of the master processing circuit and the slave processing circuit are described in detail in the foregoing text in conjunction with FIG1a , they will not be repeated here. In addition to including the same master processing circuit and slave processing circuit as the computing device 100 shown in FIG1a , the computing device 200 of FIG2 also includes a control circuit 210 and a storage circuit 212. In one embodiment, the control circuit may be configured to obtain the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction, and send the master instruction to the master processing circuit 202 and send the slave instruction to one or more of the plurality of slave processing circuits 204, 206, and 208. In one scenario, the control circuit may send the slave instruction obtained after parsing to the slave processing circuit through the master processing circuit, as shown in FIG2 . Alternatively, when there is a connection between the control circuit and the slave processing circuit, the control circuit may also directly send the parsed slave instruction to the slave processing circuit. Similarly, when there is a connection between the storage circuit and the slave processing circuit, the control circuit may also send the slave instruction to the slave processing circuit via the storage circuit. In some computing scenarios, when the computing instruction includes an operand involving a tensor operation, the control circuit may use the descriptor discussed above to determine the storage address of the data corresponding to the operand, such as the starting address of the tensor, and may instruct the master processing circuit or the slave processing circuit to obtain the tensor data involved in the tensor operation from the corresponding storage address in the storage circuit 212 so as to perform the tensor operation.

In one or more embodiments, the storage circuit 212 may store various types of data or instructions related to the calculation, such as the tensors described above. In one scenario, the storage circuit may store neuron or weight data related to the neural network operation, or store the final operation result obtained after the main processing circuit performs the post-processing operation. Additionally, the storage circuit may store the intermediate result obtained after the main processing circuit performs the pre-processing operation, or the intermediate result obtained after the slave processing circuit performs the operation operation. In the operation for the tensor, the aforementioned intermediate result may also be data of the tensor type, and is read and stored by the storage address determined by the descriptor. In some application scenarios, the storage circuit may be used as an on-chip memory of the computing device 200 to perform data read and write operations with the off-chip memory, such as through a direct memory access ("DMA") interface. In some scenarios, when the calculation instruction is parsed by the control circuit, the storage circuit may store the operation instruction obtained after the control circuit is parsed, such as the master instruction and/or the slave instruction. In addition, although the storage circuit is shown in a block diagram in FIG2, depending on the application scenario, the storage circuit can be implemented as a memory including a main memory and a main cache, wherein the main memory can be used to store relevant operation data such as neurons, weights and various constant terms, and the main cache module can be used to temporarily store intermediate data, such as data after the pre-processing operation and data before the post-processing operation, and these intermediate data may be invisible to the operator according to the settings.

In the interactive application of the main memory and the main processing circuit, the pipeline operation circuit in the main processing circuit can also perform corresponding operations with the help of the mask stored in the main storage circuit. For example, in the process of performing pipeline operations, the operation circuit can read a mask from the main storage circuit, and the mask can be used to indicate whether the data performing the operation in the operation circuit is valid. The main storage circuit can not only perform internal storage applications, but also has the function of data interaction with the storage device outside the computing device of the present disclosure, for example, it can exchange data with the external storage device through direct memory access ("DMA").

FIG3 is a block diagram showing a main processing circuit 300 of a computing device according to an embodiment of the present disclosure. It can be understood that the main processing circuit 300 shown in FIG3 is also the main processing circuit shown and described in conjunction with FIG1a and FIG2, so the description of the main processing circuit in FIG1a and FIG2 is also applicable to the description below in conjunction with FIG3.

As shown in FIG3 , the main processing circuit 300 may include a data processing unit 302, a first group of pipeline operation circuits 304 and a last group of pipeline operation circuits 306, and one or more groups of pipeline operation circuits (replaced by black circles) located between the two groups. In one embodiment, the data processing unit 302 includes a data conversion circuit 3021 and a data splicing circuit 3022. As described above, when the main operation operation includes a pre-processing operation for the slave operation operation, such as a data conversion operation or a data splicing operation, the data conversion circuit 3021 or the data splicing circuit 3022 will perform the corresponding conversion operation or splicing operation according to the corresponding main instruction. The conversion operation and the splicing operation will be explained by examples below.

As far as the data conversion operation is concerned, when the data bit width input to the data conversion circuit is high (for example, the data bit width is 1024 bits wide), the data conversion circuit can convert the input data into data with a lower bit width (for example, the output data bit width is 512 bits wide) according to the operation requirements. According to different application scenarios, the data conversion circuit can support conversions between multiple data types, for example, FP16 (16-bit floating point), FP32 (32-bit floating point), FIX8 (8-bit fixed point), FIX4 (4-bit fixed point), FIX16 (16-bit fixed point) and other data types with different bit widths can be converted. When the data input to the data conversion circuit is a matrix, the data conversion operation can be a transformation performed on the arrangement position of the matrix elements. The transformation can, for example, include matrix transposition and mirroring (described later in conjunction with Figures 4a-4c), matrix rotation at a predetermined angle (for example, 90 degrees, 180 degrees or 270 degrees) and matrix dimension conversion.

As for the data splicing operation, the data splicing circuit can perform operations such as parity splicing on the data blocks extracted from the data according to the bit length set in the instruction, for example. For example, when the data bit length is 32 bits, the data splicing circuit can divide the data into 8 data blocks 1 to 8 according to the bit width length of 4 bits, and then splice the data blocks 1, 3, 5 and 7 together, and splice the data blocks 2, 4, 6 and 8 together for operation.

In other application scenarios, the above-mentioned data splicing operation can also be performed on the data M (for example, a vector) obtained after performing the operation. It is assumed that the data splicing circuit can first split the lower 256 bits of the even-numbered rows of the data M as 1 unit data with an 8-bit bit width to obtain 32 even-numbered row unit data (represented as M_2i ₀ to M_2i ₃₁ respectively). Similarly, the lower 256 bits of the odd-numbered rows of the data M can also be split as 1 unit data with an 8-bit bit width to obtain 32 odd-numbered row unit data (represented as M_(2i+1) ₀ to M_(2i+1) ₃₁ respectively). Further, the 32 odd-numbered row unit data and the 32 even-numbered row unit data after the split are alternately arranged in sequence according to the order of the data bits from low to high, first the even-numbered rows and then the odd-numbered rows. Specifically, the even-numbered row unit data 0 (M_2i ₀ ) is arranged in the low position, and then the odd-numbered row unit data 0 (M_(2i+1) ₀ ) is arranged in sequence. Next, even-numbered row unit data 1 (M_2i ₁ ) ... are arranged. Similarly, when the arrangement of odd-numbered row unit data 31 (M_(2i+1) ₃₁ ) is completed, 64 unit data are concatenated together to form a new data with a bit width of 512 bits.

According to different application scenarios, the data conversion circuit and the data splicing circuit in the data processing unit can be used together to perform data pre-processing more flexibly. For example, according to different operations included in the main instruction, the data processing unit can only perform data conversion without performing data splicing operations, only perform data splicing operations without performing data conversion, or perform both data conversion and data splicing operations. In some scenarios, when the main instruction does not include pre-processing operations for slave operation operations, the data processing unit can be configured to disable the data conversion circuit and the data splicing circuit.

As mentioned above, the main processing circuit according to the present disclosure may include one or more groups of multi-stage pipeline operation circuits, such as two groups of multi-stage pipeline operation circuits 304 and 306 shown in Figure 3, wherein each group of multi-stage pipeline operation circuits performs multi-stage pipeline operations including the first level to the Nth level, wherein each level may include one or more operators, so as to perform multi-stage pipeline operations according to the main instruction. In one embodiment, the main processing circuit of the present disclosure can be implemented as a single instruction multiple data (Single Instruction Multiple Data, SIMD) module, and each group of multi-stage pipeline operation circuits can form an operation pipeline. The operation pipeline can be set up with different numbers of different or identical functional modules (i.e., operators of the present disclosure) step by step according to the operation requirements, such as various types of functional modules such as addition modules (or adders), multiplication modules (or multipliers), and table lookup modules (or table lookups).

In some application scenarios, when the order requirements of the pipeline are met, different functional modules on a pipeline can be used in combination, and one level of pipeline completes the operation represented by an operation code ("op") in a microinstruction. Therefore, the SIMD disclosed in the present invention can support different levels of pipeline operations. That is, based on the setting of the operator in the operation pipeline, the SIMD disclosed in the present invention can flexibly support the combination of different numbers of ops.

Assume that there is a pipeline similar to the first group of multi-stage pipeline operation circuits 304 and the second group of multi-stage pipeline operation circuits 306 (named "stage 1"), which is provided with six functional modules in order from top to bottom to form a six-stage pipeline, specifically: stage 1-1-adder 1 (first-stage adder), stage 1-2-adder 2 (second-stage adder), stage 1-3-multiplier 1 (first-stage multiplier), stage 1-4-multiplier 2 (second-stage multiplier), stage 1-5-adder 1 (first-stage adder), stage 1-6-adder 2 (second-stage adder). It can be seen that the first-stage adder (which serves as the first stage of the pipeline) and the second-stage adder (which serves as the second stage of the pipeline) are used in conjunction to complete the two-stage operation of the addition operation. Similarly, the first-stage multiplier and the second-stage multiplier also perform similar two-stage operations. Of course, the two-stage adder or multiplier here is merely exemplary and not restrictive. In some application scenarios, only one-stage adder or multiplier may be provided in a multi-stage pipeline.

In some embodiments, two or more pipelines as described above may also be provided, wherein each pipeline may include a number of identical or different operators to implement identical or different functions. Further, different pipelines may include different operators so that each pipeline implements operations of different functions. The operators or circuits implementing the aforementioned different functions may include, but are not limited to, random number processing circuits, addition and subtraction circuits, subtraction circuits, table lookup circuits, parameter configuration circuits, multipliers, dividers, poolers, comparators, absolute value circuits, logic operators, position index circuits or filters. Here, a pooler is taken as an example, which may be exemplarily composed of operators such as adders, dividers, and comparators to perform pooling operations in a neural network.

In some application scenarios, the multi-stage pipeline operation in the main processing circuit can support unary operations (i.e., there is only one input data). Taking the operation at the scale layer + relu layer in the neural network as an example, it is assumed that the calculation instruction to be executed is expressed as result = relu (a * ina + b), where ina is the input data (for example, it can be a vector, a matrix or a tensor), and a and b are both operation constants. For this calculation instruction, a set of three-stage pipeline operation circuits including multipliers, adders, and nonlinear operators disclosed in the present disclosure can be used to perform the operation. Specifically, the multiplier of the first-stage pipeline can be used to calculate the product of the input data ina and a to obtain the first-stage pipeline operation result. Then, the adder of the second-stage pipeline can be used to perform an addition operation on the first-stage pipeline operation result (a * ina) and b to obtain the second-stage pipeline operation result. Finally, the relu activation function of the third-stage pipeline can be used to activate the second-stage pipeline operation result (a * ina + b) to obtain the final operation result result.

In some application scenarios, the multi-stage pipeline operation circuit in the main processing circuit can support binary operations (for example, the convolution calculation instruction result = conv (ina, inb)) or ternary operations (for example, the convolution calculation instruction result = conv (ina, inb, bias)), where the input data ina, inb and bias can be either a one-dimensional tensor (i.e., a vector, which can be, for example, integer, fixed-point or floating-point data), or a two-dimensional tensor (i.e., a matrix), or a tensor of 3 dimensions or more. Here, taking the convolution calculation instruction result = conv (ina, inb) as an example, the convolution operation expressed by the calculation instruction can be performed using multiple multipliers, at least one addition tree and at least one nonlinear operator included in the three-stage pipeline operation circuit structure, where the two input data ina and inb can be, for example, neuron data. Specifically, the first-stage pipeline multiplier in the three-stage pipeline operation circuit can be used for calculation, so that the first-stage pipeline operation result product = ina * inb (regarded as a microinstruction in the operation instruction, which corresponds to the multiplication operation) can be obtained. Then, the addition tree in the second-stage pipeline operation circuit can be used to perform an addition operation on the first-stage pipeline operation result "product" to obtain the second-stage pipeline operation result sum. Finally, the nonlinear operator of the third-stage pipeline operation circuit is used to perform an activation operation on "sum" to obtain the final convolution operation result.

In some application scenarios, a bypass operation can be performed on one or more stages of pipeline operation circuits that will not be used in the operation, that is, one or more stages of the multi-stage pipeline operation circuit can be selectively used according to the needs of the operation, without requiring the operation to pass through all the multi-stage pipeline operations. Taking the operation of calculating the Euclidean distance as an example, assuming that its calculation instruction is expressed as dis=sum((ina-inb)^2), only a few stages of pipeline operation circuits composed of adders, multipliers, adder trees and accumulators can be used to perform the operation to obtain the final operation result, and the unused pipeline operation circuits can be bypassed before or during the pipeline operation.

In the aforementioned pipeline operation, each group of pipeline operation circuits can independently perform the pipeline operation. However, each group of pipeline operation circuits in multiple groups can also perform the pipeline operation in a collaborative manner. For example, the output of the first and second stages of the first group of pipeline operation circuits after performing serial pipeline operation can be used as the input of the third stage of the pipeline of another group of pipeline operation circuits. For another example, the first and second stages of the first group of pipeline operation circuits perform parallel pipeline operation, and respectively output the results of their respective pipeline operations as the input of the first and/or second stage pipeline operation of another group of pipeline operation circuits.

4a, 4b and 4c are schematic diagrams showing matrix conversion performed by the data conversion circuit according to the embodiment of the present disclosure. In order to better understand the conversion operation performed by the data conversion circuit 3021 in the main processing circuit, the following will be further described by taking the transposition operation and horizontal mirror operation performed by the original matrix (which can be regarded as a 2-dimensional tensor under the present disclosure) as an example.

As shown in FIG4a, the original matrix is a matrix of (M+1) rows × (N+1) columns. According to the requirements of the application scenario, the data conversion circuit can perform a transposition operation on the original matrix shown in FIG4a to obtain a matrix as shown in FIG4b. Specifically, the data conversion circuit can exchange the row number and column number of the elements in the original matrix to form a transposed matrix. Specifically, the element "10" whose coordinate is the 1st row and 0th column in the original matrix shown in FIG4a has a coordinate of the 0th row and 1st column in the transposed matrix shown in FIG4b. By analogy, the element "M0" whose coordinate is the M+1th row and 0th column in the original matrix shown in FIG4a has a coordinate of the 0th row and the M+1th column in the transposed matrix shown in FIG4b.

As shown in FIG4c, the data conversion circuit can perform a horizontal mirror operation on the original matrix shown in FIG4a to form a horizontal mirror matrix. Specifically, the data conversion circuit can convert the arrangement order from the first row elements to the last row elements in the original matrix into the arrangement order from the last row elements to the first row elements through the horizontal mirror operation, while the column number of the elements in the original matrix remains unchanged. Specifically, the coordinates in the original matrix shown in FIG4a are the element "00" in the 0th row and the 0th column and the element "10" in the 1st row and the 0th column, respectively, and the coordinates in the horizontal mirror matrix shown in FIG4c are the M+1th row and the 0th column and the Mth row and the 0th column, respectively. By analogy, the coordinates in the original matrix shown in FIG4a are the element "M0" in the M+1th row and the 0th column, and the coordinates in the horizontal mirror matrix shown in FIG4c are the 0th row and the 0th column.

Fig. 5 is a block diagram showing a slave processing circuit 500 of a computing device according to an embodiment of the present disclosure. It is understood that the structure shown in the figure is merely exemplary and not restrictive, and those skilled in the art may also conceive of adding more operators to form more stages of pipeline operation circuits based on the teachings of the present disclosure.

As shown in Fig. 5, the slave processing circuit 500 includes a four-stage pipeline operation circuit consisting of a multiplier 502, a comparator 504, a selector 506, an accumulator 508 and a converter 510. In an application scenario, the slave processing circuit as a whole can perform vector (including, for example, matrix) operations.

When performing vector operations, the vector data (which can be regarded as a 1-dimensional tensor under the present disclosure) including weight data and neuron data is controlled by the processing circuit 500 according to the received microinstructions (such as the control signal shown in the figure) to be input into the multiplier. After performing the multiplication operation, the multiplier inputs the result to the selector 506. Here, the selector 506 selects to pass the result of the multiplier rather than the result from the comparator to the accumulator 508 to perform the accumulation operation in the vector operation. Then, the accumulator passes the accumulated result to the converter 510 to perform the data conversion operation described above. Finally, the converter outputs the cumulative sum (i.e., "ACC_SUM" shown in the figure) as the final result.

In addition to performing the matrix multiplication and addition ("MAC") operation between the above-mentioned neuron data and weight data, the four-stage pipeline operation circuit shown in Figure 5 can also be used to perform histogram operations, depthwise layer multiplication and addition operations, integration and winograd multiplication and addition operations in neural network operations. When performing histogram operations, in the first stage of operation, the input data is input to the comparator from the processing circuit according to the microinstruction. Accordingly, here the selector 506 selects to pass the result of the comparator rather than the result of the multiplier to the accumulator to perform subsequent operations.

Through the above description, those skilled in the art can understand that in terms of hardware arrangement, the slave processing circuit of the present disclosure may include multiple operation circuits for performing slave operation, and the multiple operation circuits are connected and configured to perform multi-stage pipeline operation. In one or more embodiments, the aforementioned operation circuit may include but is not limited to one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit to at least perform vector operations, such as multi-dimensional convolution operations in a neural network.

In one operation scenario, the slave processing circuit disclosed in the present invention can operate on the data that has been pre-processed by the main processing circuit according to the slave instruction (implemented as, for example, one or more microinstructions or control signals) to obtain the expected operation result. In another operation scenario, the slave processing circuit can send the intermediate result obtained after its operation (for example, via an interconnect interface) to the data processing unit in the main processing circuit, so that the data conversion circuit in the data processing unit can perform data type conversion on the intermediate result or the data splicing circuit in the data processing unit can perform data splitting and splicing operations on the intermediate result, so as to obtain the final operation result. The operation of the master processing circuit and the slave processing circuit disclosed in the present invention will be described below in conjunction with several exemplary instructions.

Taking the calculation instruction "COSHLC" including the pre-processing operation as an example, the operation performed by it (including the pre-processing operation performed by the master processing circuit and the slave operation performed by the slave processing circuit) can be expressed as:

COSHLC＝FPTOFIX+SHUFFLE+LT3DCONV，

Wherein FPTOFIX represents the data type conversion operation performed by the data conversion circuit in the main processing circuit, that is, converting the input data from floating-point numbers to fixed-point numbers, SHUFFLE represents the data splicing operation performed by the data splicing circuit, and LT3DCONV represents the 3DCONV operation performed by the slave processing circuit (represented by "LT"), that is, the convolution operation of 3D data. It can be understood that when only the convolution operation of 3D data is performed, FPTOFIX and SHUFFLE as part of the main operation can be set as optional operations.

Taking the calculation instruction LCSU including the post-processing operation as an example, the operation performed by it (including the slave operation performed by the slave processing circuit and the post-processing operation performed by the master processing circuit) can be expressed as:

LCSU＝LT3DCONV+SUB，

After the slave processing circuit performs the LT3DCONV operation to obtain the 3D convolution result, the subtractor in the master processing circuit may perform a subtraction operation SUB on the 3D convolution result. Thus, in each instruction execution cycle, a 2-element operand (i.e., the convolution result and the subtrahend) may be input, and a 1-element operand (i.e., the final result obtained after executing the LCSU instruction) may be output.

Taking the calculation instruction SHLCAD including the pre-processing operation, the slave operation and the post-processing operation as an example, the operation performed by it (including the pre-processing operation performed by the main processing circuit, the slave operation performed by the slave processing circuit and the post-processing operation performed by the main processing circuit) can be expressed as:

SHLCAD＝SHUFFLE+LT3DCONV+ADD

In the pre-processing operation, the data splicing circuit performs a data splicing operation represented by SHUFFLE. Then, the slave processing circuit performs an LT3DCONV operation on the spliced data to obtain a 3D convolution result. Finally, the adder in the master processing circuit performs an addition operation ADD on the 3D convolution result to obtain the final calculation result.

From the above examples, it can be understood by those skilled in the art that after parsing the calculation instructions, the operation instructions obtained by the present disclosure include one of the following combinations according to the specific operation operations: pre-processing instructions and sub-processing instructions; sub-processing instructions and post-processing instructions; and pre-processing instructions, sub-processing instructions and post-processing instructions. Based on this, in some embodiments, the pre-processing instructions may include data conversion instructions and/or data splicing instructions. In other embodiments, the post-processing instructions include one or more of the following: random number processing instructions, addition instructions, subtraction instructions, table lookup instructions, parameter configuration instructions, multiplication instructions, pooling instructions, activation instructions, comparison instructions, absolute value instructions, logical operation instructions, position index instructions or filtering instructions. In other embodiments, the sub-processing instructions may include various types of operation instructions, including but not limited to instructions similar to those in the post-processing instructions and instructions for complex data processing, such as vector operation instructions or tensor operation instructions.

Based on the above description in combination with Figures 1 (including Figures 1a and 1b) to 5, those skilled in the art can understand that the present disclosure also discloses a method of using a computing device to perform a computing operation, wherein the computing device includes a main processing circuit and at least one slave processing circuit (i.e., the computing device discussed in combination with Figures 1 to 5 above), and the method includes configuring the main processing circuit to perform a main operation in response to a main instruction, and configuring the slave processing circuit to perform a slave operation in response to a slave instruction. In one embodiment, the aforementioned main operation includes a pre-processing operation and/or a post-processing operation for the slave operation, and the main instruction and the slave instruction are parsed according to the computing instruction received by the computing device. In another embodiment, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand.

Based on the above-mentioned descriptor settings, the method may also include configuring the master processing circuit and/or slave processing circuit to perform respective corresponding master operations and/or slave processing operations according to the storage address. As previously mentioned, through the descriptor settings disclosed in the present invention, the efficiency of tensor operations and the rate of data access can be improved, and the overhead of tensor operations can be further reduced. In addition, although the other steps of the method are not described here for the purpose of simplicity, those skilled in the art can understand that the method disclosed in the present invention can perform the various operations described in the foregoing text in conjunction with Figures 1-5 based on the contents disclosed in the present invention.

FIG6 is a structural diagram showing a combined processing device 600 according to an embodiment of the present disclosure. As shown in FIG6, the combined processing device 600 includes a computing processing device 602, an interface device 604, other processing devices 606, and a storage device 608. According to different application scenarios, the computing processing device may include one or more computing devices 610, which may be configured to perform the operations described herein in conjunction with FIG1-FIG5.

In different embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, with respect to the computing and processing device of the present disclosure, it may be regarded as having a single-core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and/or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

In one or more embodiments, the other processing device can serve as an interface between the computing device disclosed herein (which can be embodied as an artificial intelligence such as a computing device related to neural network computing) and external data and control, and perform basic controls including but not limited to data handling, starting and/or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the computing device to jointly complete computing tasks.

In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it into a storage device (or memory) on the computing and processing device chip. Further, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them into a control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and/or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

In some embodiments, the present disclosure further discloses a chip (e.g., chip 702 shown in FIG. 7 ). In one implementation, the chip is a system-on-chip (SoC) and is integrated with one or more combined processing devices as shown in FIG. 6 . The chip can be connected to other related components through an external interface device (e.g., external interface device 706 shown in FIG. 7 ). The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interfaces) may be integrated on the chip. In some embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure further discloses a board card, which includes the above-mentioned chip packaging structure. The board card will be described in detail below in conjunction with FIG. 7 .

FIG. 7 is a schematic diagram showing the structure of a board 700 according to an embodiment of the present disclosure. As shown in FIG. 7 , the board includes a storage device 704 for storing data, which includes one or more storage units 710. The storage device can be connected and data can be transmitted with the control device 708 and the chip 702 described above by means of, for example, a bus. Further, the board also includes an external interface device 706, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 712 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) for regulating the working state of the chip.

According to the above description in combination with Figures 6 and 7, those skilled in the art can understand that the present disclosure also discloses an electronic device or device, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and/or one or more of the above-mentioned combined processing devices.

According to different application scenarios, the electronic equipment or device disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, transportation, household appliances, and/or medical equipment. The transportation includes airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and/or electrocardiographs. The electronic equipment or device disclosed herein may also be applied to the Internet, IoT, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical fields. Further, the electronic equipment or device disclosed herein may also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and/or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and/or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or edge device are compatible with each other, so that according to the hardware information of the terminal device and/or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein are not necessarily necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and/or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

The foregoing content can be better understood in accordance with the following terms:

Clause 1. A computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

The main processing circuit is configured to perform main computing operations in response to main instructions,

The slave processing circuit is configured to perform slave computing operations in response to slave instructions,

The master operation includes a pre-processing operation and/or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The master processing circuit and/or the slave processing circuit are configured to execute respective corresponding master computing operations and/or slave processing operations according to the storage address.

Clause 2. A computing device according to clause 1, wherein the computing instruction includes an identification of a descriptor and/or the content of the descriptor, and the content of the descriptor includes at least one shape parameter representing the shape of tensor data.

Clause 3. A computing device according to clause 2, wherein the contents of the descriptor also include at least one address parameter representing an address of tensor data.

Clause 4. A computing device according to clause 3, wherein the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data.

Clause 5. The computing device of clause 4, wherein the shape parameter of the tensor data comprises at least one of the following:

The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

Clause 6. The computing device of clause 1, wherein the main processing circuit is configured to:

Acquire the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction; and

The slave instruction is sent to the slave processing circuit.

Clause 7. The computing device of clause 1, further comprising a control circuit configured to:

Acquire the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction; and

The master instructions are sent to the master processing circuit and the slave instructions are sent to the slave processing circuit.

Clause 8. A computing device according to Clause 1, wherein the main instruction includes an identification bit for identifying the pre-processing operation and/or the post-processing operation.

Clause 9. A computing device according to clause 1, wherein the computing instruction includes a preset bit for distinguishing the pre-processing operation and the post-processing operation in the main instruction.

Item 10. A computing device according to Item 1, wherein the main processing circuit includes a data processing unit for performing the main computing operation, and the data processing unit includes a data conversion circuit for performing a data conversion operation and/or a data splicing circuit for performing a data splicing operation.

Item 11. A computing device according to Item 10, wherein the data conversion circuit includes one or more converters for realizing conversion of computing data between a plurality of different data types.

Clause 12. A computing device according to clause 10, wherein the data splicing circuit is configured to split the computing data into predetermined bit lengths and to splice the multiple data blocks obtained after the splitting in a predetermined order.

Item 13. A computing device according to Item 1, wherein the main processing circuit includes one or more groups of pipeline operation circuits, each group of pipeline operation circuits forms an operation pipeline and includes one or more operators, wherein when each group of pipeline operation circuits includes multiple operators, the multiple operators are connected and configured to selectively participate in performing the main operation according to the main instruction.

Clause 14. A computing device according to clause 13, wherein the main processing circuit comprises at least two operation pipelines, and each operation pipeline comprises one or more of the following operators or circuits:

Random number processing circuit, addition and subtraction circuit, subtraction circuit, table lookup circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.

Item 15. A computing device according to Item 1, wherein the slave processing circuit includes a plurality of operation circuits for performing the slave operation, and the plurality of operation circuits are connected and configured to perform multi-stage pipeline operation, wherein the operation circuit includes one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit to perform at least vector operation.

Clause 16. The computing device according to clause 15, wherein the slave instruction comprises a convolution instruction for performing a convolution operation on the calculation data subjected to the pre-processing operation, and the slave processing circuit is configured to:

A convolution operation is performed on the calculated data after the pre-processing operation according to the convolution instruction.

Clause 17. An integrated circuit chip comprising a computing device according to any one of clauses 1-16.

Clause 18. A board comprising the integrated circuit chip according to clause 17.

Clause 19. An electronic device comprising the integrated circuit chip according to clause 17.

Clause 20. A method of performing a computing operation using a computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising:

configuring the main processing circuit to perform main computing operations in response to main instructions,

configuring the slave processing circuit to perform slave computing operations in response to slave instructions,

The master operation includes a pre-processing operation and/or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand,

The method further comprises configuring the master processing circuit and/or the slave processing circuit to execute respective corresponding master computing operations and/or slave processing operations according to the storage address.

Clause 21. A method according to clause 20, wherein the computation instruction includes an identification of a descriptor and/or content of the descriptor, wherein the content of the descriptor includes at least one shape parameter representing a shape of tensor data.

Clause 22. A method according to clause 21, wherein the contents of the descriptor also include at least one address parameter representing an address of tensor data.

Clause 23. A method according to clause 22, wherein the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data.

Clause 24. The method of clause 23, wherein the shape parameter of the tensor data comprises at least one of the following:

The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

Clause 25. The method of clause 20, wherein the main processing circuit is configured to:

Acquire the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction; and

The slave instruction is sent to the slave processing circuit.

Clause 26. The method of clause 20, wherein the computing device includes a control circuit, the method further comprising configuring the control circuit to:

Acquire the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction; and

The master instructions are sent to the master processing circuit and the slave instructions are sent to the slave processing circuit.

Clause 27. A method according to clause 20, wherein the main instruction includes an identification bit for identifying the pre-processing operation and/or the post-processing operation.

Clause 28. The method of clause 20, wherein the computation instruction includes a preset bit for distinguishing the pre-processing operation from the post-processing operation in the host instruction.

Item 29. A method according to Item 20, wherein the main processing circuit includes a data processing unit, and the data processing unit includes a data conversion circuit and/or a data splicing circuit, and the method includes configuring the data processing unit to perform the main operation, configuring the data conversion circuit to perform a data conversion operation, and configuring the data splicing circuit to perform a data splicing operation.

Clause 30. A method according to clause 29, wherein the data conversion circuit comprises one or more converters, and the method comprises configuring the one or more converters to implement conversion of computational data between a plurality of different data types.

Clause 31. A method according to clause 29, wherein the data splicing circuit is configured to split the calculation data into predetermined bit lengths and to splice the multiple data blocks obtained after the splitting in a predetermined order.

Item 32. A method according to Item 20, wherein the main processing circuit includes one or more groups of pipeline operation circuits, each group of pipeline operation circuits forms an operation pipeline and includes one or more operators, wherein when each group of pipeline operation circuits includes multiple operators, the method includes connecting the multiple operators and configuring them to selectively participate in performing the main operation according to the main instruction.

Clause 33. A method according to clause 32, wherein the main processing circuit comprises at least two operation pipelines, and each operation pipeline comprises one or more of the following operators or circuits:

Random number processing circuit, addition and subtraction circuit, subtraction circuit, table lookup circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.

Item 34. A method according to Item 20, wherein the slave processing circuit includes multiple operation circuits, the method includes configuring the multiple operation circuits to perform the slave operation, and the method also includes connecting and configuring the multiple operation circuits to perform multi-stage pipeline operation, wherein the operation circuit includes one or more of a multiplication circuit, a comparison circuit, an accumulation circuit and a rotation circuit to perform at least vector operation.

Clause 35. A method according to clause 34, wherein the slave instruction comprises a convolution instruction for performing a convolution operation on the computational data subjected to the pre-processing operation, the method comprising configuring the slave processing circuit to:

A convolution operation is performed on the calculated data after the pre-processing operation according to the convolution instruction.

Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims (32)

1. An artificial intelligence processor for executing a computing instruction, the computing instruction comprising a descriptor, the artificial intelligence processor comprising: Storage circuit; A main processing circuit accesses the tensor based on the storage address in the storage circuit obtained from the descriptor and the shape of the tensor indicating N dimensions, and performs pre-processing operations; A plurality of slave processing circuits are configured to perform N-dimensional matrix operations in parallel based on the tensors after the pre-processing operations. 2. The artificial intelligence processor according to claim 1, wherein the main processing circuit is used to perform the data splicing operation in the pre-processing operation. 3. The artificial intelligence processor according to claim 1, wherein the main processing circuit is used to perform a data conversion operation in the pre-processing operation. 4. The artificial intelligence processor according to claim 1, wherein the tensors are stored in the same area of the internal memory. 5. The artificial intelligence processor of claim 1, wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operation. 6. The artificial intelligence processor according to claim 5, wherein the main processing circuit matches the pre-processing operation and the post-processing operation through an identification bit of the computing instruction. 7. The artificial intelligence processor of claim 5, wherein the computing instruction comprises one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction. 8. The artificial intelligence processor of claim 1, wherein the slave processing circuit performs data type conversion. 9. The artificial intelligence processor of claim 1, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations. 10. The artificial intelligence processor according to claim 1, wherein The storage address includes a reference address of the data reference point of the descriptor in the data storage space. The shape of an N-dimensional tensor includes at least the size of a storage area of the tensor in at least one direction of the N dimensions. 11. An artificial intelligence processor for executing a computing instruction, the computing instruction comprising a descriptor, the artificial intelligence processor comprising: A main processing circuit configured to perform a main operation, the main operation including accessing the tensor using a storage address obtained from the descriptor and a shape indicating an N-dimensional tensor, and a pre-processing operation; The main processing circuit is used to perform the splicing operation in the pre-processing operation. 12. The artificial intelligence processor according to claim 11, wherein the main processing circuit is used to perform a data conversion operation in the pre-processing operation. 13. The artificial intelligence processor according to claim 11, further comprising: A plurality of slave processing circuits are configured to perform N-dimensional matrix operations in parallel based on the tensors after the pre-processing operations. 14. The artificial intelligence processor according to claim 13, wherein the tensors are stored in the same area of the internal memory. 15. The artificial intelligence processor of claim 13, wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operation. 16. The artificial intelligence processor according to claim 15, wherein the main processing circuit matches the pre-processing operation and the post-processing operation through an identification bit of the computing instruction. 17. The artificial intelligence processor of claim 15, wherein the computing instruction comprises one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction. 18. The artificial intelligence processor of claim 13, wherein the slave processing circuit performs data type conversion. 19. The artificial intelligence processor of claim 13, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations. 20. The artificial intelligence processor of claim 11, wherein The storage address includes a reference address of the data reference point of the descriptor in the data storage space. The shape of an N-dimensional tensor includes at least the size of a storage area of the tensor in at least one direction of the N dimensions. 21. An artificial intelligence processor for executing a computing instruction, the computing instruction comprising a descriptor, the artificial intelligence processor comprising: A main processing circuit configured to perform a main operation, the main operation including accessing the tensor using a storage address obtained from the descriptor and a shape indicating an N-dimensional tensor, and a pre-processing operation; The main processing circuit is used to perform the data conversion operation in the pre-processing operation. 22. The artificial intelligence processor according to claim 21, further comprising: A plurality of slave processing circuits are configured to perform N-dimensional matrix operations in parallel based on the tensors after the pre-processing operations. 23. The artificial intelligence processor of claim 22, wherein the tensors are stored in the same area of the internal memory. 24. The artificial intelligence processor of claim 22, wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operations. 25. The artificial intelligence processor according to claim 24, wherein the main processing circuit matches the pre-processing operation and the post-processing operation through an identification bit of the computing instruction. 26. The artificial intelligence processor of claim 24, wherein the computational instructions comprise one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction. 27. The artificial intelligence processor of claim 22, wherein the slave processing circuit performs data type conversion. 28. The artificial intelligence processor of claim 22, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations. 29. The artificial intelligence processor of claim 21, wherein The storage address includes a reference address of the data reference point of the descriptor in the data storage space. The shape of an N-dimensional tensor includes at least the size of a storage area of the tensor in at least one direction of the N dimensions. 30. An integrated circuit chip comprising an artificial intelligence processor according to any one of claims 1-29. 31. A board comprising the integrated circuit chip according to claim 30. 32. An electronic device comprising the integrated circuit chip according to claim 30.