CN117828253B - Multi-bit matrix vector multiplication calculation unit, array and working method thereof - Google Patents

Abstract

The present invention discloses a multi-bit matrix vector multiplication calculation unit, array and working method thereof, wherein the unit comprises: an analog voltage signal input module, a flash memory storage unit, a calculation capacitor module, a proportional time signal generation module and a readout circuit module; the array comprises a plurality of multi-bit matrix vector multiplication calculation units arranged in parallel. The method comprises: performing a zeroing process on the calculation capacitor unit; obtaining a voltage signal of a proportional time length; charging the calculation capacitor module after clearing the charge to obtain a digital weight; performing a multiplication calculation process on the analog input voltage signal and the digital weight; and outputting the calculation result in the form of a digital signal. The present invention can improve the calculation rate of a flash memory device and reduce the calculation energy consumption of the flash memory device. As a multi-bit matrix vector multiplication calculation unit, array and working method thereof, the present invention can be widely used in the field of flash memory chip technology.

Description

A multi-bit matrix-vector multiplication calculation unit, array and working method thereof

Technical Field

The present invention relates to the technical field of flash memory chips, and in particular to a multi-bit matrix-vector multiplication calculation unit, an array and a working method thereof.

Background Art

With the availability of big data and the improvement of processor performance, various high-performance neural network algorithms have been developed rapidly, especially various neural network algorithms based on dot product calculations, which are used to achieve functions such as image classification recognition and machine translation, and are widely deployed in various applications such as self-driving cars, virtual reality, social media, and medical devices. With the increase in the complexity of such networks and the increase in computing work, the development of an efficient neural accelerator is becoming an urgent and critical need in many applications. From a computing perspective, neural network processing can be divided into two main stages, namely training and inference. The two stages have different computing requirements. Training, which is usually performed on powerful servers, requires a lot of computing power and memory to store huge training data sets, calculate outputs, and run training algorithms to calculate weight updates. On the other hand, end-user inference only requires enough memory and processing power to input input data into a pre-trained network and calculate the results within a specific application. In a wide range of applications, such as the rapidly growing "Internet of Things", people want to perform inference on the terminal rather than in a cloud server. Inference on the terminal device reduces processing latency and communication costs, improves security, and eliminates the reliance on reliable network access. On the other hand, most end-user devices have strict power budget constraints, but the reasoning of neural network algorithms currently running on terminal devices still has high power consumption and heat dissipation problems caused by the small memory capacity of the terminal processor and the calculation and storage functions being performed by the central processing unit and memory respectively. The application of neural networks requires a large number of memory access operations during the calculation process, and memory access operations occupy a large amount of power consumption and latency in the calculation process, which limits the performance improvement of the processor.

Summary of the invention

In order to solve the above technical problems, the purpose of the present invention is to provide a multi-bit matrix-vector multiplication calculation unit, array and working method thereof, which can improve the calculation rate of flash memory devices and reduce the calculation energy consumption of flash memory devices.

The first technical solution adopted by the present invention is: a multi-bit matrix vector multiplication calculation unit, comprising an analog voltage signal input module, a flash memory storage unit, a calculation capacitance module, a proportional time signal generation module and a readout circuit module, wherein the output end of the analog voltage signal input module is connected to the drain end of the flash memory storage unit, the output end of the proportional time signal generation module is connected to the gate end of the flash memory storage unit, the source end of the flash memory storage unit is connected to the input end of the calculation capacitance module, and the output end of the calculation capacitance module is connected to the input end of the readout circuit module, wherein:

The analog voltage signal input module is used to generate an analog input voltage signal and load it to the drain end of the flash memory storage unit;

The flash memory storage unit is used to store digital weights;

The capacitance calculation module is used to perform multiplication calculation processing on the analog input voltage signal and the digital weight, and output the calculation result in the form of a voltage signal;

The proportional time signal generating module is used to generate a voltage signal of proportional time length and control the conduction time of the flash memory storage unit;

The readout circuit module is used to convert the calculation result in the form of a voltage signal and output the calculation result in the form of a digital signal.

Furthermore, the analog voltage signal input module is specifically implemented in any one of the following two construction modes:

The first construction method: construction through digital-to-analog converter ADC;

The second construction method is to construct by electrically connecting the sensor and the amplifier.

Furthermore, the flash memory storage unit includes at least one flash memory device, and the flash memory device is used to store 1-bit data.

Further, the capacitance calculation module includes a plurality of capacitance calculation units, a connection switch and a grounding switch, the capacitance calculation unit is electrically connected to the connection switch, and the capacitance calculation unit is electrically connected to the grounding switch, wherein:

The capacitance calculation unit is used to perform multiplication calculation processing on the analog input voltage signal and the digital weight;

The connecting switch is used to connect the calculating capacitance unit;

The grounding switch is used to clear the charge of the calculation capacitor unit.

Further, the proportional time signal generating module includes a clock generator, a first digital delay unit, a second digital delay unit, a first input XOR gate, a second input XOR gate and a third input XOR gate, the first output end of the clock generator is respectively connected to the first input end of the first input XOR gate, the first input end of the second input XOR gate and the first input end of the third input XOR gate, the second output end of the clock generator is connected to the input end of the first digital delay unit, the output end of the first digital delay unit is connected to the second input end of the first input XOR gate, the output end of the second digital delay unit is connected to the second input end of the second input XOR gate, and the input end of the second digital delay unit is connected to the second input end of the third input XOR gate, wherein:

The clock generator is used to generate a computing clock signal;

The first digital delay unit and the second digital delay unit are used to delay the calculation clock signal to obtain a delayed calculation clock signal;

The first input XOR gate, the second input XOR gate and the third input XOR gate are used to perform XOR calculation on the calculation clock signal and the delayed calculation clock signal to obtain voltage signals of equal proportional time lengths.

Furthermore, the readout circuit module is an analog-to-digital converter.

The second technical solution adopted by the present invention is: a multi-bit matrix-vector multiplication calculation array, including a plurality of multi-bit matrix-vector multiplication calculation units arranged in parallel.

The third technical solution adopted by the present invention is: a working method of a multi-bit matrix-vector multiplication calculation array, including an independent calculation capacitor working mode and a shared calculation capacitor working mode.

Furthermore, the independent capacitance calculation working mode specifically includes the following steps:

The connecting switch and the grounding switch are closed, and the capacitance calculation unit is cleared to obtain a capacitance calculation module after charge is cleared;

The connecting switch is disconnected from the grounding switch, and the analog input voltage signal is obtained based on the analog voltage signal input module, and the proportional time signal generating module obtains the voltage signal of the proportional time length;

The analog input voltage signal is loaded to the drain end of the flash memory unit, the voltage signal of the proportional time length is loaded to the source end of the flash memory unit, the calculation capacitance module after the charge is cleared is charged, and a digital weight is obtained;

The connection switch is closed, the grounding switch remains open, and the analog input voltage signal and the digital weight are multiplied and calculated based on the capacitance calculation module, and a calculation result in the form of a voltage signal is output;

The calculation result in the form of a voltage signal is converted and processed by the readout circuit module, and the calculation result in the form of a digital signal is output.

Furthermore, the shared calculation capacitor working mode is to construct at least one page module, the page module includes at least one flash memory storage unit and at least one calculation capacitor module, the flash memory storage unit and the calculation capacitor module are connected one-to-one, if one of the page modules is in working state, the connection switches of the other page modules are disconnected and the gate end of the flash memory storage unit is not loaded with the voltage signal of the equal proportional time length.

The beneficial effects of the computing unit, array and working method of the present invention are as follows: the present invention constructs a multi-bit matrix vector multiplication computing unit by combining an analog voltage signal input module, a flash memory storage unit, a computing capacitance module, a proportional time signal generating module and a readout circuit module, performs charge calculation based on the computing capacitance module, and realizes multiplication calculation in stages through the computing capacitance module, thereby further reducing the working energy consumption of the multi-bit matrix vector multiplication computing unit, improving the reliability of the calculation result based on the charge calculation, and enabling the in-memory computing unit to have large-scale parallelism based on the storage digital weight of the flash memory storage unit, thereby improving the computing energy efficiency and speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a multi-bit matrix-vector multiplication calculation unit of the present invention;

FIG2 is a block diagram of a working method of a multi-bit matrix-vector multiplication calculation array according to the present invention;

3 is a schematic diagram of the structure of a proportional time signal generating module according to a specific embodiment of the present invention;

FIG4 is a schematic diagram of a complete single multiplication calculation structure of a specific embodiment of the present invention;

5 is a schematic diagram of the structure of an array calculation mode for independent capacitance calculation according to a specific embodiment of the present invention;

6 is a schematic diagram of the structure of a calculation mode for shared capacitance calculation by an array according to a specific embodiment of the present invention;

FIG. 7 is a schematic diagram of a conventional NAND flash memory storage architecture provided by a specific embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

1, the present invention provides a multi-bit matrix vector multiplication calculation unit, including an analog voltage signal input module, a flash memory storage unit, a calculation capacitance module, a proportional time signal generation module and a readout circuit module, the output end of the analog voltage signal input module is connected to the drain end of the flash memory storage unit, the output end of the proportional time signal generation module is connected to the gate end of the flash memory storage unit, the source end of the flash memory storage unit is connected to the input end of the calculation capacitance module, and the output end of the calculation capacitance module is connected to the input end of the readout circuit module, wherein:

The analog voltage signal input module is used to generate an analog input voltage signal and load it to the drain end of the flash memory storage unit;

Specifically, the analog voltage signal input module includes two construction methods. The first construction method is to construct it through a digital-to-analog converter ADC, and the second construction method is to construct it through an electrical connection between a sensor and an amplifier.

In this embodiment, there are two schemes for the analog voltage signal input module. The first is a sensor plus amplifier scheme, which is used to directly load the analog signal at the sensor end with the drain of the FLASH device as an analog voltage. The amplifier DAC scheme is used to convert any bit of the digital signal processed by the sensor itself into an analog voltage and load it with the drain of the FLASH device as an analog voltage for multiplication calculation.

The flash memory unit is used to store the digital weights;

Specifically, the flash memory storage unit includes at least one flash memory device, and the flash memory device is used to store 1-bit data.

In this embodiment, the flash memory storage unit is used to complete the multiplication of the analog input and the digital weight, the calculated capacitor is a capacitor of equal size, and the multiplication result is represented by the voltage after the charge is evenly divided.

The flash memory storage unit may include different numbers of flash memory devices according to the bit width of the digital value. Each flash memory device is configured to store 1 bit of data. The type of the flash memory unit may be either a NOR type flash memory or a NAND type flash memory. Specifically, as shown in FIG. 7 , the storage unit may be any storage device that can implement data 0/1 storage in a conductive and blocked form.

Furthermore, an N-bit flash memory unit can be composed of N flash memory devices. In the flash memory unit, the flash memory device with the highest position weight, that is, the flash memory device with a position weight of 2N, has a drain connected to an input analog voltage signal, a gate connected to a voltage signal of 2N times the unit time length, and a source connected to an upper plate of a corresponding calculated capacitor. The flash memory device with a position weight of 2N-1 has a drain connected to the same analog voltage signal as other flash memory devices, a gate connected to a voltage signal of 2(N-1) times the unit time length, and a source connected to an upper plate of a corresponding calculated capacitor. The N flash memory devices are the same as the first two flash memory devices, and have the same connection relationship with the input voltage proportional time length signal and the calculated capacitor.

The calculation capacitance module is used to multiply the analog input voltage signal with the digital weight and output the calculation result in the form of a voltage signal;

Specifically, the calculation capacitor module includes a plurality of calculation capacitor units, a connecting switch and a grounding switch, wherein the calculation capacitor unit is electrically connected to the connecting switch, and the calculation capacitor unit is electrically connected to the grounding switch, wherein the calculation capacitor unit is used to multiply the analog input voltage signal with the digital weight; the connecting switch is used to connect the calculation capacitor unit; and the grounding switch is used to clear the charge of the calculation capacitor unit.

In this embodiment, the calculation capacitance module includes a calculation capacitance, a connection switch and a grounding switch. The calculation capacitance is used to complete the multiplication of the analog input and the digital weight. The calculation capacitance is an equal-sized capacitance. The multiplication result is represented by the voltage after the charge is evenly divided. The connection switch is used to cooperate with the grounding switch to complete the charge zeroing step before the calculation, and to connect the equal-sized calculation capacitances in the calculation stage. The grounding switch is used to cooperate with the connection switch in the charge zeroing stage to clear the charge on the capacitor to improve the calculation accuracy and reduce the error.

The number of calculation capacitors is consistent with the bit width of the multiplier 2, the upper plates of the plurality of calculation capacitors are connected to the input end of the transmission gate, and the output ends of the plurality of connection switches are connected to the readout circuit module.

Further, as shown in FIG4 , the capacitance calculation module includes: a capacitance calculation, a connection switch and a grounding switch, the number of capacitance calculations is consistent with the bit width of the multiplier 2, the upper plates of the plurality of capacitance calculations are connected to the input end of the transmission gate and to the source end of the flash memory device, the output ends of the plurality of connection switches are connected to the readout circuit module, the multiplier 1, i.e., the external input analog voltage signal is loaded on the drain end of the flash memory device, if the corresponding flash memory device stores a value of 1, and the signal loaded on the gate of the flash memory device is within the high level of the proportional time signal, then the voltage at the drain end will charge the capacitance calculation within the proportional time signal. , the charge on the flash memory device increases and is proportional to the length of the time signal. If the value stored in the flash memory device is 0 or the proportional time signal of the gate is low, the charging path is blocked, the calculation capacitor is not charged, and the charge on the calculation capacitor is 0. After the charging stage is over, the proportional time signal is low, and the external input analog voltage signal can be maintained or disconnected. At this time, the ground switch is disconnected and the connecting switch is closed, and the charge on the calculation capacitor is migrated. All the calculation capacitors and wires are physically connected. The calculation capacitor is directly connected to the readout circuit to convert the analog voltage of the calculation result into a digital signal.

The proportional time signal generating module is used to generate a voltage signal of proportional time length and control the conduction time of the flash memory storage unit;

Specifically, the proportional time signal generating module includes a clock generator, a first digital delay unit, a second digital delay unit, a first input XOR gate, a second input XOR gate and a third input XOR gate, wherein the first output end of the clock generator is respectively connected to the first input end of the first input XOR gate, the first input end of the second input XOR gate and the first input end of the third input XOR gate, the second output end of the clock generator is connected to the input end of the first digital delay unit, the output end of the first digital delay unit is connected to the second input end of the first input XOR gate, the output end of the second digital delay unit is connected to the second input end of the second input XOR gate, and the input end of the second digital delay unit is connected to the second input end of the third input XOR gate, wherein the clock generator is used to generate a calculation clock signal; the first digital delay unit and the second digital delay unit are used to delay the calculation clock signal to obtain a delayed calculation clock signal; the first input XOR gate, the second input XOR gate and the third input XOR gate are used to perform XOR calculation on the calculation clock signal and the delayed calculation clock signal to obtain a voltage signal of proportional time length.

In this embodiment, the proportional time generation module is used to generate proportional times of 1:2:4, etc. The time signal is loaded on the gate terminal of the FLASH device to control the on-time of the corresponding FLASH device to realize the position weights 2 ⁰ , 2 ¹ , 2 ² to 2 ^N of the digital signal in the multiplication calculation process.

As shown in FIG3 , the proportional time signal generation module is composed of a clock generator, a standard digital delay unit and a two-input XOR gate, wherein the clock generator is used to generate the clock of the entire calculation module, the standard digital delay unit is used to delay the input time signal, and in order to achieve proportional time, a proportional number of delay units are inserted, and the input XOR gate is used to XOR the clock signal with the delayed signal, and finally generate a proportional high-level signal, i.e., a proportional time signal;

It should be noted that different manufacturers have digital delay units with different standards. The appropriate delay time length can be selected based on the capacitance of the calculated capacitance module, and then the appropriate digital delay unit can be selected. The digital delay unit suitable for specific implementation is the standard digital delay unit.

Furthermore, the signal output end of the clock generator is connected to the input ends of three two-input XOR gates, the signal of the clock generator is connected to the input end of the first standard digital delay unit, the output end of the first standard delay unit is connected to the input end of the first two-input XOR gate, and a voltage signal of unit time length is generated and loaded on the drain end of the flash memory device. After the signal of the clock generator passes through two digital standard delay units, the output end of the second standard delay unit is connected to one end of the second two-input XOR gate, and the XOR gate output generates a voltage signal with twice the unit time length. After the clock signal of the clock generator passes through four digital standard delay units, the input end is connected to one end of the third two-input XOR gate, and the XOR gate output generates a voltage signal with four times the unit time length, and so on, to generate a voltage signal with 2N times the unit time length. The multiple outputs of the proportional time signal generating module correspond to the gate of the flash memory device connected to the flash memory storage unit.

The readout circuit module is used to convert the calculation result in the form of a voltage signal and output the calculation result in the form of a digital signal.

Specifically, the readout circuit module is an analog-to-digital converter;

In this embodiment, the readout circuit is used to convert the calculated multiplication result voltage signal into a digital signal for subsequent processing.

A multi-bit matrix-vector multiplication calculation array comprises a plurality of multi-bit matrix-vector multiplication calculation units arranged in parallel.

Specifically, the array is composed of a plurality of multiplication units, and the size of the array, that is, the number of matrix multiplication units, can be set according to the size of the visual storage scale.

The multi-bit matrix-vector multiplication calculation array structure combines storage devices, calculation capacitors and proportional time to realize calculations in flash memory, which can to a certain extent solve the problems of low speed, power consumption and reliability of current-type in-memory calculations.

In summary, the embodiment of the present invention provides a multi-bit matrix vector multiplication calculation unit and array based on flash memory, and the multi-bit in-memory calculation unit performs matrix vector calculation between input data and storage data in the storage unit. In the unit, the digital-to-analog converter converts the multi-bit digital input signal into an analog voltage signal or the analog voltage output by the sensor is added to the drain end of the floating gate tube of the storage unit, and the flash memory storage unit stores a single bit of data. The retention time of the voltage applied to the gate end of the flash memory storage unit is in an equal proportional relationship. The equal proportional time is realized by the digital module, and then the multi-bit digital signal is stored by multiple flash memory storage units. According to the size of the analog voltage signal input to the drain end and the length of the retention time of the gate end voltage of the storage unit, the charge amount on the capacitors of equal size corresponding to the storage unit is controlled, and the voltage after the capacitors of equal size are evenly divided is the product of a single multiplication. Multiple multiplication units are connected, and the voltage after the shared even division is the matrix vector calculation result, and the calculation result is converted and read out by the readout circuit. Based on the original basic architecture of the flash memory, large-scale parallel matrix vector multiplication calculation can be realized, and the calculation array includes multiple matrix vector multiplication calculation units.

Referring to FIG. 2 , a working method of a multi-bit matrix-vector multiplication calculation array includes an independent calculation capacitor working mode and a shared calculation capacitor working mode, wherein:

As shown in FIG5 , the independent capacitor calculation working mode includes the following steps:

S1, closing the connection switch and the grounding switch, clearing the calculation capacitance unit, and obtaining a calculation capacitance module after clearing the charge;

S2, disconnecting the connection switch from the grounding switch, and obtaining an analog input voltage signal based on the analog voltage signal input module, and obtaining a voltage signal of an equal-proportional time length by the equal-proportional time signal generation module;

S3, loading the analog input voltage signal to the drain end of the flash memory unit, loading the voltage signal of equal proportional time length to the source end of the flash memory unit, charging the calculation capacitor module after the charge is cleared, and obtaining the digital weight;

S4, closing the connection switch, keeping the grounding switch open, performing multiplication calculation processing on the analog input voltage signal and the digital weight based on the calculation capacitance module, and outputting the calculation result in the form of a voltage signal;

S5. Convert the calculation result in the form of a voltage signal through the readout circuit module and output the calculation result in the form of a digital signal.

In the independent calculation capacitor mode, the analog input voltage signal is connected to the drain of the flash memory device, the source of the flash memory device is connected to the upper plate of the calculation capacitor, the upper plate is connected to a switch, the lower plate is grounded, and multiple switches are closed to complete the equal distribution of charges; in the independent calculation capacitor mode, the same as the aforementioned multiplication unit, each flash memory device is connected to a calculation capacitor, N×N calculation units are connected to realize an N×N matrix-vector multiplication, and an N×N matrix-vector multiplication unit includes N×N flash memory devices and corresponding calculation capacitors; after multiple multiplication units are connected, multiple calculation capacitors are evenly distributed to realize matrix-vector multiplication; the connection method of the readout circuit is that a matrix-vector multiplication module (i.e., N×N×(multiplier 2) bit-width flash memory devices) is connected to an analog-to-digital conversion module; multiple matrix-vector multiplication modules can work simultaneously; multiple matrix-vector multiplication modules share the analog voltage signal output by the sensor and amplifier or digital-to-analog converter.

As shown in FIG6 , for the shared calculation capacitor working mode, at least one page module is constructed, and the page module includes at least one flash memory storage unit and at least one calculation capacitor module. The flash memory storage unit and the calculation capacitor module are connected one-to-one. If one page module is in a working state, the connection switches of the other page modules are disconnected and the gate end of the flash memory storage unit is not loaded with a voltage signal of equal proportional time length.

Furthermore, in the charge clearing stage, the first group of pages is switched to the second group of pages, the averaging switch of the first group of pages is disconnected, and the averaging switch and grounding switch of the second group of pages are closed, and the large amount of charge remaining from the previous page calculation is grounded and cleared; in the charging stage of the calculation process, the switch connected to the three calculation capacitors and the ground is disconnected, the analog voltage signal is loaded on the drain end of the flash memory device, and the output voltage of the proportional time generation circuit is loaded on the source end of the flash memory device to charge the calculation capacitor; in the averaging stage of the calculation process: the switch connected to the three calculation capacitors is closed, and the grounding switch is disconnected, so that the charge on the calculation capacitor is evenly distributed within a large clock cycle and the calculation result voltage is obtained; in the result data reading stage, after the averaging voltage in the averaging stage of the calculation process is stable, the analog conversion module is enabled to convert the analog voltage signal into a digital signal output.

Specifically, the analog input voltage signal is connected to the drain of the flash memory device, the source of the flash memory device is connected to the upper plate of the calculation capacitor, the upper plate is connected to a switch, the lower plate is grounded, and multiple switches are closed to complete the equalization of the charge; similar to the aforementioned multiplication unit, each flash memory device is connected to a calculation capacitor, and N×N calculation units are connected to realize an N×N matrix-vector multiplication. An N×N matrix-vector multiplication unit includes N×N flash memory devices and corresponding calculation capacitors; in the shared calculation capacitor mode, according to the storage architecture concept of the flash memory, the flash memory devices on a page are connected to the calculation capacitors one by one, but multiple pages share a group of calculation capacitors. When performing matrix-vector multiplication calculations, a very multiplexed method is adopted. When a page is working, the connection switches of the other pages are disconnected and the gate end of the flash memory device is not loaded with voltage. Only the page performing the calculation is connected to the upper plate of the calculation capacitor.

In summary, in terms of computing speed, since the in-memory computing unit performs calculations based on charge, theoretically the speed can be close to DRAM; in terms of power consumption, capacitors are energy storage devices, and the averaging stage of matrix-vector calculations does not consume energy, so it has certain advantages over other in-memory computing solutions in terms of power consumption; in terms of computing density, flash memory itself has a high storage density, which can further enable large-scale parallelism of in-memory computing units and improve computing energy efficiency; in terms of computing reliability, calculations are based on charge, and there is no current-type flash memory in-memory computing that suffers from a decrease in computing reliability due to the decrease in the reliability of the storage device itself; in terms of computing architecture, the size of the convolutional layer and the computing scale of the fully connected layer can be flexibly configured according to the specific algorithm, and the existing in-memory computing path will not affect the original storage function, and the calculation will not affect the reliability of the storage; this makes the application range of this architecture wider than the current-type flash memory in-memory computing that modifies the original storage structure.

The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims (9)

1. A multi-bit matrix vector multiplication calculation unit, characterized in that it includes an analog voltage signal input module, a flash memory storage unit, a calculation capacitor module, a proportional time signal generation module and a readout circuit module, wherein the output end of the analog voltage signal input module is connected to the drain end of the flash memory storage unit, the output end of the proportional time signal generation module is connected to the gate end of the flash memory storage unit, the source end of the flash memory storage unit is connected to the input end of the calculation capacitor module, and the output end of the calculation capacitor module is connected to the input end of the readout circuit module, wherein: The analog voltage signal input module is used to generate an analog input voltage signal and load it to the drain end of the flash memory storage unit; The flash memory storage unit is used to store digital weights; The capacitance calculation module is used to perform multiplication calculation processing on the analog input voltage signal and the digital weight, and output the calculation result in the form of a voltage signal; The proportional time signal generating module is used to generate a voltage signal of proportional time length and control the conduction time of the flash memory storage unit; The proportional time signal generating module includes a clock generator, a first digital delay unit, a second digital delay unit, a first input XOR gate, a second input XOR gate and a third input XOR gate, wherein the first output end of the clock generator is connected to the first input end of the first input XOR gate, the first input end of the second input XOR gate and the first input end of the third input XOR gate respectively, the second output end of the clock generator is connected to the input end of the first digital delay unit, the output end of the first digital delay unit is connected to the second input end of the first input XOR gate, the output end of the second digital delay unit is connected to the second input end of the second input XOR gate, and the input end of the second digital delay unit is connected to the second input end of the third input XOR gate, wherein: The clock generator is used to generate a computing clock signal; The first digital delay unit and the second digital delay unit are used to delay the calculation clock signal to obtain a delayed calculation clock signal; The first input XOR gate, the second input XOR gate and the third input XOR gate are used to perform XOR calculation on the calculation clock signal and the delayed calculation clock signal to obtain a voltage signal of equal proportional time length; The readout circuit module is used to convert the calculation result in the form of a voltage signal and output the calculation result in the form of a digital signal. 2. According to claim 1, a multi-bit matrix-vector multiplication calculation unit is characterized in that the analog voltage signal input module is specifically implemented in any one of the following two construction modes: The first construction method: construction through digital-to-analog converter ADC; The second construction method is to construct by electrically connecting the sensor and the amplifier. 3. A multi-bit matrix-vector multiplication calculation unit according to claim 1, characterized in that the flash memory storage unit includes at least one flash memory device, and the flash memory device is used to store 1-bit data. 4. A multi-bit matrix-vector multiplication calculation unit according to claim 1, characterized in that the calculation capacitance module comprises a plurality of calculation capacitance units, a connection switch and a grounding switch, the calculation capacitance unit is electrically connected to the connection switch, and the calculation capacitance unit is electrically connected to the grounding switch, wherein: The capacitance calculation unit is used to perform multiplication calculation processing on the analog input voltage signal and the digital weight; The connecting switch is used to connect the calculating capacitance unit; The grounding switch is used to clear the charge of the calculation capacitor unit. 5. A multi-bit matrix-vector multiplication calculation unit according to claim 1, characterized in that the readout circuit module is an analog-to-digital converter. 6. A multi-bit matrix-vector multiplication calculation array, characterized in that it comprises a plurality of multi-bit matrix-vector multiplication calculation units as described in claim 1 arranged in parallel. 7. A working method of a multi-bit matrix-vector multiplication calculation array, characterized in that it includes the multi-bit matrix-vector multiplication calculation unit as described in claim 1, and also includes an independent calculation capacitor working mode and a shared calculation capacitor working mode. 8. The method for operating a multi-bit matrix vector multiplication calculation array according to claim 7, wherein the independent capacitance calculation working mode specifically comprises the following steps: The connection switch and the grounding switch are closed, and the calculation capacitance unit is cleared to obtain a calculation capacitance module after the charge is cleared; The connecting switch is disconnected from the grounding switch, and an analog input voltage signal is obtained based on an analog voltage signal input module, and a proportional time signal generation module obtains a voltage signal of proportional time length; The analog input voltage signal is loaded to the drain end of the flash memory unit, the voltage signal of the equal-proportional time length is loaded to the source end of the flash memory unit, the calculation capacitance module after the charge is cleared is charged, and the digital weight is obtained; The connection switch is closed, the grounding switch remains open, and the analog input voltage signal and the digital weight are multiplied and calculated based on the capacitance calculation module, and the calculation result in the form of a voltage signal is output; The calculation result in the form of a voltage signal is converted and processed by a readout circuit module, and the calculation result in the form of a digital signal is output. 9. According to claim 8, a working method of a multi-bit matrix-vector multiplication calculation array is characterized in that the shared calculation capacitor working mode is to construct at least one page module, the page module includes at least one flash memory storage unit and at least one calculation capacitor module, the flash memory storage unit and the calculation capacitor module are connected one-to-one, if one of the page modules is in a working state, the connection switches of the other page modules are disconnected and the gate end of the flash memory storage unit is not loaded with a voltage signal of equal proportional time length.