CN117747654A - A new topology HEMT device - Google Patents

Abstract

The invention discloses a new topological HEMT device, which includes: a substrate, a semiconductor layer and a plurality of basic units; along the direction perpendicular to the plane of the substrate, the shortest straight line between the gate and the drain in each basic unit The orthographic projection of at least one insulating blocking area overlaps with the orthographic projection of the shortest straight line between the source and the drain. The orthographic projection overlaps with at least one orthographic projection of the insulating blocking area. There is at least one in the basic unit. The 2DEG area is used to connect the source and drain via the gate. This path does not pass through the insulation blocking area and the shortest distance that the current passes is greater than the shortest straight-line distance between the source and the drain; the basic unit does not use the 2DEG area but A path connecting the source and drain without passing through the gate. There is at least one point on the source that is the shortest straight line to the drain that does not pass through the gate. The invention can effectively change the electric field distribution between the source and drain and the gate and drain, and improves the voltage resistance and reliability of the device.

Description

A new topology HEMT device

Technical field

The invention belongs to the field of semiconductor technology, and specifically relates to a new topology HEMT device.

Background technique

HEMT devices have two-dimensional electron gas 2DEG as the current conduction channel, so they have high electron mobility and electron density, and are suitable for making high-frequency devices. In particular, GaN-based HEMT devices have been used in the fields of power devices and radio frequency devices in recent years. Widely used, it has become a hot topic of current research.

GaN-based HEMT devices are planar devices, that is, the gate, source and drain of the device are all on the same side of the device, and when designing the contact electrodes of the gate, source and drain, they are often designed to be parallel to each other, that is, the current Starting from a point on the source, passing through the conductive channel of 2DEG, passing through the gate point closest to the straight line distance, and reaching the drain point closest to the straight line distance.

The layout topology design of gate, source and drain of existing GaN-based HEMT devices follows the principle of being parallel to each other, that is, the shortest distance from source to gate to drain is the same at every point. Or the shortest straight line distance from source to drain is always larger than the shortest straight line distance from gate to drain and the difference is fixed. No matter how the layout topology is improved, such as from intersecting fingers or combs to concentric circles, or to hexagons, pentagons or even triangles nested layer by layer, the gate, source and drain Always maintain the same shortest straight-line distance between each other, and there must be a point on the shortest straight-line distance from the source to the drain that passes through the gate. This is also the reason why the source and drain can be controlled through the gate. The basic principles of current conduction between pipe sections.

However, due to the design method in which the gate, source and drain are parallel to each other in the existing technology, the voltage resistance of GaN-based HEMT devices can only be improved by increasing the distance between the source and drain. Therefore, the reliability of the device and The voltage resistance characteristics are limited.

Contents of the invention

In order to solve the above-mentioned problems existing in the prior art, the present invention provides a new topology HEMT device. The technical problems to be solved by the present invention are achieved through the following technical solutions:

The invention provides a new topology HEMT device, which includes: a substrate, a semiconductor layer located on one side of the substrate, and a plurality of basic units located on the side of the semiconductor layer away from the substrate. The channel layer in the semiconductor layer is close to the potential barrier. One side of the layer includes a 2DEG area, the plurality of basic units are arranged in an array, and the gates, sources and drains of all basic units are connected in parallel;

Each basic unit includes: a source, a drain, a gate, and an insulating blocking region located on the semiconductor layer. The insulating blocking region is used to form on the 2DEG region between the source and drain of the basic unit. Obstruction; Along the direction perpendicular to the plane of the substrate, the orthographic projection of the shortest straight line between the gate and the drain in each basic unit overlaps with at least the orthographic projection of one of the insulating blocking regions, the source and the drain The orthographic projection of the shortest straight line between the electrodes overlaps with at least one orthographic projection of the insulation blocking region, and there is at least one path in the basic unit using the 2DEG region to connect the source and the drain through the gate, This path does not pass through the insulation blocking area and the shortest distance that the current passes is greater than the shortest straight-line distance between the source and the drain; the basic unit does not have a path that uses the 2DEG area but connects the source and the drain without passing through the gate. There is at least one point on the pole where the shortest straight line to the drain does not pass through the gate.

In one embodiment of the present invention, in the basic unit, the shortest straight line distance between the gate electrode and the drain electrode is greater than or equal to the shortest straight line distance between the source electrode and the drain electrode.

In one embodiment of the present invention, the insulation blocking area includes an opening;

In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the side of the source electrode close to the drain electrode is surrounded by the orthographic projection of the insulation blocking region, and the shortest straight line between the source electrode and the drain electrode is The orthographic projection only overlaps with the orthographic projection of the insulation blocking region, and the extending directions of the source electrode and the drain electrode are parallel.

In one embodiment of the present invention, the orthographic projection of the shortest straight line between the gate and the drain in the basic unit only overlaps the orthographic projection of the insulation blocking region.

In one embodiment of the present invention, the shortest straight line between the gate and the drain in the basic unit starts from the gate, passes through the source and the insulation blocking region in sequence, and then reaches the drain.

In one embodiment of the present invention, the isolation blocking region includes a first blocking region and a second blocking region, the drain electrode includes a first drain electrode and a second drain electrode, and the gate electrode includes a first gate and second gate;

In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the side of the first drain close to the source is surrounded by the orthographic projection of the first blocking region, and the orthographic projection of the second drain close to the side of the source is surrounded by the orthographic projection of the first blocking region. The front projection is surrounded by the front projection of the second blocking area, and the front projection of the source is located between the front projection of the first grid, the front projection of the second grid, the front projection of the first blocking area and the second In the closed area formed by the orthographic projection of the blocking region, and the orthographic projection of the shortest straight line connecting the source to the first drain only overlaps with the orthographic projection of the first insulating blocking region, and the orthographic projection from the source to the second drain The orthographic projection of the shortest straight line connecting the gate electrode to the first drain electrode only overlaps with the orthographic projection of the second insulation blocking region, and the orthographic projection of the shortest straight line connecting the gate electrode to the first drain electrode overlaps with the orthographic projection of the source electrode and the first drain electrode. The orthographic projection of an insulation blocking region all overlaps, and the orthographic projection of the shortest straight line connecting the gate to the second drain overlaps with the orthographic projection of the source and the orthographic projection of the second insulation blocking region;

The shortest straight line distance from the source electrode to the first drain electrode is equal to the shortest straight line distance from the source electrode to the second drain electrode, and the shortest straight line distance from the source electrode to the first gate electrode is equal to the shortest straight line distance from the source electrode to the second gate electrode.

In one embodiment of the present invention, in the basic unit, the shortest straight line between at least one point of the source electrode and the drain electrode passes through at least one insulation blocking region and does not pass through the 2DEG region covered by the gate electrode.

In one embodiment of the present invention, in each basic unit, the drain electrode includes a first drain electrode and a second drain electrode, and the insulating blocking region includes a first blocking region and a second blocking region;

In a direction perpendicular to the plane of the substrate, the orthographic projection of the first blocking region is located on the side of the orthographic projection of the first drain electrode close to the orthographic projection of the second drain electrode, and at least part of the first drain electrode The front projection of the electrode is surrounded by the front projection of the first blocking area, and the front projection of the second blocking area is located on the side of the front projection of the second drain electrode close to the front projection of the first drain electrode, And at least part of the orthographic projection of the second drain is surrounded by the orthographic projection of the second blocking region, and the orthographic projection of the gate is located between the orthographic projection of the first blocking region and the orthogonal projection of the second blocking region. Between the orthographic projections, the gate electrode includes a first gate electrode and a second gate electrode, the source electrode is located between the first gate electrode and the second gate electrode, and the source electrode is connected to the first drain electrode/second drain electrode. The orthographic projection of the shortest straight line connecting the poles only overlaps the orthographic projection of the first insulation blocking area/second insulation blocking area.

In one embodiment of the present invention, the extension direction of the first gate electrode is parallel to the extension direction of the second gate electrode, the extension direction of the first drain electrode is parallel to the extension direction of the second drain electrode, and the extension direction of the first gate electrode is parallel to the extension direction of the second drain electrode. The extension direction of the first gate electrode is perpendicular to the extension direction of the first drain electrode;

The shortest straight line distance from the source electrode to the first drain electrode is equal to the shortest straight line distance from the source electrode to the second drain electrode, and the shortest straight line distance from the source electrode to the first gate electrode is equal to the shortest straight line distance from the source electrode to the second gate electrode.

In one embodiment of the present invention, the shortest straight line between the source and the drain in the basic unit starts from the source and passes through at least one insulating blocking area, the 2DEG area covered by the gate and at least one insulating resistor in sequence. After the break area reaches the drain.

In one embodiment of the present invention, in each basic unit, the insulation blocking area includes: a first blocking area and a second blocking area; in a direction perpendicular to the plane of the substrate, the first blocking area The orthographic projection of the region is located on the side of the source electrode that is close to the drain electrode's orthographic projection, and the orthographic projection of the second blocking region is located on the side of the drain electrode's orthographic projection that is close to the source electrode's orthographic projection. The orthographic projection of the gate is located between the orthographic projection of the first blocking region and the orthographic projection of the second blocking region.

In one embodiment of the present invention, the basic unit includes multiple sets of source electrodes and drain electrodes, wherein in at least one set of source electrodes and drain electrodes, the shortest straight line between at least one point of the source electrode and the drain electrode is In the 2DEG area that passes through at least one insulating blocking area and is not covered by the gate, the shortest straight line distance between the gate and the drain is greater than or equal to the shortest straight line distance between the source and the drain, and the shortest straight line between the gate and the drain The connection starts from the gate, passes through the source and the insulation blocking area, and then reaches the drain.

In one embodiment of the present invention, the insulation blocking region is formed by etching the semiconductor layer to form a recessed area, and filling the recessed area with a predetermined material by sidewall deposition or complete filling; wherein , the filling material is Ga _x O _1-x ;

Alternatively, the insulating blocking region is formed by converting the semiconductor material in the semiconductor layer into an insulating semiconductor material or a P-type semiconductor material through ion implantation.

Compared with the prior art, the beneficial effects of the present invention are:

The present invention provides a new topological HEMT device, which makes full use of the widespread presence of 2DEG in the semiconductor layer, and designs a new topological structure in which the shortest straight line between the source and the drain in the basic unit does not pass through the gate. Based on the principle of new topological structures, various topological structures with gate, source and drain combinations have been extended. These topological structures have common characteristics in electrical characteristics: First, the electric field distribution between the source and drain in the basic unit is mainly Act on the insulating blocking area, while the electric field distribution between the source and drain of the traditional HEMT device topology all acts on the gate. Therefore, the HEMT device provided by the present invention can improve the impact of the drain voltage on the gate performance. ; Secondly, the electric field distribution between the gate, source and gate and drain in the basic unit is not uniform. Taking the electric field distribution between the gate and drain as an example, the closer the gate part is to the drain, the stronger the electric field it endures. In traditional HEMT devices, the electric field distribution between the gate and electrode and the source and drain is uniform, so the above-mentioned HEMT devices can obtain different gate turn-on characteristics and are more suitable for some special application scenarios, such as obtaining different dv/dt and di/dt characteristics; thirdly, when the source-drain channel is turned on, the current conduction path in the 2DEG does not necessarily coincide with the direction of the electric field between the source-drain electrode and is not necessarily parallel, and the current direction in some areas may even be perpendicular to the source-drain electrode. The direction of the electric field between the source and drain electrodes of the traditional HEMT device topology is parallel or coincident with the direction of the electric field between the source and drain electrodes. Therefore, the HEMT device provided by the present invention can effectively reduce the continuous acceleration of carriers by the electric field. The hot carrier emission effect caused by this makes it less likely for carriers to break away from the 2DEG and enter the semiconductor material surface or buffer zone, eventually causing current collapse, thereby improving the reliability of the device; furthermore, because part of the gate reaches the drain The path of the electrode will pass through the source first, so the source potential will provide a natural protective barrier to the gate when the device is turned off. It is also more conducive to the source field plate to function, thereby improving the device's withstand voltage characteristics and dynamics when turned on. The purpose of the feature.

The present invention will be further described in detail below with reference to the accompanying drawings and examples.

Description of drawings

Figure 1 is a schematic structural diagram of a basic unit provided by an embodiment of the present invention;

Figure 2 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 3 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 4 is a schematic diagram of an arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 5 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 6 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 7 is a schematic diagram of a topological connection circuit provided by an embodiment of the present invention;

Figure 8 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 9 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 10 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 11 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 12 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 13 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 14 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 15 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 16 is another structural schematic diagram of a basic unit provided by an embodiment of the present invention;

Figure 17 is another schematic diagram of the arrangement of multiple basic units provided by an embodiment of the present invention;

Figure 18 is a schematic diagram of an insulation blocking area provided by an embodiment of the present invention;

Figure 19 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 20 is another schematic diagram of an insulation blocking area provided by an embodiment of the present invention;

Figure 21 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 22 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 23 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 24 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 25 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 26 is another schematic diagram of the insulation blocking area provided by the embodiment of the present invention;

Figure 27 is a top view of the insulation blocking region provided by the embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific examples, but the implementation of the present invention is not limited thereto.

Referring to Figures 1-3, 8, 10 and 12, embodiments of the present invention provide a new topology HEMT device, including: a substrate, a semiconductor layer located on one side of the substrate, and a side of the semiconductor layer away from the substrate. A plurality of basic units. The side of the channel layer in the semiconductor layer close to the barrier layer includes a 2DEG region. The multiple basic units are arranged in an array. The gate G, source S and drain D of all basic units are respectively in parallel;

Each basic unit includes: a source S, a drain D, a gate G, and an insulating blocking region 10 located on the semiconductor layer. The insulating blocking region 10 is used between the source and drain D of the basic unit. Obstacles are formed on the 2DEG area between; along the direction perpendicular to the plane of the substrate, the orthographic projection of the shortest straight line between the gate G and the drain D in each basic unit is at least the same as that of one of the insulating blocking areas 10 The orthographic projection overlaps. The orthographic projection of the shortest straight line between the source S and the drain D overlaps with at least one orthographic projection of the insulation blocking region 10. There is at least one 2DEG region in the basic unit. The path connecting the source S and the drain D through the gate G does not pass through the insulation blocking area 10 and the shortest distance that the current passes is greater than the shortest straight-line distance between the source and the drain D; the basic unit does not use The 2DEG area connects the source S and the drain D without passing through the gate G. There is at least one shortest straight line from the source S to the drain D that does not pass through the gate G.

Specifically, the topological structure of the above-mentioned HEMT device includes a basic unit composed of a topological pattern of gate G, source S and drain D. Each basic unit can realize the gate G, drain D in a complete HEMT device. Control and conduction characteristics between source S and drain D. These basic units are arranged in an array. A large-area, high-current device can be directly obtained by repeatedly distributing the basic units. That is, the sources S of each basic unit are connected in parallel to form a unified source S, and the sources S of each basic unit are connected in parallel. The drains D are connected in parallel to form a unified drain D, and the gates G of each basic unit are connected in parallel to form a unified gate G. For example, an insulating isolation area can also be made around the basic unit to make the basic unit into an independent small unit. After connecting several independent small units together in series or parallel, a large-area, A high-current device or a circuit topology, such as a half-bridge circuit.

Usually, GaN-based HEMT devices mainly include a substrate, a buffer layer, a channel layer and a barrier layer grown sequentially on the substrate. Above the barrier layer, there is also a semiconductor layer surface as a cap layer and a surface passivation layer. It needs to be explained. What is interesting is that the new topological structure of the HEMT device provided by the present invention takes the GaN-based HEMT device structure as an example, and mainly designs the relative positions of the gate G, the source S and the drain D and the insulation blocking area 10 and other functional areas, but It is not limited to general GaN-based HEMT device structures, but is applicable to any GaN-based HEMT device structure. No matter what kind of GaN-based HEMT device structure, the common point is that 2DEG widely exists between the barrier layer and the channel layer. From a top view, the 2DEG area covers the entire device semiconductor surface and/or surface passivation layer. That is, as long as the area not covered by the insulating blocking region 10 and/or the insulating isolation region has 2DEG, the production of the gate G can modulate the 2DEG below the gate G and reduce or restore the electron density in the 2DEG, but it does not Affects the existence of 2DEG regions.

Optionally, in the basic unit, the shortest straight line distance between the gate G and the drain D is greater than or equal to the shortest straight line distance between the source S and the drain D.

As shown in Figures 1-3, the insulation blocking area 10 includes openings;

In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the side of the source S close to the drain D is surrounded by the orthographic projection of the insulating blocking region 10, and the orthographic projection between the source S and the drain D is The orthographic projection of the shortest straight line only overlaps the orthographic projection of the insulation blocking region 10 , and the extending directions of the source electrode S and the drain electrode D are parallel.

In the above basic unit, the source and drain D are mainly composed of an insulating blocking region 10. Preferably, the extending directions of the source S and the drain D are parallel to each other. The source S is surrounded by the insulating blocking region 10 and the insulating blocking region An opening is provided on the farthest side of 10 from the drain D, and a gate G is provided at the opening position. Preferably, the extending direction of the gate G is parallel to the extending direction of the source S.

Alternatively, as shown in Figure 1, the gate G can be arranged in the opening, that is, the shortest straight line between the gate and the drain D in the basic unit starts from the gate G and passes through the source S and the insulation blocking area in sequence. 10 to reach the drain D; in addition, as shown in Figure 2-3, the gate G can also be set outside the opening, that is to say, the orthographic projection of the shortest straight line between the gate and drain D in the basic unit is only Overlapping with the orthographic projection of the insulation blocking area 10 . In the basic unit composed of the above topological pattern, the distance from the gate G to the drain D is greater than or equal to the distance from the source S to the drain D. There is no device semiconductor layer that is completely separated by the insulation blocking region 10 in the basic unit. Surface or surface passivation layer area, that is, there is at least one path that uses the 2DEG area to connect the source S and the drain D through the gate G, and there is no path that uses the 2DEG area but does not go through the gate G to connect the source S and the drain D. of passage.

Furthermore, an insulating isolation area is made around the basic unit to make the basic unit into an independent small unit, and a large-area device is obtained by splicing several independent small units together. Of course, as shown in Figure 4-6, a large-area device can also be obtained by directly repeatedly distributing the basic units. Figure 7 shows a schematic diagram of the topological connection circuit in the HEMT device. When the basic units are repeatedly distributed, in the same row The basic units can be directly spliced, and the basic units in different rows must be spliced through horizontal mirror flipping, and the opening positions of the source S that are not surrounded by the insulating isolation area should be aligned with each other.

Optionally, as shown in Figure 8, the isolation blocking region includes a first blocking region 101 and a second blocking region 102, and the drain D includes a first drain electrode D1 and a second drain electrode D2, so The gate G includes a first gate G1 and a second gate G2;

In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the first drain D1 close to the source S is surrounded by the orthographic projection of the first blocking region 101, and the second drain D2 is close to the source. The orthographic projection of the electrode S side is surrounded by the orthographic projection of the second blocking region 102. The orthographic projection of the source electrode S is located in the orthographic projection of the first gate electrode G1, the orthographic projection of the second gate electrode G2, and the orthographic projection of the first gate electrode G2. The orthographic projection of the blocking region 101 and the orthographic projection of the second blocking region 102 form a closed area, and the orthographic projection of the shortest straight line connecting the source S to the first drain D1 is only blocked by the first insulation. The orthographic projection of the region 10 overlaps, and the orthographic projection of the shortest straight line connecting the source S to the second drain D2 only overlaps with the orthographic projection of the second insulation blocking region 10, and the gate G to the first drain The orthographic projection of the shortest straight line connecting D1 overlaps the orthographic projection of the source S and the orthographic projection of the first insulation blocking region 10 , and the orthographic projection of the shortest straight line connecting the gate G to the second drain D2 Overlapping with the orthographic projection of the source S and the orthographic projection of the second insulation blocking region 10;

The shortest straight line distance from the source S to the first drain D1 is equal to the shortest straight line distance from the source S to the second drain D2. The shortest straight line distance from the source S to the first gate G1 is equal to the shortest straight line distance from the source S to the second gate G2. The shortest straight line distances are equal.

Optionally, in the basic unit, the shortest straight line between at least one point of the source S and the drain D passes through at least one insulation blocking region 10 and does not pass through the 2DEG region covered by the gate G.

Please continue to refer to Figure 8. In each basic unit, the drain D includes a first drain D1 and a second drain D2, and the insulation blocking region 10 includes a first blocking region 101 and a second blocking region 102. ;

In a direction perpendicular to the plane of the substrate, the orthographic projection of the first blocking region 101 is located on the side of the orthographic projection of the first drain electrode D1 close to the orthographic projection of the second drain electrode D2, and is at least partially The orthographic projection of the first drain D1 is surrounded by the orthographic projection of the first blocking region 101 , and the orthographic projection of the second blocking region 102 is located near the orthographic projection of the second drain D2 close to the first drain. The front projection side of electrode D1 and at least part of the front projection of second drain electrode D2 are surrounded by the front projection of the second blocking region 102 , and the front projection of the gate G is located in the first blocking region 101 Between the orthographic projection of the first gate electrode G1 and the orthographic projection of the second blocking region 102, the gate electrode G includes a first gate electrode G1 and a second gate electrode G2, and the source electrode S is located between the first gate electrode G1 and the second gate electrode G2. Between the gates G2, the orthographic projection of the shortest straight line connecting the source S to the first drain D1/second drain D2 is only in contact with the first insulation blocking region 10/the second insulation blocking region 10 orthographic projection overlap.

Specifically, in the basic unit, the source S is located between the first drain D1 and the second drain D2, and the shortest straight-line distance from the source S to the first drain D1 only passes through the first blocking region 101 without passing through The shortest straight line distance from the gate G, the source S to the second drain D2 only passes through the second blocking region 102 and does not pass through the gate G; the first drain D1 is close to the first drain D1 toward the source S side. The first blocking region 101 is provided and at least part of the orthographic projection of the first drain electrode D1 is surrounded by the orthographic projection of the first blocking region 101. Only the side farthest from the source electrode S is not provided with the first blocking region 101, A second blocking region 102 is provided on the side of the second drain D2 toward the source S and close to the second drain D2, and at least part of the orthographic projection of the second drain D2 is surrounded by the orthographic projection of the second blocking region 102. Only The second blocking region 102 is not provided on the side farthest from the source S; further, the orthographic projection of the gate G is located between the orthographic projection of the first blocking region 101 and the orthographic projection of the second blocking region 102, The gate G includes a first gate G1 and a second gate G2. The orthographic projection of the source S is located in a closed area formed by the orthographic projections of the two gates G and the orthographic projections of the two insulation blocking regions 10. The shortest straight line distance from electrode G to drain D must pass through source S and insulation blocking region 10 .

Preferably, the shortest straight-line distances from the source S to the first drain D1 and the second drain D2 are equal, and the shortest straight-line distances from the source S to the first gate G1 and the second gate G2 are equal.

It should be understood that in the basic unit composed of such a topological pattern, there is no device semiconductor layer surface or surface passivation layer area that is completely separated by the insulation blocking area 10, that is, there is at least one 2DEG area connected to the source S through the gate G. and the drain D, and there is no path that uses the 2DEG region but does not pass through the gate G to connect the source S and the drain D. The basic unit can be made into an independent small unit by making an insulating isolation area around the basic unit, and a large-area device can be obtained by splicing several independent small units together; of course, as shown in Figure 9, by repeatedly distributing the basic units It is also possible to directly obtain a large-area device. At this time, the basic units in the same row can be directly spliced, and the opening positions of the drains D of the basic units in different rows that are not surrounded by insulating isolation areas are aligned with each other.

Optionally, please refer to FIG. 10 , the extension direction of the first gate G1 and the second gate G2 are parallel, and the extension direction of the first drain D1 is parallel to the extension direction of the second drain D2 Parallel, and the extension direction of the first gate G1 is perpendicular to the extension direction of the first drain D1;

The shortest straight line distance from the source S to the first drain D1 is equal to the shortest straight line distance from the source S to the second drain D2. The shortest straight line distance from the source S to the first gate G1 is equal to the shortest straight line distance from the source S to the second gate G2. The shortest straight line distances are equal.

Specifically, the basic unit includes two drains D, namely a first drain D1 and a second drain D2. The source S is located between the first drain D1 and the second drain D2. The first drain D1 faces A first blocking region 101 is provided on one side of the source electrode S close to the first drain electrode D1, and at least part of the orthographic projection of the first drain electrode D1 is surrounded by the orthographic projection of the first blocking region 101, with only the one furthest from the source electrode S being The first blocking region 101 is not provided on one side of the second drain electrode D2 toward the source electrode S, a second blocking region 102 is provided near the second drain electrode D2, and at least part of the orthographic projection of the second drain electrode D2 is Surrounded by the orthographic projection of the second blocking region 102, only the side farthest from the source S is not provided with the second blocking region 102; two gates are provided between the first blocking region 101 and the second blocking region 102. The electrodes G are the first gate G1 and the second gate G2. Preferably, the extending direction of the first gate G1 and the second gate G2 are parallel, and the extending direction of the first drain D1 is parallel to the extending direction of the second drain D2. The extending directions are parallel, and the extending direction of the first gate G1 is perpendicular to the extending direction of the first drain D1. As shown in Figure 10, the source S is also located in the middle area of the two gates G. Preferably, the shortest straight line distance from the source S to the first drain D1 is equal to the shortest straight line distance to the second drain D2, and The shortest straight line distance from the source S to the first gate G1 is equal to the shortest straight line distance from the source S to the second gate G2. In addition, in this topological structure, the shortest straight line distance from the source S to the first drain D1 only passes through the first blocking region 101 and does not pass through the gate G, and the shortest straight line distance from the source S to the second drain D2 Only passes through the second blocking region 102 without passing through the gate G.

It should be noted that there is no device semiconductor layer surface or surface passivation layer area that is completely separated by the insulation blocking region 10 in the above basic unit, that is, there is at least one 2DEG area connected to the source S and the drain through the gate G. D path, and there is no path that uses the 2DEG region but does not pass through the gate G to connect the source S and the drain D. By making an insulating isolation area around the basic unit, the basic unit can be made into an independent small unit. By splicing several independent small units together, a large-area device can be obtained. Of course, as shown in Figure 11, the basic units can also be repeatedly distributed. To directly obtain a large-area device, when the basic units are repeatedly distributed, the basic units in the same row can be directly spliced, and the opening positions of the drains D of the basic units in different rows that are not surrounded by insulating isolation areas are aligned with each other.

Optionally, as shown in Figure 12, the shortest straight line between the source and drain D in the basic unit starts from the source S and passes through at least one insulation blocking region 10 and the 2DEG region covered by the gate G in sequence. and at least one insulating blocking region 10 before reaching the drain D.

Exemplarily, in each basic unit, the insulation blocking area 10 includes: a first blocking area 101 and a second blocking area 102; in a direction perpendicular to the plane of the substrate, the first blocking area 101 The front projection of the source electrode S is located on the side of the front projection of the source electrode S close to the front projection of the drain electrode D. The front projection of the second blocking region 102 is located on the side of the front projection of the drain electrode D close to the front projection of the source electrode S. On the other side, the orthographic projection of the gate G is located between the orthographic projection of the first blocking region 101 and the orthographic projection of the second blocking region 102 .

In this embodiment, a first blocking region 101 is provided near the source S on the side of the source S toward the drain D, and a second blocking region 102 is provided on the side of the drain D toward the source S and close to the drain D. , a gate G is disposed between the first blocking region 101 and the second blocking region 102; preferably, the extending direction of the gate G is perpendicular to the extending direction of the source S and the drain D. In the basic unit composed of the above topological pattern, there is no device semiconductor layer surface or surface passivation layer area that is completely separated by the insulation blocking area 10, that is, there is at least one 2DEG area connected to the source S and the drain D through the gate G. path, and there is no path that uses the 2DEG region but does not pass through the gate G to connect the source S and the drain D.

Furthermore, a large-area device can be obtained by repeatedly distributing such basic units in the manner shown in Figure 13. Alternatively, an insulating isolation area can be made around such basic units first, and the basic units can be made into independent small units. , and then splicing several independent small units together to obtain a large-area device. Among them, when the basic units are repeatedly distributed, two adjacent basic units in the same row are flipped through vertical mirroring and spliced, and basic units in different rows are spliced after flipping through horizontal mirroring.

Optionally, as shown in Figures 14-17, the basic unit includes multiple groups of source electrodes S and drain electrodes D, wherein in at least one group of source electrodes and drain electrodes D, at least one point of the source electrode S is in contact with the drain electrode The shortest straight line between D passes through at least one insulation blocking area 10 and does not pass through the 2DEG area covered by the gate G. The shortest straight line distance between the gate and the drain D is greater than or equal to the shortest distance between the source and the drain D. The straight line distance, and the shortest straight line between the gate and the drain D starts from the gate G, passes through the source S and the insulation blocking region 10 in sequence, and then reaches the drain D.

In this embodiment, the same basic unit includes multiple groups of source electrodes S and drain electrodes D. For at least one group of source electrodes S and drain electrodes D, there is an arrival path starting from the source electrode S and consisting of a 2DEG region. The path of the drain D passes through the gate G. The 2DEG area covered by the gate G on the path can control the opening and closing of the path. At the same time, the path does not pass through any insulation blocking area 10, and the current actually passes through the shortest time. The distance is greater than the shortest straight-line distance between the source S and the drain D. There is at least one point from the source S to the drain D. The shortest straight-line distance passes through at least one insulation blocking area 10 but does not pass through any 2DEG area covered by the gate G, The shortest straight-line distance from the gate G to the drain D is greater than or equal to the shortest straight-line distance between the source and the drain D. The shortest straight-line distance from the gate G to the drain D passes through at least one insulation blocking region 10. For example, the gate The shortest straight line distance from the electrode G to the drain D can first pass through the source S, then pass through the insulation blocking region 10 and then reach the drain D.

For the remaining sets of sources S and drains D in the basic unit, the shortest straight-line distance from the gate G to the drain D passes through at least one insulation blocking region 10, and the shortest straight-line distance from the source S to the drain D It also passes through at least one insulation blocking area 10 .

Optionally, the insulation blocking region 10 is made by etching the semiconductor layer to form a recessed area, and filling the recessed area with a predetermined material by sidewall deposition or complete filling; wherein, the filling The material is Ga _x O _1-x ;

Alternatively, the insulating blocking region 10 is formed by converting the semiconductor material in the semiconductor layer into an insulating semiconductor material or a P-type semiconductor material through ion implantation.

It should be understood that the main function of the insulation blocking region 10 is to destroy the 2DEG in the semiconductor layer to achieve the insulation blocking effect. During specific production, the semiconductor material in this region can be etched away first, and the etching depth needs to reach the channel layer. Preferably, the semiconductor material can be completely etched until the substrate is exposed; then, other materials are filled in the etched recessed area.

Specifically, please refer to Figure 18-24. The materials filled after etching include a variety of structures: (1) completely filling the recessed area with insulating dielectric material; (2) filling the recessed area with P-type through secondary epitaxial growth Materials, such as P-type GaN-based materials; (3) Deposit insulating dielectric material only on the inner wall of the recessed area; (4) Deposit insulating dielectric material on the inner wall of the recessed area and then fill it with metal; (5) Only deposit the insulating dielectric material on the inner wall of the recessed area P-type material is grown by secondary epitaxial growth on the inner wall of the recessed area; (6) P-type material is grown by secondary epitaxial growth only on the inner wall of the recessed area and then filled with metal; (7) P-type material is grown by secondary epitaxial growth of P-type material only on the inner wall of the recessed area and then filled with insulation media material.

It should be noted that, please refer to Figures 25-27. Taking the filling of insulating dielectric material and P-type material as an example, the retained P-type material can completely surround the recessed area in the top view shown in Figure 27.

Furthermore, a protective layer of P-type material, such as P-type GaN-based material, can also be formed on the surface area of the device semiconductor layer around the insulation blocking region 10 by epitaxy and etching.

Optionally, the above-mentioned insulation blocking region 10 can destroy the 2DEG in the semiconductor layer and form an insulation blocking effect by also converting the semiconductor material in the insulation blocking region 10 into a P-type doped material by means of ion implantation. complex semiconductor materials.

Furthermore, the depth of the insulating blocking region can be to block the 2DEG region and penetrate deep into the channel layer or buffer layer, or it can completely penetrate the entire semiconductor layer and directly penetrate into the substrate layer, that is, it can completely penetrate the buffer layer and interact with the substrate. touch.

The above-mentioned GaN material series mainly includes GaN, BN and Al _x Ga _y In _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) alloy materials.

The above-mentioned insulating dielectric material may be silicon oxide or nitride; of course, in some other embodiments of the present application, the insulating dielectric material may also be metal oxide or nitride, or other insulating materials. Not limited.

It can be seen from the above embodiments that the beneficial effects of the present invention are:

The present invention provides a new topological HEMT device, which makes full use of the widespread presence of 2DEG in the semiconductor layer, and designs a new topological structure in which the shortest straight line between the source and the drain in the basic unit does not pass through the gate. Based on the principle of new topological structures, various topological structures with gate, source and drain combinations have been extended. These topological structures have common characteristics in electrical characteristics: First, the electric field distribution between the source and drain in the basic unit is mainly Act on the insulating blocking area, while the electric field distribution between the source and drain of the traditional HEMT device topology all acts on the gate. Therefore, the HEMT device provided by the present invention can improve the impact of the drain voltage on the gate performance. ; Secondly, the electric field distribution between the gate, source and gate and drain in the basic unit is not uniform. Taking the electric field distribution between the gate and drain as an example, the closer the gate part is to the drain, the stronger the electric field it endures. In traditional HEMT devices, the electric field distribution between the gate and electrode and the source and drain is uniform, so the above-mentioned HEMT devices can obtain different gate turn-on characteristics and are more suitable for some special application scenarios, such as obtaining different dv/dt and di/dt characteristics; thirdly, when the source-drain channel is turned on, the current conduction path in the 2DEG does not necessarily coincide with the direction of the electric field between the source-drain electrode and is not necessarily parallel, and the current direction in some areas may even be perpendicular to the source-drain electrode. The direction of the electric field between the source and drain electrodes of the traditional HEMT device topology is parallel or coincident with the direction of the electric field between the source and drain electrodes. Therefore, the HEMT device provided by the present invention can effectively reduce the continuous acceleration of carriers by the electric field. The hot carrier emission effect caused by this makes it less likely for carriers to break away from the 2DEG and enter the semiconductor material surface or buffer zone, eventually causing current collapse, thereby improving the reliability of the device; furthermore, because part of the gate reaches the drain The path of the electrode will pass through the source first, so the source potential will provide a natural protective barrier to the gate when the device is turned off. It is also more conducive to the source field plate to function, thereby improving the device's withstand voltage characteristics and dynamics when turned on. The purpose of the feature.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " The directions indicated by "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" etc. or The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as a limitation of the present invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the present invention, unless otherwise clearly stated and limited, the term "above" or "below" a first feature of a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them. Furthermore, the terms "above", "above" and "above" a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature. “Below”, “below” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may join and combine the different embodiments or examples described in this specification.

Although the present application has been described herein in connection with various embodiments, in practicing the claimed application, those skilled in the art will understand and understand by reviewing the drawings, the disclosure, and the appended claims. Other variations of the disclosed embodiments are implemented. The word "comprising" does not exclude other components or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may perform several of the functions recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be combined to advantageous effects.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be concluded that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all of them should be regarded as belonging to the protection scope of the present invention.

Claims (13)

1. A new topological HEMT device, characterized in that it includes: a substrate, a semiconductor layer located on one side of the substrate, and a plurality of basic units located on the side of the semiconductor layer away from the substrate. A channel layer in the semiconductor layer The side close to the barrier layer includes a 2DEG region, the plurality of basic units are arranged in an array, and the gates, sources and drains of all basic units are connected in parallel; Each basic unit includes: a source, a drain, a gate, and an insulating blocking region located on the semiconductor layer. The insulating blocking region is used to form on the 2DEG region between the source and drain of the basic unit. Obstruction; Along the direction perpendicular to the plane of the substrate, the orthographic projection of the shortest straight line between the gate and the drain in each basic unit overlaps with at least the orthographic projection of one of the insulating blocking regions, the source and the drain The orthographic projection of the shortest straight line between the electrodes overlaps with at least one orthographic projection of the insulation blocking region, and there is at least one path in the basic unit using the 2DEG region to connect the source and the drain through the gate, This path does not pass through the insulation blocking area and the shortest distance that the current passes is greater than the shortest straight-line distance between the source and the drain; the basic unit does not have a path that uses the 2DEG area but connects the source and the drain without passing through the gate. There is at least one point on the pole where the shortest straight line to the drain does not pass through the gate. 2. The HEMT device with new topology according to claim 1, wherein in the basic unit, the shortest straight line distance between the gate and the drain is greater than or equal to the shortest straight line distance between the source and the drain. 3. The novel topological HEMT device according to claim 2, wherein the insulation blocking region includes an opening; In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the side of the source electrode close to the drain electrode is surrounded by the orthographic projection of the insulation blocking region, and the shortest straight line between the source electrode and the drain electrode is The orthographic projection only overlaps with the orthographic projection of the insulation blocking region, and the extending directions of the source electrode and the drain electrode are parallel. 4. The new topological HEMT device according to claim 3, characterized in that the orthographic projection of the shortest straight line between the gate and the drain in the basic unit only overlaps with the orthographic projection of the insulating blocking region. . 5. The new topological HEMT device according to claim 3, characterized in that the shortest straight line between the gate and the drain in the basic unit starts from the gate, passes through the source and the insulation blocking area in sequence, and then reaches the drain. pole. 6. The novel topological HEMT device according to claim 5, wherein the isolation blocking region includes a first blocking region and a second blocking region, and the drain electrode includes a first drain electrode and a second drain electrode. The gate electrode includes a first gate electrode and a second gate electrode; In each basic unit, along the direction perpendicular to the plane of the substrate, the orthographic projection of the side of the first drain close to the source is surrounded by the orthographic projection of the first blocking region, and the orthographic projection of the second drain close to the side of the source is surrounded by the orthographic projection of the first blocking region. The front projection is surrounded by the front projection of the second blocking area, and the front projection of the source is located between the front projection of the first grid, the front projection of the second grid, the front projection of the first blocking area and the second In the closed area formed by the orthographic projection of the blocking region, and the orthographic projection of the shortest straight line connecting the source to the first drain only overlaps with the orthographic projection of the first insulating blocking region, and the orthographic projection from the source to the second drain The orthographic projection of the shortest straight line connecting the gate electrode to the first drain electrode only overlaps with the orthographic projection of the second insulation blocking region, and the orthographic projection of the shortest straight line connecting the gate electrode to the first drain electrode overlaps with the orthographic projection of the source electrode and the first drain electrode. The orthographic projection of an insulation blocking region all overlaps, and the orthographic projection of the shortest straight line connecting the gate to the second drain overlaps with the orthographic projection of the source and the orthographic projection of the second insulation blocking region; The shortest straight line distance from the source electrode to the first drain electrode is equal to the shortest straight line distance from the source electrode to the second drain electrode, and the shortest straight line distance from the source electrode to the first gate electrode is equal to the shortest straight line distance from the source electrode to the second gate electrode. 7. The new topological HEMT device according to claim 1, characterized in that in the basic unit, there is at least one shortest straight line connection between the source electrode and the drain electrode passing through at least one insulation blocking area and not The 2DEG area covered by the gate. 8. The novel topological HEMT device according to claim 7, wherein in each basic unit, the drain electrode includes a first drain electrode and a second drain electrode, and the insulation blocking region includes a first blocking region. and second blocking zone; In a direction perpendicular to the plane of the substrate, the orthographic projection of the first blocking region is located on the side of the orthographic projection of the first drain electrode close to the orthographic projection of the second drain electrode, and at least part of the first drain electrode The front projection of the electrode is surrounded by the front projection of the first blocking area, and the front projection of the second blocking area is located on the side of the front projection of the second drain electrode close to the front projection of the first drain electrode, And at least part of the orthographic projection of the second drain is surrounded by the orthographic projection of the second blocking region, and the orthographic projection of the gate is located between the orthographic projection of the first blocking region and the orthogonal projection of the second blocking region. Between the orthographic projections, the gate electrode includes a first gate electrode and a second gate electrode, the source electrode is located between the first gate electrode and the second gate electrode, and the source electrode is connected to the first drain electrode/second drain electrode. The orthographic projection of the shortest straight line connecting the poles only overlaps the orthographic projection of the first insulation blocking area/second insulation blocking area. 9. The novel topological HEMT device according to claim 8, wherein the extension direction of the first gate electrode and the second gate electrode are parallel, and the extension direction of the first drain electrode is parallel to the extension direction of the second gate electrode. The extending direction of the drain electrode is parallel, and the extending direction of the first gate electrode is perpendicular to the extending direction of the first drain electrode; The shortest straight line distance from the source electrode to the first drain electrode is equal to the shortest straight line distance from the source electrode to the second drain electrode, and the shortest straight line distance from the source electrode to the first gate electrode is equal to the shortest straight line distance from the source electrode to the second gate electrode. 10. The HEMT device of new topology according to claim 1, characterized in that the shortest straight line between the source and the drain in the basic unit starts from the source and passes through at least one insulating blocking area and gate in sequence. The drain is reached after the electrode covers the 2DEG area and at least one insulating blocking area. 11. The new topological HEMT device according to claim 10, characterized in that in each basic unit, the insulation blocking area includes: a first blocking area and a second blocking area; along a plane perpendicular to the substrate direction, the orthographic projection of the first blocking region is located on the side of the orthographic projection of the source electrode close to the orthographic projection of the drain electrode, and the orthographic projection of the second blocking region is located on the orthographic projection of the drain electrode close to the source The orthographic projection of the grid is located between the orthographic projection of the first blocking area and the orthographic projection of the second blocking area. 12. The HEMT device of new topology according to claim 1, characterized in that the basic unit includes multiple groups of source electrodes and drain electrodes, wherein in at least one group of source electrodes and drain electrodes, at least one point of the source electrode The shortest straight line between the gate and the drain passes through at least one insulation blocking area and does not pass through the 2DEG area covered by the gate. The shortest straight line distance between the gate and the drain is greater than or equal to the shortest straight line distance between the source and the drain. , and the shortest straight line between the gate and the drain starts from the gate, passes through the source and the insulation blocking area, and then reaches the drain. 13. The new topology HEMT device according to claim 1, wherein the insulating blocking region is formed by etching the semiconductor layer to form a recessed region, and is deposited or completely filled with sidewalls in the recessed region. It is prepared by filling preset materials in a way; wherein, the filling material is Ga _x O _1-x ; Alternatively, the insulating blocking region is formed by converting the semiconductor material in the semiconductor layer into an insulating semiconductor material or a P-type semiconductor material through ion implantation.