CN116230714A - Gallium nitride integrated power chip and manufacturing method thereof - Google Patents

Abstract

The invention discloses a gallium nitride integrated power chip and a manufacturing method thereof. The gallium nitride integrated power chip includes a substrate, a cascode cascade structure arranged on the substrate, a metal sheet and a molding compound. The cascode cascade structure includes a gallium nitride transistor and a silicon transistor, the source of the gallium nitride transistor is connected to the drain of the silicon transistor, and the gate of the gallium nitride transistor is connected to the source of the silicon transistor. The metal pads are connected to GaN transistors and/or silicon transistors. The molding compound encapsulates the cascode structure, and the metal sheet is exposed outside the molding compound for heat dissipation. In the technical solution of the present invention, the metal sheet is connected to the gallium nitride transistor and/or the silicon transistor, and the heat dissipation can be performed by exposing the metal sheet to the outside of the plastic encapsulant, reducing the heat transfer path, so that the heat dissipation capability of the gallium nitride integrated power chip is greatly improved Improve and enhance the reliability of gallium nitride integrated power chips.

Description

Gallium nitride integrated power chip and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor devices, and more specifically, to a gallium nitride integrated power chip and a manufacturing method thereof.

Background technique

In related technologies, the GaN cascode cascade structure (Cascode) package is mainly for bottom heat dissipation, the heat generated by the chip has a long heat transfer path, and the heat dissipation efficiency is low. Efficient cooling requirements.

Contents of the invention

Embodiments of the present invention provide a gallium nitride integrated power chip and a manufacturing method thereof.

An embodiment of the present invention provides a gallium nitride integrated power chip. The gallium nitride integrated power chip includes a substrate, a cascode structure arranged on the substrate, a metal sheet, and a plastic packaging compound. The common source The common gate cascade structure includes a gallium nitride transistor and a silicon transistor, the source of the gallium nitride transistor is connected to the drain of the silicon transistor, the gate of the gallium nitride transistor is connected to the source of the silicon transistor connect. The metal sheet is connected to the gallium nitride transistor and/or the silicon transistor. The molding compound encapsulates the cascode structure, and the metal sheet is exposed outside the molding compound for heat dissipation.

In some embodiments, the substrate is a copper-clad ceramic substrate, and the gallium nitride transistor and the silicon transistor are connected to the copper-clad ceramic substrate through conductive silver paste.

In some embodiments, the GaN integrated power chip further includes a frame, and the substrate is connected to the frame through conductive silver paste.

In some embodiments, the metal piece includes a first metal piece, and the first metal piece is connected to the drain of the gallium nitride transistor as a drain pin.

In some embodiments, the metal piece includes a second metal piece connected to the source of the silicon transistor as a source pin.

In some embodiments, the second metal sheet is also used to connect the source of the silicon transistor and the gate of the gallium nitride transistor.

In some embodiments, the second metal sheet is exposed outside the molding compound for heat dissipation.

In some embodiments, the metal piece includes a third metal piece, and the third metal piece is connected to the gate of the silicon transistor as a gate pin.

In some embodiments, the metal sheet includes a fourth metal sheet, and the fourth metal sheet is used to connect the drain of the silicon transistor and the source of the gallium nitride transistor.

An embodiment of the present invention provides a method for manufacturing a gallium nitride integrated power chip. The manufacturing method includes: forming a cascode structure on a substrate, and the cascode structure includes a gallium nitride transistor and a gallium nitride transistor. A silicon transistor, the source of the gallium nitride transistor is connected to the drain of the silicon transistor, the gate of the gallium nitride transistor is connected to the source of the silicon transistor; the gallium nitride is connected by a metal sheet Transistors and/or the silicon transistors; encapsulating the cascode cascade structure with a plastic encapsulant, and the metal sheet is exposed outside the plastic encapsulant for heat dissipation.

In the gallium nitride integrated power chip and the manufacturing method thereof of the present invention, the metal sheet is connected to the gallium nitride transistor and/or the silicon transistor, and heat dissipation can be performed by exposing the metal sheet to the outside of the plastic encapsulant, reducing the heat transfer path, so that the gallium nitride The heat dissipation capability of the integrated power chip is greatly improved, and the reliability of the gallium nitride integrated power chip is enhanced.

Additional aspects and advantages of embodiments of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

FIG. 1 is a schematic structural diagram of a gallium nitride integrated power chip according to some embodiments of the present invention;

FIG. 2 is a schematic structural diagram of a gallium nitride integrated power chip according to some embodiments of the present invention;

3 is a schematic circuit diagram of a gallium nitride integrated power chip according to some embodiments of the present invention;

Fig. 4 is a schematic flow diagram of the manufacturing method of some embodiments of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary, are only for explaining the embodiments of the present invention, and should not be construed as limiting the embodiments of the present invention.

In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "thickness", "upper", "top", "bottom", "inner", "outer" etc. are based on those shown in the accompanying drawings. The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, but does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. And, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense. In one example, it can be a fixed connection, or a Detachably connected, or integrally connected; can be mechanically connected, or electrically connected, or can communicate with each other; can be directly connected, or indirectly connected through an intermediary, can be internal communication between two components or two components interaction relationship.

Gallium Nitride High Electron Mobility Transistor (GaN HEMT) has the characteristics of high mobility, high breakdown field strength, and wide bandgap. According to its operating characteristics, it is mainly divided into enhancement mode devices and depletion mode devices. The high-voltage depletion-mode GaN HEMT and the low-voltage enhancement-mode Si MOSFET are packaged together in a common-gate and common-source manner to form a normally-off Cascode (cascaded) GaN HEMT, and the drive power is compatible with the drive of the Si MOSFET device , can simplify the design of the driving circuit, greatly save the cost and reduce the design difficulty, and meet the application requirements of higher voltage and higher power. Common cascode-type GaN HEMT devices mainly adopt TO (Transistor Outline, transistor shape) and other packaging forms, and basically adopt bottom heat dissipation packaging solutions.

Specifically, a TO220 copper frame can be used as the packaging frame, firstly the copper-clad ceramic substrate is bonded to the base island of the frame through conductive silver paste, and then the Si MOSFET and GaN HEMT are bonded to the copper-clad ceramic substrate through conductive silver paste. Finally, lead wires (copper wires or aluminum wires) are used to form an electrical connection between the two chips and lead out the G pole, S pole and D pole of the mixing tube, and finally the chip is encapsulated by a plastic encapsulant.

The TO220 package is mainly single-sided bottom heat dissipation, and most GaN chips are planar structures at present, resulting in the heat generated by the die to be dissipated through the chip substrate, ceramic substrate, frame and other paths. The heat transfer path is lengthy and the heat dissipation efficiency is low. , the current package cannot meet the requirements of fast and efficient heat dissipation under high heat flux.

Referring to FIGS. 1 to 3 , an embodiment of the present invention provides a gallium nitride integrated power chip 100 , the gallium nitride integrated power chip 100 includes a substrate 10 , a cascode cascode structure 20 disposed on the substrate 10 , a metal sheet 30 and molding compound 40. The cascode cascode structure 20 includes a gallium nitride transistor 22 and a silicon transistor 24, the source of the gallium nitride transistor 22 is connected to the drain of the silicon transistor 24, the gate of the gallium nitride transistor 22 is connected to the source of the silicon transistor 24 pole connection. Metal sheet 30 is connected to GaN transistor 22 and/or Si transistor 24 . The molding compound 40 encapsulates the cascode structure 20 , and the metal sheet 30 is exposed outside the molding compound 40 for heat dissipation.

Referring to FIG. 4 , an embodiment of the present invention provides a method for manufacturing a GaN integrated power chip 100 , and the manufacturing method can be used to manufacture the GaN integrated power chip 100 in any embodiment of the present invention. Manufacturing methods include:

01: Form a cascode cascade structure 20 on the substrate 10, the cascode cascade structure 20 includes a gallium nitride transistor 22 and a silicon transistor 24, the source of the gallium nitride transistor 22 and the drain of the silicon transistor 24 connected, the gate of the gallium nitride transistor 22 is connected to the source of the silicon transistor 24;

02: use the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24;

03: Encapsulate the cascode cascode structure 20 with a molding compound 40 , and the metal sheet 30 is exposed outside the molding compound 40 for heat dissipation.

The gallium nitride integrated power chip 100 of the present invention can be a GaN HEMT cascaded power device. The gallium nitride integrated power chip 100 is suitable for packaging design of Cascode high-voltage GaN HEMT devices with a breakdown voltage of 650V and above, and is suitable for high-voltage high-power electronic devices. device for better heat dissipation.

In the gallium nitride integrated power chip 100 and its manufacturing method of the present invention, the metal sheet 30 is connected to the gallium nitride transistor 22 and/or the silicon transistor 24, and the metal sheet 30 is exposed to the outside of the plastic encapsulant 40 to dissipate heat and reduce heat transfer The path greatly improves the heat dissipation capability of the GaN integrated power chip 100 and enhances the reliability of the GaN integrated power chip 100 . In addition, the cascode cascade structure 20 can achieve relatively high and stable threshold voltage and gate operating voltage.

The molding compound 40 may include a heat dissipation area, through which the metal sheet 30 is exposed to the outside of the molding compound 40, and the cascode cascode structure 20 is located between the substrate 10 and the heat dissipation area, that is to say, the heat dissipation area may be located on the gallium nitride The top of the power chip 100 is integrated to realize the top heat dissipation packaging design.

The gallium nitride transistor 22 may be a GaNHEMT chip, and the GaNHEMT chip is a high-voltage-resistant depletion-type GaN-based power chip with a lateral structure. Silicon transistor 24 may be a Si MOSFET chip. The Si MOSFET chip is a low-voltage, enhanced silicon-based power MOS chip with a vertical structure. The schematic diagram of the cascode cascade structure 20 can be referred to FIG. 3 , the cascode cascade structure 20 has a forward turn-on voltage enhanced mode of operation through cascading, wherein the silicon transistor 24 controls the turn-on and turn-off of the entire device When the device is turned off, the GaN transistor 22 plays a role of withstanding high voltage.

The metal sheet 30 can be a copper sheet. In the present invention, the electrical connection of the gallium nitride transistor 22 and/or the silicon transistor 24 can be realized by using the copper sheet clamping process instead of the bonding and bonding process, so that the gallium nitride integrated power chip 100 can pass through the metal The chip 30 realizes heat dissipation at the top, and improves the shortcomings of the wire bonding process and bottom heat dissipation of the GaN HEMT cascode cascade structure in the related art.

Referring to FIG. 1 , in some embodiments, the substrate 10 is a copper-clad ceramic substrate 10 , and the gallium nitride transistor 22 and the silicon transistor 24 are connected to the copper-clad ceramic substrate 10 through a conductive silver paste 50 .

In some embodiments, step 01 (forming a cascode structure 20 on the substrate 10) includes:

012: Connect the gallium nitride transistor 22 and the copper-clad ceramic substrate 10 through the conductive silver paste 50 , and connect the silicon transistor 24 and the copper-clad ceramic substrate 10 through the conductive silver paste 50 .

In this way, the GaN transistor 22 and the silicon transistor 24 can be fixed and electrically connected through the conductive silver paste 50 .

Referring to FIG. 1 and FIG. 2 , in some embodiments, the GaN integrated power chip 100 further includes a frame 60 , and the substrate 10 is connected to the frame 60 through a conductive silver paste 50 .

In some embodiments, the manufacturing method also includes:

04: Connect the substrate 10 and the frame 60 through the conductive silver paste 50 .

In this way, the GaN integrated power chip 100 can be packaged and protected by the frame 60 . Specifically, the substrate 10 may be connected to the base island of the frame 60 through the conductive silver paste 50 .

In some implementations, the frame 60 may be a SOT (Small Outline Transistor, Small Outline Transistor) frame 60, and the heat in the gallium nitride integrated power chip 100 may pass through the bottom of the cascode structure 20, the substrate 10 and the The frame 60 realizes bottom heat dissipation.

Referring to FIG. 1 and FIG. 2 , in some embodiments, the metal piece 30 includes a first metal piece 32 , and the first metal piece 32 is connected to the drain of the GaN transistor 22 as a drain pin.

In some embodiments, step 02 (using the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24) includes:

021: use the first metal sheet 32 to connect the drain of the GaN transistor 22 as the drain pin.

In this way, the drain of the GaN transistor 22 can be taken out as the drain pin of the cascode structure 20 .

In some embodiments, the first metal sheet 32 is exposed outside the molding compound 40 for heat dissipation. In this way, heat dissipation can be achieved through the first metal sheet 32 .

Referring to FIGS. 1 and 2 , in some embodiments, the metal piece 30 includes a second metal piece 34 connected to the source of the silicon transistor 24 as a source pin.

In some embodiments, step 02 (using the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24) includes:

023: use the second metal sheet 34 to connect the source of the silicon transistor 24 as the source pin.

In this way, the source of the silicon transistor 24 can be taken out as the source pin of the cascode structure 20 .

Referring to FIG. 2 , in some embodiments, the second metal sheet 34 is also used to connect the source of the silicon transistor 24 and the gate of the GaN transistor 22 .

In some embodiments, step 02 (using the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24) includes:

025: use the second metal sheet 34 to connect the source of the silicon transistor 24 and the gate of the gallium nitride transistor 22 .

In this way, the cascode structure 20 can be formed by connecting the source of the silicon transistor 24 and the gate of the GaN transistor 22 .

In some embodiments, the second metal sheet 34 is exposed outside the molding compound 40 for heat dissipation. In this way, heat dissipation can be achieved through the second metal sheet 34 . Specifically, please refer to FIG. 1 , the second metal sheet 34 exposes the molding compound 40 from the top to realize top heat dissipation.

Referring to FIG. 2 , in some embodiments, the metal piece 30 includes a third metal piece 36 , and the third metal piece 36 is connected to the gate of the silicon transistor 24 as a gate pin.

In some embodiments, step 02 (using the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24) includes:

027: use the third metal sheet 36 to connect the gate of the silicon transistor 24 as a gate pin.

In this way, the gate of the silicon transistor 24 can be taken out as the gate pin of the cascode structure 20 .

Referring to FIG. 2 , in some embodiments, the metal sheet 30 includes a fourth metal sheet 38 for connecting the drain of the silicon transistor 24 and the source of the GaN transistor 22 .

In some embodiments, step 02 (using the metal sheet 30 to connect the GaN transistor 22 and/or the silicon transistor 24) includes:

029: use the fourth metal sheet 38 to connect the drain of the silicon transistor 24 and the source of the gallium nitride transistor 22 .

In this way, the cascode structure 20 can be formed by connecting the drain of the silicon transistor 24 and the source of the GaN transistor 22 .

In the description of this specification, descriptions with reference to the terms "certain embodiments", "in one example", "exemplarily" and the like mean that specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in the In at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiment of the present invention has been shown and described above, it can be understood that the above embodiment is exemplary and should not be construed as a limitation of the present invention, and those skilled in the art can make the above-mentioned The embodiments are subject to changes, modifications, substitutions and variations.

Claims (10)

1. A gallium nitride integrated power chip, characterized in that the gallium nitride integrated power chip comprises: Substrate; A cascode cascade structure disposed on the substrate, the cascode cascade structure includes a gallium nitride transistor and a silicon transistor, the source of the gallium nitride transistor is connected to the drain of the silicon transistor connected, the gate of the gallium nitride transistor is connected to the source of the silicon transistor; a metal sheet connected to the gallium nitride transistor and/or the silicon transistor; A molding compound, the molding compound encapsulates the cascode structure, and the metal sheet is exposed outside the molding compound for heat dissipation. 2. The gallium nitride integrated power chip according to claim 1, wherein the substrate is a copper-clad ceramic substrate, and the gallium nitride transistor and the silicon transistor are connected to the copper-clad ceramic through conductive silver paste Substrate connection. 3. The gallium nitride integrated power chip according to claim 1, wherein the gallium nitride integrated power chip further comprises: a frame, the substrate is connected to the frame through conductive silver paste. 4. The gallium nitride integrated power chip according to claim 1, wherein the metal sheet comprises a first metal sheet, and the first metal sheet is connected to the drain of the gallium nitride transistor as a drain pole pins. 5. The gallium nitride integrated power chip according to claim 1, wherein the metal sheet comprises a second metal sheet, and the second metal sheet is connected to the source of the silicon transistor as a source lead foot. 6. The gallium nitride integrated power chip according to claim 5, wherein the second metal sheet is also used to connect the source of the silicon transistor and the gate of the gallium nitride transistor. 7. The GaN integrated power chip according to claim 5, wherein the second metal sheet is exposed outside the molding compound for heat dissipation. 8. The gallium nitride integrated power chip according to claim 1, wherein the metal sheet comprises a third metal sheet, and the third metal sheet is connected to the gate of the silicon transistor as a gate lead foot. 9. The gallium nitride integrated power chip according to claim 1, wherein the metal sheet comprises a fourth metal sheet, and the fourth metal sheet is used to connect the drain of the silicon transistor and the nitrogen source of the GaN transistor. 10. A method of manufacturing a gallium nitride integrated power chip, characterized in that the method of manufacturing comprises: A cascode cascade structure is formed on the substrate, the cascode cascade structure includes a gallium nitride transistor and a silicon transistor, the source of the gallium nitride transistor is connected to the drain of the silicon transistor, so The gate of the gallium nitride transistor is connected to the source of the silicon transistor; connecting the gallium nitride transistor and/or the silicon transistor by using a metal sheet; The cascode cascaded structure is encapsulated by a molding compound, and the metal sheet is exposed outside the molding compound for heat dissipation.

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