CN116166222B

CN116166222B - Pseudo-random binary sequence generating device and checking device

Info

Publication number: CN116166222B
Application number: CN202310443747.3A
Authority: CN
Inventors: 周波; 李谊
Original assignee: Shanghai Mi Silicon Technology Co ltd
Current assignee: Shanghai Mi Silicon Technology Co ltd
Priority date: 2023-04-24
Filing date: 2023-04-24
Publication date: 2023-07-11
Anticipated expiration: 2043-04-24
Also published as: CN116166222A

Abstract

The invention provides a pseudo-random binary sequence generating device and a checking device, wherein the generating device comprises two groups of shift register circuits, clock signal circuits, a data synthesizer and a control circuit which are symmetrically arranged, and the generation of a half-clock frequency PRBS sequence is realized based on the feedback of the two groups of clock signals with opposite phases, so that the working frequency of a shift register core is reduced. In addition, by arranging PRBS generating circuits with various code types in the circuits, PRBS sequence checking devices which generate different code types based on switching in application can be correspondingly arranged with the generating devices, and checking of PRBS sequences with different code types of half clock signal frequency generated by the generating devices can be realized. The generating device and the checking device can meet the simulation requirement of data streams with different code types during chip self-checking, and the defect that the traditional PRBS generating and checking device can only generate or check the PRBS sequence with the fixed code type is avoided.

Description

Pseudo-random binary sequence generating device and checking device

Technical Field

The invention relates to the technical field of digital communication, in particular to a Pseudo random binary sequence (PRBS, pseudo-Random Binary Sequence) generating device and a checking device.

Background

The pseudo-random binary sequence refers to a pseudo-random sequence only comprising 0 and 1, has not only the statistical property of the random sequence and the good autocorrelation property of Gaussian noise, but also certain coding rules, can be repeatedly generated and processed, and is widely applied to the communication field, for example, in the simulation and test of a high-speed digital communication link for simulating a real data stream. Wherein PRBS is generated by primitive polynomial, which is characterized by a plurality of linear feedback shift registers connected in series in turn, the length of the shift registers is called the order n, and the common orders are 7, 9, 11, 15, 20, 23 and 31, and the cycle period of PRBS is 2 ⁿ -1。

Currently, for each PRBS pattern, a corresponding PRBS Generator (PRBS Generator) is configured to generate a PRBS data stream, for example, taking a 7-order PRBS pattern as an example, the PRBS Generator includes 7 shift registers (LFSRs, linear Feedback Shift Registers) and an exclusive-or circuit (Xor), where the 7 shift registers are sequentially connected, and the output of the sixth register is input to the first register after being exclusive-ored with the output of the seventh register, and the output of the seventh register is the output of the PRBS Generator, that is, the PRBS (PRBS data stream). Wherein the primitive polynomial corresponding to 7-order PRBS code pattern is X ⁶ +X ⁷ +1。

PRBS codes are commonly used for simulating and testing high-speed digital communication links to simulate real data flows, and the shift register core of the existing PRBS generator has higher working frequency, so that the design difficulty is increased. In addition, the existing PRBS generating device and the checking device are required to correspondingly set a PRBS generator and a checking device aiming at different PRBS code types, so that the cost of simulation and test is high, and especially when a chip is subjected to self-checking, the data flow of different code types is required to be simulated, and the self-checking requirement of the chip cannot be met by a single PRBS generator and checking device, so that the self-checking efficiency of the chip is low.

Disclosure of Invention

In view of the above, the present invention aims to provide a pseudo-random binary sequence generating device and a checking device, so as to reduce the working frequency of the shift register core, meet the simulation requirement of the chip self-checking on the data streams with different code types, and avoid the defect that the conventional PRBS generating and checking device can only generate or check the PRBS sequence with fixed code types.

In a first aspect, an embodiment of the present invention provides a pseudo random binary sequence generating device, including:

an n-order pseudo-random binary sequence PRBS generator for generating an n-order PRBS sequence based on a half-clock signal frequency, the n-order PRBS sequence including 2 ⁿ -1 bit of data, n being an integer greater than 3, comprising: two groups of shift register circuits, a clock signal circuit, a data synthesizer and a control circuit which are symmetrically arranged, wherein,

the shift register circuit is used for encoding the initial value to obtain PRBS data;

the clock signal circuit is used for generating a clock signal, inputting the clock signal into the data synthesizer and synchronously and inversely inputting the clock signal input ends of the two groups of shift register circuits;

two input ends of the data synthesizer are respectively connected with the outputs of the two groups of shift register circuits to receive PRBS data and output an n-order PRBS sequence based on half clock signal frequency according to the clock signal;

and the control circuit is used for controlling the shift register circuit and the clock signal circuit.

With reference to the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, wherein each set of shift register circuits includes: the first D flip-flop module comprises (n-3)/2 first D flip-flops which are connected in sequence;

the initial value sequentially passes through a first D trigger module, a third latch, a second latch and a first latch to be shifted and encoded, and then PRBS data is output;

Two input ends of the first selector are respectively connected with the input ends of the first latch and the third latch;

the two input ends of the logic gate circuit are respectively connected with the output end of the first selector and the final output end of the other group of shift register circuits which are symmetrically arranged, and the output end is connected with the input end of the first D trigger module.

With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a second possible implementation manner of the first aspect, where the logic gate circuit is an exclusive or gate or an exclusive or gate.

With reference to the first possible implementation manner of the first aspect, the present embodiment provides a third possible implementation manner of the first aspect, where n is 7 or 9 or 11 or 15 or 21 or 23 or 31.

With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the clock signals are input to the respective latches in the two sets of shift register circuits and the clock signal input terminal of the first D flip-flop in synchronous inversion, and the input clock signals of the first latch, the third latch and the second latch of each set of shift register circuits are input in synchronous inversion with the first D flip-flop input clock signal.

With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a fifth possible implementation manner of the first aspect, wherein each group of shift register circuits further includes 1 second selector and a second D flip-flop module, forming an m-order PRBS generator for generating 2 ^m -a 1-bit PRBS sequence, wherein m is an integer greater than n, a secondThe D trigger module comprises (m-n) and 2 second D triggers which are connected in sequence;

the logic gate circuit is connected with the input end of the first D trigger module through the second selector: one input end of the second selector is connected with the output end of the logic gate circuit, and the output end of the second selector is connected with the input end of the first D trigger module;

the output end of the second D trigger module is connected with the other input end of the second selector, and the input end of the second D trigger module is connected with the output end of the logic gate circuit.

With reference to the fifth possible implementation manner of the first aspect, the present embodiment provides a sixth possible implementation manner of the first aspect, where n is 7 or 9 or 11 or 15 or 21 or 23, and m is 11 or 15 or 21 or 23 or 31.

With reference to the fifth possible implementation manner of the first aspect, the present embodiment provides a seventh possible implementation manner of the first aspect, where,

Each group of shift register circuits also comprises 1 third selector and a third D trigger module, forming an r-order PRBS generator for generating 2 ^r -a PRBS sequence of bits 1, where r is an integer greater than m, the third D flip-flop module comprising (m-n)/2 sequentially connected third D flip-flops;

the logic gate circuit is connected with the input end of the second D trigger module through a third selector: one input end of the third selector is connected with the output end of the logic gate circuit, and the output end of the third selector is connected with the input end of the second D trigger module;

the output end of the third D trigger module is connected with the other input end of the third selector, and the input end of the third D trigger module is connected with the output end of the logic gate circuit.

With reference to the seventh possible implementation manner of the first aspect, the present embodiment provides an eighth possible implementation manner of the first aspect, wherein n is 7 or 9 or 11 or 15, m is 11 or 15 or 21 or 23, and r is 15 or 21 or 23 or 31.

In a second aspect, an embodiment of the present invention provides a PRBS data generating method, which is characterized by applying the generating device of the fifth possible embodiment or the seventh possible embodiment, and includes the following steps:

s1, a control circuit receives PRBS sequence generation indication information and controls two groups of shift register circuits to reset to a preset value;

S2, the control circuit controls the PRBS generator with the corresponding order to be started according to the indication information to obtain a target PRBS sequence, wherein the method comprises the following steps:

controlling the conduction of an n-order PRBS generator and other corresponding trigger modules and selectors;

inputting corresponding control signals to the selection ends of the conducted selectors to control the outputs of the selectors;

the control clock signal circuit generates a clock signal, and the clock signal is synchronously and reversely input into two groups of shift register circuits to respectively obtain final outputs A and B;

A. b, inputting a clock signal into a data synthesizer;

and controlling the data synthesizer to output A or B on the rising edge and the falling edge of the clock signal respectively so as to obtain the target PRBS sequence.

In a third aspect, an embodiment of the present invention provides a pseudo random binary sequence PRBS verification device, including: the PRBS sequence generated by the generating device applied to check any one of the first to eighth possible embodiments of the first aspect includes 2 groups of second shift register circuits, 2 groups of delay circuits, 2 second logic gates, and a second clock signal circuit, a second control circuit, and 1 third logic gate that are symmetrically arranged;

each group of second shift register circuits is used for encoding the received PRBS data and transmitting the encoding results to 2 second logic gate circuits respectively;

Each group of delay circuits is used for delaying the received PRBS data and transmitting delay results to 2 second logic gate circuits respectively;

each second logic gate circuit is used for carrying out logic operation on the received coding result and the delay result, and transmitting the operation result to a third logic gate circuit respectively;

the third logic gate circuit is used for comparing the received 2 operation results and outputting a signal whether the PRBS sequence generated by the generating device is correct or not;

the second clock signal circuit is used for generating a second clock signal and synchronously and inversely inputting clock signal input ends of the two groups of second shift register circuits;

the second control circuit is used for controlling the second shift register circuit and the second clock signal circuit.

With reference to the third aspect, an embodiment of the present invention provides a first possible implementation manner of the third aspect, where each set of second shift register circuits includes:

a fourth D flip-flop;

the logic operation of the fourth logic gate circuit and the logic gate circuit of the generating device are mutually non-operation;

the fifth D trigger module comprises (n-1)/2 fifth D triggers which are connected in sequence;

The sixth D trigger module comprises (m-n)/2 sixth D triggers which are connected in sequence;

the two input ends of the fourth selector are respectively connected with the output ends of the fifth D trigger module and the sixth D trigger module;

the latch circuit comprises a fourth latch, the input end of the fourth latch is connected with the output end of the fourth D trigger, and the output end of the fourth latch is connected with one input end of a second logic gate circuit of the other group of second shift register circuits;

the input end of the delay circuit is respectively connected with the output end of the fourth D trigger;

two input ends of the second logic gate circuit are respectively connected with the output ends of the delay circuit and the fourth selector;

the two input ends of the third logic gate circuit are respectively connected with the output ends of the two second logic gate circuits.

With reference to the third aspect, an embodiment of the present invention provides a second possible implementation manner of the third aspect, where each group of third shift register circuits includes sequentially connected:

a seventh D flip-flop;

an eighth logic gate circuit, wherein the logic operations of the eighth logic gate circuit and the logic gate circuit of the generating device are mutually non-operations;

an eighth D trigger module comprising (n-1)/2 eighth D triggers connected in sequence;

A ninth D trigger module comprising (m-n)/2 ninth D triggers connected in sequence;

a tenth D trigger module comprising (r-m-2)/2 tenth D triggers connected in sequence;

and a fifth selector, wherein the two input ends are respectively connected with the output ends of the eighth D trigger module and the ninth D trigger module;

the latch circuit comprises a sixth selector, wherein two input ends are respectively connected with the output end of the seventh D trigger through an eleventh D trigger; a fifth latch, the input end of which is connected with the output end of the sixth selector, and the output end of which is connected with one input end of an eighth logic gate circuit of the other group of third shift register circuits;

a seventh selector, wherein two input ends are respectively connected with the output end of the fifth selector and the output end of the tenth D trigger module;

the input end of the delay circuit is connected with the output end of the seventh D trigger;

two input ends of the second logic gate circuit are respectively connected with the output ends of the delay circuit and the seventh selector;

the two input ends of the third logic gate circuit are respectively connected with the output ends of the two second logic gate circuits, and the output of the third logic gate circuit is used for representing whether the PRBS sequence is correct or not.

With reference to the third aspect, an embodiment of the present invention provides a third possible implementation manner of the third aspect, where the PRBS verification device further includes an inverter, and the PRBS data enters the shift register circuit after passing through the inverter.

The pseudo-random binary sequence generating device and the checking device provided by the embodiment of the invention comprise: an n-order pseudo-random binary sequence PRBS generator for generating an n-order PRBS sequence based on a half-clock signal frequency, the n-order PRBS sequence including 2 ⁿ -1 bit data, nIs an integer greater than 3, comprising: the device comprises two groups of shift register circuits, a clock signal circuit, a data synthesizer and a control circuit which are symmetrically arranged, wherein the shift register circuits are used for encoding initial values to obtain PRBS data; the clock signal circuit is used for generating a clock signal, inputting the clock signal into the data synthesizer and synchronously and inversely inputting the clock signal input ends of the two groups of shift register circuits; two input ends of the data synthesizer are respectively connected with the outputs of the two groups of shift register circuits to receive PRBS data and output an n-order PRBS sequence based on half clock signal frequency according to the clock signal; and the control circuit is used for controlling the shift register circuit and the clock signal circuit. Therefore, based on the two groups of shift register circuits, the clock signal circuit, the data synthesizer and the control circuit which are symmetrically arranged, the working frequency of the shift register core can be reduced, meanwhile, the pseudo-random binary sequence switching of different code types is realized, the simulation requirement on data streams of different code types during chip self-checking is met, and the defect that the traditional PRBS generating and checking device can only generate or check the PRBS sequence of a fixed code type is avoided.

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a pseudo-random binary sequence generating device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a pseudo-random binary sequence generating device according to an embodiment of the present invention;

FIG. 4 is a flowchart of a PRBS data generation method according to an embodiment of the present invention;

FIG. 5 shows a schematic diagram of a pseudo random binary sequence PRBS verification device according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another configuration of a pseudo random binary sequence PRBS verification device according to an embodiment of the present invention;

FIG. 7 is a schematic diagram showing a specific structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing another specific structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention;

FIG. 9 is a schematic diagram showing a specific structure of a pseudo random binary sequence checking device according to an embodiment of the present invention;

fig. 10 is a schematic diagram showing another specific structure of a pseudo random binary sequence checking device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.

The embodiment of the invention provides a pseudo-random binary sequence generation device and a verification device, and the pseudo-random binary sequence generation device and the verification device are described through the embodiment.

Fig. 1 shows a schematic structural diagram of a pseudo-random binary sequence generating device according to an embodiment of the present invention. As shown in fig. 1, includes:

an n-order pseudo-random binary sequence PRBS generator for generating an n-order PRBS sequence based on a half-clock signal frequency, the n-order PRBS sequence including 2 ⁿ -1 bit of data, n being an integer greater than 3, comprising: two sets of

shift register circuits

02 and 03, a clock signal circuit 04, a data synthesizer 05 and a control circuit (not shown) which are symmetrically arranged, wherein,

a shift register circuit 02 (03) for encoding the initial value to obtain PRBS data;

a clock signal circuit 04 for generating a clock signal, inputting the clock signal to the data synthesizer 05, and inputting the clock signal input terminals of the two sets of shift register circuits 02 (03) in synchronous and inverted phases;

two input ends of the data synthesizer 05 are respectively connected with the outputs of the two groups of shift register circuits 02 (03) to receive PRBS data and output an n-order PRBS sequence based on half clock signal frequency according to the clock signal;

a control circuit for controlling the shift register circuit 02 (03) and the clock signal circuit 04.

In the embodiment of the present invention, 02 represents one set of shift register circuits of the two sets of shift register circuits, and 03 represents the other set of shift register circuits of the two sets of shift register circuits. As an alternative embodiment, each group of shift register circuits includes: a first latch 021 (031), a second latch 022 (032), a third latch 023 (033) and a first D flip-flop module 024 (034), 1 first selector 025 (035), and 1 logic gate 026 (036) connected in sequence, wherein the first D flip-flop module comprises (n-3)/2 first D flip-flops 027, 028 (037, 038) connected in sequence;

the initial value is shifted and encoded by the first D trigger module 024 (034), the third latch 023 (033), the second latch 022 (032) and the first latch 021 (031) in sequence, and then PRBS data is output;

two input ends of the first selector 025 (035) are respectively connected with the input ends of the first latch 021 (031) and the third latch 023 (033);

the two inputs of the logic gate 026 (036) are connected to the output of the first selector 025 (035) and the final output of the other set of symmetrically arranged shift register circuits, respectively, and the output is connected to the input of the first D flip-flop module 024 (034).

In an embodiment of the present invention, as an alternative embodiment, the logic gate is an exclusive or gate or an exclusive or gate.

In an embodiment of the present invention, n is 7 or 9 or 11 or 15 or 21 or 23 or 31 as an alternative embodiment.

In the embodiment of the present invention, as an alternative embodiment, clock signals are input to the clock signal input terminals of the first D flip-flop and each latch in the two sets of shift register circuits in synchronous inversion, and input clock signals of the first latch and the third latch in each set of shift register circuits are input to the second latch and the first D flip-flop in synchronous inversion.

Fig. 2 is a schematic diagram of another structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention. In an embodiment of the present invention, as an alternative embodiment, each group of shift register circuits further includes 1 second selector 29 (39) and second D flip-flop module 081 (091) to form an m-stage PRBS generator for generating 2 ^m -a PRBS sequence of bits 1, where m is an integer greater than n, the second D flip-flop module 081 (091) comprising (m-n)/2 second D flip-flops 082, 083 (092, 093) connected in sequence;

logic gate 026 (036) is connected to the input of first D flip-flop module 024 (034) through second selector 29 (39): one input end of the second selector 29 (39) is connected with the output end of the logic gate circuit 026 (036), and the output end of the second selector 29 (39) is connected with the input end of the first D trigger module 024 (034);

The output of the second D flip-flop module 081 (091) is connected to the other input of the second selector 29 (39), and the input is connected to the output of the logic gate 026 (036).

In an embodiment of the present invention, as an alternative embodiment, n is 7 or 9 or 11 or 15 or 21 or 23, and m is 11 or 15 or 21 or 23 or 31.

Fig. 3 is a schematic diagram of still another structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention. In the embodiment of the present invention, as an alternative embodiment, each group of shift register circuits further includes 1 third selector 074 (084) and third D flip-flop module 075 (085) to form an r-stage PRBS generator for generating 2 ^r A PRBS sequence of 1 bit, wherein r is an integer greater than m, the third D flip-flop module 075 (085) comprises (m-n) 2 third D flip-flops 076, 077 (086, 087) connected in sequence,

logic gate 026 (036) is connected to the input of the second D flip-flop module through a third selector 074 (084): one input end of the third selector 074 (084) is connected with the output end of the logic gate circuit 026 (036), and the output end of the third selector 074 (084) is connected with the input end of the second D trigger module;

The output of the third D flip-flop module is connected to the other input of the third selector 074 (084), and the input is connected to the output of the logic gate 026 (036).

In an embodiment of the present invention, as an alternative embodiment, n is 7 or 9 or 11 or 15, m is 11 or 15 or 21 or 23, and r is 15 or 21 or 23 or 31.

Fig. 4 is a flowchart illustrating a PRBS data generation method according to an embodiment of the present invention. As shown in fig. 4. The generating device applying the above fig. 2 or 3 comprises the following steps:

A. b, inputting a clock signal into a data synthesizer;

Fig. 5 shows a schematic structural diagram of a pseudo random binary sequence PRBS verification device according to an embodiment of the present invention. As shown in fig. 5. In the embodiment of the present invention, as an alternative embodiment, the pseudo random binary sequence PRBS verification device is applied to verify the PRBS sequence generated by the generating device in fig. 1, 2, or 3, and includes 2 sets of second shift register circuits 051 (052), 2 sets of first delay circuits 053 (054), 2 second logic gate circuits 055 (056), and second clock signal circuits 057, second control circuits (not shown in the figure), and 1 third logic gate circuit 058, which are symmetrically arranged;

each group of second shift register circuits 051 (052) is used for encoding the received PRBS data and transmitting the encoding results to 2 second logic gates 055 (056) respectively;

each group of delay circuits 053 (054) is used for delaying the received PRBS data and respectively transmitting the delay results to 2 second logic gates 055 (056);

each second logic gate circuit 055 (056) is used for performing logic operation on the received coding result and the delay result, and transmitting the operation result to the third logic gate circuits 058 respectively;

the third logic gate circuit 058 is used for comparing the received 2 operation results and outputting a signal whether the PRBS sequence generated by the generating device is correct or not;

A second clock signal circuit 057 for generating a second clock signal and inputting clock signal input terminals of the two sets of second shift register circuits 051 (052) in synchronous and inverted phases;

and a second control circuit for controlling the second shift register circuit 051 (052) and the second clock signal circuit 057.

In an embodiment of the present invention, as an optional embodiment, each group of second shift register circuits includes, connected in sequence:

fourth D flip-flop 0511 (0521);

the fourth logic gate 0512 (0522), the logic operation of the fourth logic gate 0512 (0522) and the logic gate of the generating device are non-operation;

a fifth D trigger module comprising (n-1)/2 fifth D triggers 0513 (0523) connected in sequence;

a sixth D flip-flop module comprising (m-n)/2 sequentially connected sixth D flip-flops 0514 (0524);

and a fourth selector 0515 (0525), wherein two input ends are respectively connected with the output ends of the fifth D trigger module and the sixth D trigger module;

the latch circuit comprises a fourth latch 0516 (0526), wherein the input end of the fourth latch 0516 (0526) is connected with the output end of a fourth D trigger 0511 (0521), and the output end is connected with one input end of a second logic gate circuit 055 (056) of the other group of second shift register circuits;

The input ends of the first delay circuits 053 (054) are respectively connected with the output ends of the fourth D trigger 0511 (0521);

two input ends of the second logic gate circuit 055 (056) are respectively connected with the output ends of the first delay circuit 053 (054) and the fourth selector 0515 (0525);

the two input ends of the third logic gate circuit 058 are respectively connected with the output ends of the two second logic gate circuits 055 (056), and the output of the fourth logic gate circuit 0512 (0522) is used for representing whether the PRBS sequence is correct or not.

Fig. 6 is a schematic diagram of another structure of a pseudo random binary sequence PRBS verification device according to an embodiment of the present invention. As shown in fig. 6. In the embodiment of the present invention, as an alternative embodiment, the pseudo random binary sequence PRBS verification device is applied to verify the PRBS sequence generated by the PRBS generating device in fig. 3, and includes 2 sets of third shift register circuits 061 (062), 2 sets of second delay circuits 063 (064), 2 fifth logic gates 065 (066), and third clock signal circuits 067, third control circuits (not shown in the figure), and 1 sixth logic gate 068,

each group of third shift register circuits comprises sequentially connected:

seventh D flip-flop 0611 (0621);

An eighth logic gate 0612 (0622), the logic operations of the eighth logic gate 0612 (0622) and the logic gate of the PRBS generating device being non-operations;

an eighth D trigger module comprising (n-1)/2 eighth D triggers 0613 (0623) connected in sequence;

a ninth D flip-flop module including (m-n)/2 ninth D flip-flops 0614 (0624) connected in sequence;

a tenth D flip-flop module comprising (r-m-2)/2 tenth D flip-flops 0617 (0627) connected in sequence;

and a fifth selector 0615 (0625), wherein the two input ends are respectively connected with the output ends of the eighth D trigger module and the ninth D trigger module;

a latch circuit including a sixth selector 0618 (0628), two input terminals being respectively connected directly and through an eleventh D flip-flop to an output terminal of a seventh D flip-flop 0611 (0621); a fifth latch 0616 (0626), the input end of which is connected to the output end of the sixth selector 0618 (0628), the output end of which is connected to one input end of the eighth logic gate circuit of the other group of third shift register circuits;

a seventh selector 0619 (0629), two input ends are connected to the output end of the fifth selector 0615 (0625) and the output end of the tenth D trigger module respectively;

The input end of the second delay circuit 063 (064) is connected with the output end of the seventh D trigger 0611 (0621);

two input ends of the fifth logic gate circuit 065 (066) are respectively connected with the output ends of the second delay circuit 063 (064) and the seventh selector 0619 (0629);

the two input ends of the sixth logic gate circuit 068 are respectively connected with the output ends of the two fifth logic gate circuits 065 (066), and the output of the sixth logic gate circuit 068 is used for representing whether the PRBS sequence is correct or not;

a third clock signal circuit 067 for generating a third clock signal and inputting clock signal input terminals of the two groups of third shift register circuits in synchronous and inverted phases;

and a third control circuit for controlling the third shift register circuit 061 (062) and the third clock signal circuit 067.

In an embodiment of the present invention, as an alternative embodiment, the PRBS verification device of fig. 5 and 6 further includes an inverter 069, and the PRBS data enters the shift register circuit after passing through the inverter 069.

The PRBS generating device and the PRBS verification device according to the embodiments of the present invention will be described below with reference to two specific examples.

Fig. 7 is a schematic diagram showing a specific structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention. As shown in fig. 7, the apparatus includes: a first pattern pseudo-random binary sequence generator (not shown), a second pattern pseudo-random binary sequence generator (not shown), a first selector 101, a second selector 102, a third selector 103, a fourth selector 104, a fifth selector 105, a sixth selector 106, a first exclusive-or circuit 107, a second exclusive-or circuit 108, a clock generator 109, and a synthesizer 110, wherein,

The PRBS pattern of the first code pattern pseudo-random binary sequence generator is 7 steps, and the PRBS pattern of the second code pattern pseudo-random binary sequence generator is higher than 7 steps;

the first code pattern pseudo-random binary sequence generator comprises: a first shift register set 111, and a second shift register set 112, wherein,

the first shift register group includes: a first D flip-flop 113, a second D flip-flop 114, a first latch 115, a second latch 116, and a third latch 117;

the second shift register group includes: third D flip-flop 118, fourth D flip-flop 119, fourth latch 120, fifth latch 121, and sixth latch 122;

the second pattern pseudo-random binary sequence generator comprises: a third shift register group 123 and a fourth shift register group 124;

the clock signal (CLK) output by the clock generator 109 is respectively connected to the third shift register group 123, the first D flip-flop 113, the second D flip-flop 114, the second latch 116, the fourth latch 120, the sixth latch 122, and the first input terminal of the synthesizer 110;

after the clock signal is subjected to the inversion processing, the first input ends of the fourth shift register group 124, the third D flip-flop 118, the fourth D flip-flop 119, the first latch 115, the third latch 117 and the fifth latch 121 are respectively connected;

The output of the first D flip-flop 113 is connected to the second input terminal of the second D flip-flop 114, the output of the second D flip-flop 114 is connected to the second input terminal of the first latch 115 and the first input terminal of the second selector 102, respectively, the output of the first latch 115 is connected to the second input terminal of the second latch 116, the output of the second latch 116 is connected to the second input terminal of the third latch 117 and the zeroth input terminal of the second selector 102, respectively, and the output of the third latch 117 is connected to the second input terminal of the synthesizer 110 and the first input terminal of the second exclusive-or circuit 108, respectively;

the output of the third D flip-flop 118 is connected to the second input of the fourth D flip-flop 119, the output of the fourth D flip-flop 119 is connected to the second input of the fourth latch 120 and the first input of the fourth selector 104, respectively, the output of the fourth latch 120 is connected to the second input of the fifth latch 121, the output of the fifth latch 121 is connected to the second input of the sixth latch 122 and the zeroth input of the fourth selector 104, respectively, and the output of the sixth latch 122 is connected to the third input of the synthesizer 110 and the first input of the first exclusive-or circuit 107, respectively;

the output of the second selector 102 is connected to the second input end of the first exclusive-or circuit 107, the output of the first exclusive-or circuit 107 is connected to the first input end of the first selector 101 and the first input end of the fifth selector 105, the output of the fifth selector 105 is connected to the second input end of the third shift register group 123, the output of the third shift register group 123 is connected to the zeroth input end of the first selector 101, and the output of the first selector 101 is connected to the second input end of the first latch 115;

The output of the fourth selector 104 is connected to the second input terminal of the second exclusive-or circuit 108, the output of the second exclusive-or circuit 108 is connected to the zeroth input terminal of the third selector 103 and the zeroth input terminal of the sixth selector 106, the output of the sixth selector 106 is connected to the second input terminal of the fourth shift register set 124, the output of the fourth shift register set 124 is connected to the first input terminal of the third selector 103, and the output of the third selector 103 is connected to the second input terminal of the third latch 117;

synthesizer 110 outputs a pseudo-random binary sequence.

In the embodiment of the present invention, the output of the sixth latch 122 is the first data stream (labeled a in the figure), and the output of the third latch 117 is the second data stream (labeled B in the figure).

In the embodiment of the present invention, as an alternative embodiment, the first D flip-flop 113 includes a seventh latch and an eighth latch (not shown in the figure) connected to the seventh latch.

In the embodiment of the present invention, the structures of the second D flip-flop 114, the third D flip-flop 118, and the fourth D flip-flop 119 are the same as those of the first D flip-flop 113.

In an embodiment of the present invention, as an optional embodiment, the third shift register group 123 includes: fifth D flip-flop 125, sixth D flip-flop 126, fourth shift register group 124 includes: seventh D flip-flop 127, eighth D flip-flop 128, wherein,

The first input end of the fifth trigger 125 and the first input end of the sixth trigger 126 are connected with the clock signal output by the clock generator 109, the second input end of the fifth trigger 125 is connected with the output end of the fifth selector 105, the output end of the fifth trigger 125 is connected with the second input end of the sixth trigger 126, and the output end of the sixth trigger 126 is connected with the zeroth end of the first selector 101;

the first input of the seventh flip-flop 127 and the first input of the eighth flip-flop 128 are connected to the inverted signal of the clock signal, the second input of the seventh flip-flop 127 is connected to the output of the sixth selector 106, the output of the seventh flip-flop 127 is connected to the second input of the eighth flip-flop 128, and the output of the eighth flip-flop 128 is connected to the first end of the third selector 103.

In the embodiment of the present invention, the third shift register group 123 includes: the fifth D flip-flop 125, the sixth D flip-flop, is a 7-order pseudo-random binary sequence generator when the first pattern pseudo-random binary sequence generator operates independently, and is a 15-order pseudo-random binary sequence generator when the first pattern pseudo-random binary sequence generator operates simultaneously with the second pattern pseudo-random binary sequence generator. For other stages of pseudo-random binary sequence generators, this may be achieved by the number of flip-flops or latches in the third and fourth

shift register banks

123 and 124.

In the embodiment of the invention, for PRBS code pattern of 7 steps, the corresponding code length is 2 ⁷ -1。

In the embodiment of the present invention, the first shift register set 111 and the second shift register set 112 synchronize the inverted clock signals. The D flip-flop includes two Latches (LATCH), each LATCH corresponding to a shift register.

In an embodiment of the present invention, as an optional embodiment, the apparatus further includes:

a third pattern pseudo-random binary sequence generator (not shown) comprising: a fifth shift register group 129 and a sixth shift register group 130; wherein,,

the first input end of the fifth shift register group 129 is connected with the clock signal output by the clock generator 109, the second input end is connected with the output of the first exclusive-or circuit 107, and the output end is connected with the zeroth end of the fifth selector 105;

the first input of the sixth shift register bank 130 is connected to the inverted signal of the clock signal, the second input is connected to the output of the second exclusive-or circuit 108, and the output is connected to the first end of the sixth selector 106.

In this embodiment of the present invention, as an alternative embodiment, the fifth shift register group 129 includes, connected in sequence: the ninth D flip-flop, tenth D flip-flop, eleventh flip-flop, twelfth flip-flop (not shown in the figure), and the sixth shift register group 130 includes, connected in order: thirteenth, fourteenth, fifteenth, sixteenth flip-flops, wherein,

A first input of the fifth shift register group 129 is connected to the clock signal output from the clock generator 109;

a first input of the sixth shift register bank 130 is coupled to an inverted signal of the clock signal;

a second input end of the ninth D flip-flop is connected to the output end of the first exclusive or circuit 107, and an output end of the twelfth flip-flop is connected to the zeroth end of the fifth selector 105;

the second input of the thirteenth D flip-flop is coupled to the output of the second exclusive or circuit 108 and the output of the fifteenth flip-flop is coupled to the first terminal of the sixth selector 106.

In the embodiment of the invention, based on the first code type pseudo-random binary sequence generator, the second code type pseudo-random binary sequence generator and the third code type pseudo-random binary sequence generator, the pseudo-random binary sequences with different code types can be realized. For example, 7-order, 15-order and 31-order PRBS can be realized, wherein the switching among 7-order, 15-order and 31-order PRBS can be realized through one-out-of-three logic controllers, so that the data flow of the PRBS can be switched at will, different data flow test requirements can be met, and when one code pattern is gated, other irrelevant circuits are turned off so as to reduce power consumption.

In the embodiment of the present invention, as an optional embodiment, the logic controller outputs the binary control signal by using the digital module:

For example:

wherein 00 represents PRBS7, 01 represents PRBS15, 11 represents PRBS31, the logic controller converts the logic of the binary control signal into corresponding enabling control signal, controls the turning-off and the turning-on of each latch and the selector, and the selector is a two-out switch, namely a single pole double throw switch, so that three-out logic control of the PRBS7, 15, 31 generators is realized, and PRBS data streams corresponding to different code types are switched and output.

In the embodiment of the invention, for PRBS code pattern of 15 steps, the corresponding code length is 2 ¹⁵ -1, for a PRBS pattern of order 31, the corresponding code length is 2 ³¹ -1。

In the embodiment of the present invention, as an alternative embodiment, if the code pattern is 7 steps, the first end of the first selector 101 is connected to the output end, the zeroth end of the second selector 102 is connected to the output end, the zeroth end of the fourth selector 104 is connected to the output end, and the zeroth end of the third selector 103 is connected to the output end.

In the embodiment of the present invention, as an alternative embodiment, if the code pattern is 15 steps, the zeroth end of the first selector 101 is connected to the output end, the zeroth end of the second selector 102 is connected to the output end, the zeroth end of the fourth selector 104 is connected to the output end, and the first end of the third selector 103 is connected to the output end;

The first terminal of the fifth selector 105 is in communication with the output terminal, and the zeroth terminal of the sixth selector 106 is in communication with the output terminal.

In this embodiment of the present invention, as an alternative embodiment, if the code pattern is 31 steps, the zeroth end of the first selector 101 is connected to the output end, the first end of the second selector 102 is connected to the output end, the first end of the fourth selector 104 is connected to the output end, and the first end of the third selector 103 is connected to the output end;

the zeroth end of the fifth selector 105 is in communication with the output, and the first end of the sixth selector 106 is in communication with the output.

In the embodiment of the invention, according to different code patterns of the PRBS, the logic controller outputs corresponding binary control signals to control the switch of different devices, so that the PRBS7/15/31 can be switched at will, and the test requirements of different data streams are met. When the circuit is in operation, the unused circuit is turned off, so that the power consumption can be saved, and meanwhile, the interference among devices can be prevented.

In the embodiment of the invention, the working principle of the device is described by taking PRBS7 as an example:

in operation, the device performs a reset operation to make the initial values of the upper and lower paths (the first shift register set 111 and the second shift register set 112) the same, then performs a shift operation to shift the shift by using two sets of clock signals (synchronous inverted clocks) with 180 ° phase difference, then performs an exclusive-or operation to the output from the first selector 101 and the output (signal a) of the sixth latch 122 by the first exclusive-or circuit 107, and then inputs the output after the exclusive-or operation to the input of the first D flip-flop 113 after passing through the first selector 101; the second exclusive-or circuit 108 exclusive-or-operates the output from the fourth selector 104 and the output (signal B) of the third latch 117, and then passes the exclusive-or-operated output through the third selector 103 and inputs the exclusive-or-operated output to the input of the first latch in the first D flip-flop 113. In this way, the data of the signal a and the signal B are two PRBS7 data having a phase difference of 180 °, the signal a and the signal B are input to the synthesizer 110, the signal a and the signal B are synthesized by the clock signal, the synthesizer 110 outputs the signal a at the time of the clock rising edge of the synthesizer 110, and the signal B is output at the time of the clock falling edge to form the PRBS7 such that the frequency of the PRBS (PRBS 7 data) output by the synthesizer 110 is twice the frequency of the clock signal. Thus, the PRBS is constructed by the multiplexer, two opposite signals are fed, the latch is used as the shift register, two groups of related data streams are generated by cross exclusive OR, and then the data streams are synthesized into a new PRBS, so that the working frequency of the shift register core is half of the output frequency, and the design difficulty is reduced.

In the embodiment of the invention, the feedback is performed by using the first exclusive-or circuit 107 and the second exclusive-or circuit 108, and the feedback tap is arranged between the D flip-flop and the latch, and because the D flip-flop is composed of two latches, the feedback tap can be arranged between the D flip-flops relative to the feedback tap under the condition of completing the function, and half of the power consumption can be saved. Further, the feedback signal is the output of the second latch 116 and the output of the fifth latch 121, and after performing the cross exclusive-or operation, the outputs of the D flip-flop and the latch are controlled, the outputs of the third latch 117 and the sixth latch 122 are passed through the synthesizer 110, the rising edge is the second signal, the falling edge is the first signal, the data is synthesized as PRBS7 data, and the data period is 1/2 of the original data period.

In the embodiment of the present invention, the operation principle of the PRBS15 and the PRBS31 outputting PRBS is similar to that of the PRBS7, and for the PRBS15, the input of the first exclusive OR gate is the output of the second latch 116 and the output of the sixth latch 122, and the data period is 1/2 of the original data period. For the PRBS31, the input of the first exclusive OR gate is the output of the second D flip-flop 114 and the output of the fourth D flip-flop 119, and the data period of the PRBS31 synthesized and output by the synthesizer 110 is 1/2 of the original data period.

Fig. 8 is a schematic diagram showing another specific structure of a pseudo-random binary sequence generating device according to an embodiment of the present invention. As shown in fig. 8, unlike fig. 7, the first exclusive or circuit in fig. 7 is replaced with a first Nor (Nor) circuit 201 in fig. 8, and the second exclusive or circuit in fig. 7 is replaced with a second Nor circuit 202 in fig. 8, and the other structures are the same and are not repeated here.

In the embodiment of the invention, for the PRBS output by the pseudo-random binary sequence generating device, PRBS verification (PRBS check), namely the reverse process of PRBS generation, is also needed. The PRBS code is performed on the registered data by registering the received data (PRBS) one beat (delay, same as the number of delay cycles that produce the logic) and in parallel with the original data, and the coded data is compared with the latest received data, and if the coded data is consistent, the PRBS check is correct.

Fig. 9 shows a schematic diagram of a specific structure of a pseudo random binary sequence checking device according to an embodiment of the present invention. As shown in fig. 9, the apparatus is applied to verify the pseudo random binary sequence output by the pseudo random binary sequence generating means of fig. 7, and includes: seventeenth D flip-flop 301, first nor circuit 302, eighteenth D flip-flop 303, nineteenth D flip-flop 304, seventh selector 306, ninth latch 310, first buffer 311, second nor circuit 312, third nor circuit 313, second buffer 314, fourth nor circuit 315, tenth latch 318, twenty third D flip-flop 319, fifth nor circuit 320, twenty fourth D flip-flop 321, second fifteen D flip-flop 322, and eleventh selector 324, wherein,

A clock signal (CLK) 326 is input to the seventeenth D flip-flop 301, the twenty-fourth D flip-flop 321, the twenty-fifth D flip-flop 322, and the tenth latch 318, respectively, and an inverted signal of the clock signal is input to the eighteenth D flip-flop 303, the nineteenth D flip-flop 304, the ninth latch 310, and the twenty-third D flip-flop 319, respectively;

seventeenth D flip-flop 301 receives the pseudo-random binary sequence output by the pseudo-random binary sequence generating means, and its output terminal is connected to the first terminal of first nor circuit 302 and first buffer 311, respectively;

the first nor circuit 302 also receives the output of the tenth latch 318, the output being connected to the eighteenth D flip-flop 303;

an output terminal of the eighteenth D flip-flop 303 is connected to the nineteenth D flip-flop 304 and the first terminal of the seventh selector 306, respectively, an output of the nineteenth D flip-flop 304 is connected to a zeroth terminal of the seventh selector 306, and an output terminal of the seventh selector 306 is connected to a first input terminal of the second nor circuit 312;

the signal output from the output of the ninth latch 310 is input to a first input of a fifth nor circuit 320;

the output of the first buffer 311 is connected to a second input of a second nor circuit 312, the output of the second nor circuit 312 being connected to a first input of a third nor circuit 313;

The thirteenth D flip-flop 319 receives the pseudo-random binary sequence output by the pseudo-random binary sequence generating device, and the output end is respectively connected with the second buffer 314, the twenty-third D flip-flop 319 and the fifth nor circuit 320;

an output of the second buffer 314 is connected to a first input of the fourth nor circuit 315, and a signal output from an output of the tenth latch 318 is input to the first nor circuit 302;

the output terminal of the fifth nor circuit 320 is connected to the twenty-fourth D flip-flop 321, the output terminal of the twenty-fourth D flip-flop 321 is connected to the twenty-fifth D flip-flop 322 and the first terminal of the eleventh selector 324, respectively, the output terminal of the twenty-fifth D flip-flop 322 is connected to the zeroth terminal of the eleventh selector 324, the output terminal of the eleventh selector 324 is connected to the second input terminal of the fourth nor circuit 315, the output terminal of the fourth nor circuit 315 is connected to the second input terminal of the third nor circuit 313, and the output terminal of the third nor circuit 313 outputs the verification result.

In an embodiment of the present invention, as an optional embodiment, the verification device further includes:

the inverter 327 receives the pseudo-random binary sequence 328 outputted from the pseudo-random binary sequence generating device, and according to the inputted selection control signal 329, if it is determined that the received pseudo-random binary sequence is subjected to the inversion processing in the transmission process, outputs the received pseudo-random binary sequence to the seventeenth D flip-flop 301 and the twenty-third D flip-flop 319, and if it is determined that the received pseudo-random binary sequence is not subjected to the inversion processing in the transmission process, outputs the received pseudo-random binary sequence to the seventeenth D flip-flop 301 and the twenty-third D flip-flop 319.

In the embodiment of the present invention, 28Gbps data (PRBS) generated by the pseudo-random binary sequence generating device (prbs_gen) is input to the checking device (prbs_chk) circuit after passing through a series of loops, for example, CDR, BUF, etc., and if there is an inverting operation in the data path, the phase of the input signal can be inverted by 180 degrees through the Inverter (INV), and then sampled through the two D flip-flops (seventeenth D flip-flop 301 and twenty third D flip-flop 319). As an alternative embodiment, the sampling clock is a 14G clock signal with opposite directions, the two D flip-flops perform the inverse operation of the synthesizer, restore the data before synthesis, pass through the upper and lower paths respectively, and perform PRBS encoding on the upper and lower paths of data respectively: if the PRBS is generated by adopting a cross exclusive OR mode, the check adopts a cross exclusive OR (NOR) mode, and finally the PRBS is compared with the latest received data (NOR operation), and when the output of the second NOR circuit 312 or the fourth NOR circuit 315 (NOR) is 1, the PRBS data of the PRBS is correctly checked; and finally, performing the exclusive NOR operation on the two paths of NOR outputs again to judge whether the two paths are error-free, and when the third NOR circuit 313 (NOR) output is 1, checking the data of the two paths of output PRBS to be correct.

In the embodiment of the invention, PRBS verification of different code types is realized by changing the on control logic of the selector according to different code types of the PRBS.

In the embodiment of the present invention, if the code pattern of the PRBS is 7 th order, the first end of the seventh selector 306 is connected to the output terminal, the zeroth end of the eighth selector 307 is connected to the output terminal, and the first end of the eleventh selector 324 is connected to the output terminal;

the output of the seventeenth D flip-flop 301 and the output of the tenth latch 318 (the output of the thirteenth D flip-flop 319 to the tenth latch 318) are subjected to nor (nor) operation, and then output to the eighteenth D flip-flop 303 for shifting, and then output to the second nor circuit 312 through the conduction between the first end and the output end (the disconnection between the zeroth end and the output end) of the seventh selector 306, and then compared with the data output by the first Buffer (BUF), so as to determine whether the path of data is erroneous.

The fifth nor circuit 320 performs nor operation on the output of the twenty-third D flip-flop 319 and the output of the ninth latch 310, outputs the result to the twenty-fourth D flip-flop 321 for shifting, and outputs the result to the fourth nor circuit 315 through the conduction between the first end and the output end of the eleventh selector 324, and compares the result with the data output from the second Buffer (BUF) to determine whether the path of data is erroneous. And finally, the results of the two paths of NOR are again or, and no error in both paths indicates no problem in the paths, so that the verification of the pseudo-random binary sequence is realized.

In the embodiment of the present invention, if the code pattern of the PRBS is 15 th order, the zeroth end of the seventh selector 306 is connected to the output end, and the zeroth end of the eleventh selector 324 is connected to the output end;

the output of the seventeenth D flip-flop 301 and the output of the tenth latch 318 (the output of the thirteenth D flip-flop 319 to the tenth latch 318) are subjected to nor (nor) operation, and then are output to the eighteenth D flip-flop 303 and the nineteenth D flip-flop 304 for shifting, and then are output to the second nor circuit 312 through the conduction between the zeroth end and the output end of the seventh selector 306, and are compared with the data output by the first Buffer (BUF), so as to determine whether the path of data is erroneous.

The fifth nor circuit 320 performs nor operation on the output of the twenty-third D flip-flop 319 and the output of the ninth latch 310, and then outputs the result to the twenty-fourth D flip-flop 321 and the twenty-fifth D flip-flop 322 to shift, and then outputs the result to the fourth nor circuit 315 through conduction between the zeroth end and the output end of the eleventh selector 324, and compares the result with the data output from the second Buffer (BUF), thereby determining whether the path of data is erroneous. Finally, the results of the two-way NOR are again exclusive NOR, and no error in both ways indicates no problem in the way.

In the embodiment of the present invention, if the code pattern of the PRBS is 31 th order, the zeroth end and the first end of the seventh selector 306 are disconnected from the output end, and the zeroth end and the first end of the eleventh selector 324 are disconnected from the output end;

after performing nor operation on the output of the seventeenth D flip-flop 301 and the output of the tenth latch 318, the output is sequentially output to the eighteenth D flip-flop 303 and the nineteenth D flip-flop 304 to be shifted respectively, and output to the second nor circuit 312, and compared with the data output from the first Buffer (BUF), so as to determine whether the path of data is erroneous.

The fifth nor circuit 320 performs nor operation on the output of the twenty-third D flip-flop 319 and the output of the ninth latch 310, and then sequentially outputs the result to the twenty-fourth D flip-flop 321 and the twenty-fifth D flip-flop 322, which are respectively shifted, and outputs the result to the fourth nor circuit 315, and compares the result with the data output from the second Buffer (BUF), thereby determining whether the path of data is erroneous. Finally, the results of the two-way NOR are again exclusive NOR, and no error in both ways indicates no problem in the way.

In the embodiment of the invention, the control logic of the verification device is the same as that of the generation device, and the working frequency of the kernel is reduced by adopting a cross exclusive OR mode, so that the design is more convenient.

Fig. 10 is a schematic diagram showing another specific structure of a pseudo random binary sequence checking device according to an embodiment of the present invention. As shown in fig. 10, the apparatus is applied to verify the pseudo random binary sequence outputted from the pseudo random binary sequence generating means of fig. 8, and is different from fig. 9 in that the first nor circuit 302 of fig. 9 is replaced with a first exclusive or circuit 401 of fig. 10, and the fifth nor circuit 320 of fig. 9 is replaced with a second exclusive or circuit 402 of fig. 10, and further includes: twenty-D flip-flop 305, eighth selector 307, twenty-D flip-flop 308, ninth selector 309, twenty-D flip-flop 316, tenth selector 317, twenty-sixth flip-flop 323, twelfth selector 325, wherein,

a clock signal (CLK) 326 is input to the twenty-first D flip-flop 323, and an inverted signal of the clock signal is input to the twenty-second D flip-flop 305;

the seventeenth D flip-flop 301 receives the pseudo-random binary sequence output by the pseudo-random binary sequence generating device, and the output ends thereof are respectively connected with the first ends of the twenty-first D flip-flop 308 and the ninth selector 309;

an output terminal of the seventh selector 306 is connected to a zeroth terminal of the eighth selector 307, and an output terminal of the eighth selector 307 is connected to a first input terminal of the second nor circuit 312;

An output terminal of the twenty-fifth D flip-flop 322 is connected to the twenty-sixth D flip-flop 323, an output terminal of the twenty-sixth D flip-flop 323 is connected to a first terminal of the twelfth selector 325, an output terminal of the eleventh selector 324 is connected to a zeroth terminal of the twelfth selector 325, and an output terminal of the twelfth selector 325 is connected to a second input terminal of the fourth nor circuit 315;

an output terminal of the twenty-first D flip-flop 308 is connected to a zeroth terminal of the ninth selector 309, and an output terminal of the ninth selector 309 is connected to a ninth latch 310;

an output terminal of the twenty-second D flip-flop 316 is connected to a zeroth terminal of the tenth selector 317, an output terminal of the tenth selector 317 is connected to a tenth latch 318, and a signal output from the output terminal of the tenth latch 318 is input to the first nor circuit 302.

The other structures are the same and will not be described in detail herein.

In the embodiments provided herein, it should be understood that the disclosed systems and methods may be implemented in other ways. The system embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions in actual implementation, and e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, system or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments provided in the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

It should be noted that: like reference numerals and letters in the following figures denote like items, and thus once an item is defined in one figure, no further definition or explanation of it is required in the following figures, and furthermore, the terms "first," "second," "third," etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.

Finally, it should be noted that: the foregoing examples are merely illustrative of specific embodiments of the present application, and are not intended to limit the scope of the present application, although the present application is described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or make equivalent substitutions for some of the technical features within the technical scope of the disclosure of the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the corresponding technical solutions. Are intended to be encompassed within the scope of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A pseudo-random binary sequence generating device, comprising:

the clock signal circuit is used for generating a clock signal, inputting the clock signal into the data synthesizer and synchronously and inversely inputting clock signal input ends of the two groups of shift register circuits;

the two input ends of the data synthesizer are respectively connected with the outputs of the two groups of shift register circuits to receive the PRBS data, and the n-order PRBS sequence based on half clock signal frequency is output according to the clock signal;

the control circuit is used for controlling the shift register circuit and the clock signal circuit;

each set of the shift register circuits includes: the device comprises a first latch, a second latch, a third latch, a first D trigger module, 1 first selector and 1 logic gate circuit which are connected in sequence, wherein the first D trigger module comprises (n-3)/2 first D triggers which are connected in sequence;

The initial value is subjected to shift coding through the first D trigger module, the third latch, the second latch and the first latch in sequence, and then the PRBS data is output;

the two input ends of the logic gate circuit are respectively connected with the output end of the first selector and the output end of the other group of shift register circuits which are symmetrically arranged, and the output end of the logic gate circuit is connected with the input end of the first D trigger module.

2. The generating device of claim 1, wherein the logic gate is an exclusive or gate or an exclusive or gate.

3. The generating device of claim 1, wherein n is 7 or 9 or 11 or 15 or 21 or 23 or 31.

4. The generating device according to claim 1, wherein the clock signals are input to the clock signal input terminals of the first D flip-flop and the respective latches in the two sets of shift register circuits in synchronous inversion, and the input clock signals of the first and third latches in each set of shift register circuits are input to the second and first D flip-flops in synchronous inversion.

5. The generating device of claim 1, wherein each group of shift register circuits further comprises 1 second selector and second D flip-flop modules forming an m-stage PRBS generator for generating 2 ^m -a PRBS sequence of bits 1, where m is an integer greater than n, the second D flip-flop module comprising (m-n)/2 sequentially connected second D flip-flops;

the logic gate circuit is connected with the input end of the first D flip-flop module through the second selector: one input end of the second selector is connected with the output end of the logic gate circuit, and the output end of the second selector is connected with the input end of the first D trigger module;

6. The generating device of claim 5, wherein n is 7 or 9 or 11 or 15 or 21 or 23 and m is 11 or 15 or 21 or 23 or 31.

7. The generating apparatus of claim 5, wherein each set of shift register circuits further comprises 1 third selector and third D flip-flop modules forming an r-stage PRBS generator for generating 2 ^r -a PRBS sequence of bits 1, where r is an integer greater than m, the third D flip-flop module comprising (m-n)/2 sequentially connected third D flip-flops;

the logic gate circuit is connected with the input end of the second D flip-flop module through the third selector: one input end of the third selector is connected with the output end of the logic gate circuit, and the output end of the third selector is connected with the input end of the second D trigger module;

8. The generating device of claim 7, wherein n is 7 or 9 or 11 or 15, m is 11 or 15 or 21 or 23, and r is 15 or 21 or 23 or 31.

9. A PRBS data generating method, characterized by applying the generating device according to claim 5 or 7, comprising the steps of:

s1, the control circuit receives PRBS sequence generation indication information and controls two groups of shift register circuits to reset to a preset value;

s2, the control circuit controls the PRBS generator of the corresponding order to be started according to the indication information to obtain a target PRBS sequence, and the method comprises the following steps:

Controlling the conduction of the n-order PRBS generator and other corresponding trigger modules and selectors;

controlling the clock signal circuit to generate a clock signal, and inputting the clock signal into two groups of shift register circuits in synchronous and opposite phases to obtain final outputs A and B respectively;

A. b, inputting the clock signal into the data synthesizer;

10. A pseudo-random binary sequence PRBS verification device, applied to verifying a PRBS sequence generated by the generating device according to any one of claims 1 to 8, and comprising 2 groups of second shift register circuits, 2 groups of delay circuits, 2 second logic gates, a second clock signal circuit, a second control circuit, and 1 third logic gate that are symmetrically arranged;

each group of the second shift register circuits is used for encoding the received PRBS data and transmitting the encoding results to 2 second logic gate circuits respectively;

Each second logic gate circuit is used for carrying out logic operation on the received coding result and the delay result, and transmitting the operation result to a counting third logic gate circuit respectively;

11. The pseudo-random binary sequence PRBS verification device according to claim 10, wherein each set of said second shift register circuits comprises, in sequence:

a fourth D flip-flop;

a fourth logic gate circuit, wherein the logic operations of the fourth logic gate circuit and the logic gate circuit of the generating device are mutually non-operation;

the sixth D trigger module comprises (m-n)/2 sixth D triggers which are connected in sequence; m is an integer greater than n;

the latch circuit comprises a fourth latch, the input end of the fourth latch is connected with the output end of the fourth D trigger, and the output end of the fourth latch is connected with one input end of the second logic gate circuit of the other group of second shift register circuits;

two input ends of the second logic gate circuit are respectively connected with the delay circuit and the output end of the fourth selector;

and two input ends of the third logic gate circuit are respectively connected with output ends of the two second logic gate circuits.

12. The pseudo-random binary sequence PRBS verification device according to claim 10, wherein each set of said second shift register circuits comprises, in sequence:

a seventh D flip-flop;

A ninth D trigger module comprising (m-n)/2 ninth D triggers connected in sequence; m is an integer greater than n;

a tenth D trigger module comprising (r-m-2)/2 tenth D triggers connected in sequence; r is an integer greater than m;

and a fifth selector, wherein two input ends are respectively connected with the output ends of the eighth D trigger module and the ninth D trigger module;

the latch circuit comprises a sixth selector, wherein two input ends are respectively connected with the output end of the seventh D trigger through an eleventh D trigger; a fifth latch, an input terminal of which is connected to an output terminal of the sixth selector, and an output terminal of which is connected to one input terminal of the eighth logic gate circuit of the other group of the second shift register circuits;

two input ends of the second logic gate circuit are respectively connected with the delay circuit and the output end of the seventh selector;

and two input ends of the third logic gate circuit are respectively connected with output ends of the two second logic gate circuits, and the output of the third logic gate circuit is used for representing whether the PRBS sequence is correct or not.

13. A pseudo-random binary sequence PRBS verification device according to claim 10 and further comprising an inverter through which PRBS data passes into the shift register circuit.