CN116136827A

CN116136827A - Multi-port storage device, read-write method and device

Info

Publication number: CN116136827A
Application number: CN202111362170.0A
Authority: CN
Inventors: 段光生; 许俊; 夏杰
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2021-11-17
Filing date: 2021-11-17
Publication date: 2023-05-19

Abstract

The invention discloses a multi-port storage device, a read-write method and a device, wherein the device comprises the following components: n+1 memory banks, a write operation control unit, a read operation control unit, and a memory map; each memory bank includes: CEILING (M/2) pseudo dual-port two-read memories; m is the number of read ports; the N is the number of write ports; said blocking represents rounding up; the pseudo dual-port two-read memory is used for executing at least one of read operation, write operation and read-write operation; the storage mapping table is used for recording the storage mapping relation between the data and the storage address according to the storage information of the write-in data corresponding to the write operation; the write operation control unit is used for controlling and managing the write operation of the pseudo double-port two-read memory; the read operation control unit is used for controlling and managing the read operation of the pseudo double-port two-read memory.

Description

Multi-port storage device, read-write method and device

Technical Field

The present invention relates to chip design technologies, and in particular, to a multi-port memory device, a read-write method, and an apparatus.

Background

In ASIC (Application Specific Integrated Circuit ) designs, memories such as SRAM (Static Random Access Memory, static random access memory), eDRAM (Enhanced Dynamic Random Access Memory ) and the like are commonly used, and for special chips in some fields such as network switching fields, the total area of the memory is up to or even more than half of the total area of the chip, and it is seen that the design advantages and disadvantages of the memories have a significant effect on the total area of the chip. The memory may be classified into a single-port memory, a pseudo dual-port/dual-port memory, and a multi-port memory according to the access ports. For a multi-port memory, when the capacity of the memory is very small, the memory can be directly realized by a register unit, but when the capacity is very large, the register unit is still adopted to realize the memory, so that a series of problems, such as large area and power consumption, particularly large number of logic units, serious winding congestion and the like, are caused, and finally, the realization result is difficult to reach the expected index or cannot be realized at all. For a large-capacity multi-port memory, the other implementation mode is realized by a pseudo dual-port static memory, and the pseudo dual-port memory is adopted to effectively reduce the area, the power consumption and the number of logic units and the winding congestion degree, so that the design of the multi-port memory finally reaches the expected index requirement.

In the scheme provided by the prior art, the number of the pseudo double-port memory units is too large, so that the area of the realized multi-port memory is large, and the power consumption is high.

Disclosure of Invention

In order to solve the existing technical problems, the embodiment of the invention provides a multi-port storage device, a read-write method and a device.

The technical scheme of the invention is realized as follows:

the embodiment of the invention provides a multi-port storage device, which comprises: n+1 memory banks, a write operation control unit, a read operation control unit, and a memory map; each memory bank includes: CEILING (M/2) pseudo dual-port two-read memories; m is the number of read ports; the N is the number of write ports; said blocking represents rounding up;

the pseudo dual-port two-read memory is used for executing at least one of read operation, write operation and read-write operation;

the storage mapping table is used for recording the storage mapping relation between the data and the storage address according to the storage information of the write-in data corresponding to the write operation;

the write operation control unit is used for controlling and managing the write operation of the pseudo double-port two-read memory;

the read operation control unit is used for controlling and managing the read operation of the pseudo double-port two-read memory.

In the above scheme, the pseudo dual-port two-read memory has a first port and a second port; the first port is a read port; the second port is a read port or a write port.

In the above scheme, the capacity of the storage mapping table is W (blocking (LOG) ₂ (celing (M/2) × (n+1) -1))) bits;

wherein, W is the depth of a single pseudo double-port two-read memory.

The embodiment of the invention provides a read-write method of multi-port storage equipment, which is applied to any multi-port storage equipment; the method comprises the following steps:

receiving a target operation; the target operation includes at least one of: writing operation, reading operation and reading and writing operation;

determining a pseudo dual-port two-read memory for executing the target operation according to the memory mapping table;

and executing target operation through the determined pseudo double-port two-read memory.

In the above scheme, the target operation is a write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

reading the storage mapping table according to the write address corresponding to the write operation, and calculating the number of write operations of each group of memory groups;

the write operation corresponding to any memory group does not exceed 1, write the write data back to the original memory group, and does not update the memory mapping table;

corresponding to the fact that the writing operation of any memory group exceeds 1, all the writing operations to be performed are numbered according to the sequence from small to large for different memory groups, the operation with the writing operation number being the target number is written back to the original memory group, the operation with the writing operation number being larger than the target number is written into the memory group without the writing operation, and the storage mapping table is updated.

In the above scheme, the target operation is a read operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

selecting a memory group with effective read data according to the memory mapping table;

and according to the read address corresponding to the read operation, selecting a pseudo dual-port two-read memory for executing the target operation in the selected memory group and determining a corresponding port so as to execute the read operation.

In the above scheme, the target operation is a simultaneous read-write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

selecting a memory group with effective read data according to the memory mapping table aiming at the read operation of the simultaneous read-write operation;

aiming at the write operation of the simultaneous read-write operation, reading the storage zone bit information of the storage mapping table according to a read address, and calculating the number of read operations of each memory group;

determining that no read operation of any memory group exceeds CEILING (M/2), and executing preset write operation to write data;

otherwise, marking the memory group with the number of read operations exceeding CEILING (M/2) as a write operation invalid memory group, wherein the invalid memory group cannot execute write operation; and executing preset write operation according to the other memory groups except the invalid memory group so as to write data.

In the above solution, the preset writing operation includes:

reading the storage mapping table according to a write address corresponding to the write operation, and calculating the number of write operations of each group of memory groups;

The embodiment of the invention provides a read-write device of a multi-port storage device, wherein the multi-port storage device is any one of the multi-port storage devices; the device comprises:

the receiving module is used for receiving the target operation; the target operation includes at least one of: writing operation, reading operation and reading and writing operation;

the processing module is used for determining a pseudo double-port two-read memory for executing the target operation according to a memory mapping table;

The embodiment of the invention provides a multi-port storage device, a read-write method and a device, wherein the device comprises the following components: n+1 memory banks, a write operation control unit, a read operation control unit, and a memory map; each memory bank includes: CEILING (M/2) pseudo dual-port two-read memories; m is the number of read ports; the N is the number of write ports; said blocking represents rounding up; the pseudo dual-port two-read memory is used for executing at least one of read operation, write operation and read-write operation; the storage mapping table is used for recording the storage mapping relation between the data and the storage address according to the storage information of the write-in data corresponding to the write operation; the write operation control unit is used for controlling and managing the write operation of the pseudo double-port two-read memory; the read operation control unit is used for controlling and managing the read operation of the pseudo double-port two-read memory. Therefore, the chip area can be effectively reduced, the chip power consumption can be reduced, the chip cost can be reduced, and the product competitiveness can be improved by using fewer memories.

Drawings

FIG. 1 is a schematic diagram of a pseudo dual port memory;

FIG. 2 is a schematic diagram of an implementation of a pseudo dual port memory;

FIG. 3 is a schematic diagram of a pseudo dual-port two-read memory model according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a multi-port memory device based on a pseudo dual-port two-read memory according to an embodiment of the present invention;

fig. 5 is a schematic flow chart of a read-write method of a multi-port storage device according to an embodiment of the present invention;

FIG. 6 is a flowchart of a read-write operation of a multi-port memory device according to an embodiment of the present invention;

FIG. 7 is a flow chart of a read-only operation of a multi-port memory device according to an embodiment of the present invention;

FIG. 8 is a flowchart of a write-only operation of a multi-port memory device according to an embodiment of the present invention;

FIG. 9 is a flowchart of a read-while-write operation of a multi-port memory device according to an embodiment of the present invention;

FIG. 10 is a flowchart of a write-while-read operation of a multi-port memory device according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a design architecture for implementing a three-read three-write memory device based on a pseudo dual-port two-read memory according to an embodiment of the present invention;

fig. 12 is a schematic diagram of area comparison of a multi-port memory device for implementing odd read ports in a pseudo dual-port two-read memory and a normal pseudo dual-port memory according to an embodiment of the present invention.

Detailed Description

The related art will be described before the present invention will be described in further detail with reference to examples.

In the related art, a pseudo dual-port memory is provided, as shown in fig. 1, fig. 1 is a model of a conventional pseudo dual-port memory, and the memory model supports read-write operations of at most two ports simultaneously, wherein a port 1 is fixed as a read port, and a port 2 is fixed as a write port.

Fig. 2 is a specific implementation manner of a conventional pseudo dual-port memory, and the scheme is as follows: for a multi-port memory with capacity w×b for M read ports and N write ports, the multi-port memory can be implemented by m×n normal pseudo-dual-port memories with capacity w×b, and a multi-port memory with capacity w×ng (LOG) ₂ N)) of the memory map; CEILING represents rounding up. However, the above scheme uses too many pseudo dual-port memory cells, resulting in large area and high power consumption of the realized multi-port memory.

The ASIC design requires a large capacity of multiple read-multiple write memory, and if implemented by the above scheme, the area and power consumption are still large. Based on the above, the embodiment of the invention provides a novel pseudo-dual-port two-read memory for realizing a multi-port memory, which can obviously reduce the area and power consumption compared with the prior art. The number of ports of the novel pseudo-double-port two-read memory is the same as that of ports of a common pseudo-double-port memory, the density and the performance are similar, but the ports of the pseudo-double-port two-read memory are more flexible to use.

The present invention will be described in further detail with reference to examples.

Fig. 3 is a schematic diagram of a pseudo dual-port two-read memory model provided in an embodiment of the present invention, as shown in fig. 3, a port 1 of the pseudo dual-port two-read memory is fixed as a read port, and a port 2 may be selected to be used as a read port or a write port (as shown in a read/write enable 2 in fig. 3), or may be selected according to a requirement.

The multi-port memory realized based on the novel pseudo-dual-port two-read memory uses less memory quantity under the condition of reaching the same bandwidth, thereby effectively reducing the chip area, reducing the chip power consumption, reducing the chip cost and improving the product competitiveness.

If the depth of the multi-port memory device to be implemented is W, the width is B, the number of read ports is M, and the number of write ports is N, the total number of the required pseudo-dual-port two-read memories is CEILING (M/2) ×n+1 (CEILING represents rounding up), and the depth of a single pseudo-dual-port two-read memory is W, and the width is B. The pseudo-dual-port two-read memories are divided into N+1 groups, the number of the memories in each group is CEILING (M/2), and the numbers of the memories in the N+1 groups are #0, #1 and … # N.

In addition, a memory map (SMT, storage Mapping Table) is required to indicate which memory bank the valid data of each address is stored in, and the capacity of the memory map is W (LOG 2 (n+1))bit.

FIG. 4 is a schematic diagram of a multi-port memory device based on a pseudo dual-port two-read memory according to an embodiment of the present invention; as shown in fig. 4, the multi-port memory device includes:

CEILING (M/2) (n+1) pseudo dual-port two-read memory, write operation control unit, read operation control unit, and memory map.

The initialization state of the memory mapping table is zero, and when data is written into the memory group, the corresponding memory group number is updated to the write address corresponding to the memory mapping table.

Wherein M is the number of read ports; the N is the number of write ports; the CEILING represents a round-up.

Grouping the pseudo-dual port two-read memory, that is, the multi-port memory device includes:

n+1 memory banks, a write operation control unit, a read operation control unit, and a memory map; each memory bank includes: CEILING (M/2) pseudo dual-port two-read memories;

m is the number of read ports; the N is the number of write ports; said blocking represents rounding up;

The pseudo dual-port two-read memory is provided with a first port and a second port; the first port is a read port; the second port is a read port or a write port.

The memory map has a capacity of W (LOG ₂ (celing (M/2) × (n+1) -1))) bits; wherein, W is the depth of a single pseudo double-port two-read memory.

The embodiment of the invention also provides a read-write method of the multi-port memory device, which is applied to the multi-port memory device; as shown in fig. 5, the method includes:

step 501, receiving a target operation; the target operation includes at least one of: writing operation, reading operation and reading and writing operation;

step 502, determining a pseudo dual-port two-read memory for executing the target operation according to the memory mapping table;

and step 503, executing target operation through the determined pseudo dual-port two-read memory.

In one embodiment, the target operation is a write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

The original memory group refers to a memory group corresponding to the writing operation, namely, the memory group number to which each writing address is expected to be written; determined by user operation;

the target number refers to the minimum number, generally designated 0#.

In one embodiment, the target operation is a read operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

selecting a memory group with effective read data according to the memory mapping table; i.e., determining a memory bank in which reading data can be performed;

In an embodiment, the target operation is a simultaneous read-write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

Wherein the preset write operation includes:

corresponding to the fact that the writing operation of any memory group exceeds 1, all the writing operations to be performed are numbered in the sequence from small to large for different memory groups, the operation with the writing operation number being the target number (the minimum number, namely 0#) is written back to the original memory group, the operation with the writing operation number being larger than the target number is written into the memory group without the writing operation, and the storage mapping table is updated.

The above updating of the memory map and the querying of the memory map may be performed by the write operation control unit, the read operation control unit, or may be performed by a control module provided in the multi-port memory device.

For further description of the multi-port storage device and the corresponding method, the following three cases are used to describe the read-write mode of the multi-port storage device:

case 1, only write operation. As shown in figure 7 of the drawings,

assuming that N (N < = N) write ports perform write operations at the same time, searching corresponding data storage information in a storage mapping table according to a write address of each write port to obtain a memory group number to which each write address is expected to be written, calculating the number of write operations to be performed by each memory group, and dividing two situations according to the calculated number of write operations:

if any memory group has only one write operation at most, for the y (y < N) th write address, if the memory group number read from the memory mapping table is z (z < N), the data is written into all pseudo dual-port two-read memories in the z-th memory group, and the storage flag bit corresponding to the write address is not updated.

The number of the write operations of one or more memory groups is more than one, firstly, all memory groups without write operations are found out from the N+1 memory groups, the numbers of the memory groups without write operations are recorded and stored into D0, D1, … D i respectively; since there are at most N write ports, i.e. all write operations add up to at most N, and there are a total of n+1 memory banks, i.e. it must be guaranteed that there is at least one free memory bank to perform a write operation. For a certain memory bank, if the number of write operations to be performed is greater than one, these write operations are denoted as W [0], W [1], … W [ j ], respectively. Writing W [0] write data into the current memory bank, writing W [1] into the D [0] memory bank, and writing D [0] into an address corresponding to W [1] in the memory mapping table, and similarly writing W [ j ] write operation into the free memory bank D [ j-1], wherein j-1< = i, and writing D [ j-1] into an address corresponding to W [ j ] in the memory mapping table.

In case 2, only in the read operation, as shown in figure 8,

it is assumed that M (M < = M) read ports perform a read operation at the same time, corresponding storage flag bit information is searched in a storage mapping table according to each read address, which memory group each read address goes to read data is obtained according to the read information, and meanwhile, a plurality of read addresses in each memory group can be calculated to read data.

Assuming that a certain memory bank has X (X < =m) read addresses to read data, the data is read from the xth (X > =0) of the memory bank to the MOD (X, (M/2)) (MOD represents a remainder operation) of the pseudo-dual-port two-read memory (X/(M/2))) (INT represents a rounding down operation) port of the memory bank.

Because each memory bank has the reading ports of (M/2) ×2> =m, and the data corresponding to the same address in each memory bank is the same, that is, at least M read operands can be supported by any address, and in fact, the read operation of any address will not exceed the maximum port number M, so that it can be ensured that any read address can read correct data from the corresponding read port of the pseudo dual-port two-read memory.

3, when read-write operation is performed simultaneously; as shown in the figure 9 of the drawings,

it is assumed that M (M < =m) read ports perform read operation and N (N < =n) write ports perform write operation at the same time, corresponding memory mapping information is searched in a memory mapping table according to each read address and each write address, and according to the read memory mapping information, the ith (i < =n) memory group is calculated to have X [ i ] read addresses to read data and Y [ i ] write addresses to write data.

The read operation and the write operation are described below, respectively:

for a read operation, as in the read-only method, when the read operation is performed on the ith memory bank, the xth read address in the xth read operation reads the MOD (X, (M/2)) (MOD represents a remainder operation) of the mth (X/(CEILING (M/2))) port of the pseudo-dual-port two-read memory, and INT represents a rounding down operation).

For the write operation, xmax=max (X [0], X [1], … X [ N ])=xa ] (MAX represents the maximum value among all elements) needs to be further calculated based on X [ i ] information (X [ i ] represents the number of read operations that the ith memory bank needs to perform). Two cases are:

a) If xmax=x [ a ] > verify (M/2), then the a-th memory cannot be rewritten at this time, and the a-th memory is referred to as a write operation illegal memory bank.

Since SUM (X0, X1, … X N) is less than M (SUM represents a SUM of all elements), and xmax=x [ a ] > CEILING (M/2), X [ i ] (i+.a) =ceiling (M/2), i.e., the number of read operations of the N-bank memories other than bank a does not exceed CEILING (M/2), i.e., the banks other than bank a can perform write operations.

According to the storage zone bit information of all the writing addresses, all the expected storage group information to be written can be obtained, the storage group which does not need writing operation, namely the number of the writing operation free storage is stored in a free storage number queue, and if the free storage number queue contains the number a of the writing operation illegal storage group, the number a is deleted from the free storage number queue. And carrying out write operation in sequence according to the write address and the storage identification information, if the memory group to be written is the illegal memory group a of the write operation, writing the data to be written into the memory group a into a certain write operation free memory group, and writing the free memory group number into the write address corresponding to the storage mapping table. If the memory group to be written is not the write-operation illegitimate memory group a, the write operation is performed according to the flow of only the write operation.

B) If xmax=x [ a ] <=verify (M/2), then no illegal memory group a exists for writing, and then writing is performed according to the flow of writing only.

In the following, a multi-port memory with 2048 depths (w=2048) and 32 bit widths (b=32) is specifically described how to implement a multi-port memory based on a pseudo dual-port two-read memory, taking as an example the implementation of one four-read (m=4) four-write (n=4). Fig. 3 is a schematic diagram of a design architecture for implementing a four-read four-write memory based on a pseudo dual-port two-read memory.

To realize the four-read four-write memory, the number of the required pseudo dual-port two-read memories is CEILING (M/2) × (n+1) =CEILING (4/2) × (4+1) =10, and the depth width of the single pseudo dual-port two-read memory is the same as that of the multi-port memory, i.e. the depth of the single pseudo dual-port two-read memory is 2048 and the width is 32. The number of bits of the memory map is W (CEILING (LOG 2 (n+1))) =2048 (CEILING (LOG 2 (4+1))) =6144, and all the initial values of bits of the memory map (Storage Mapping Table, abbreviated SMT) are 0.

The 10 pseudo dual-port two-read memories are divided into n+1=5 groups, and are numbered #0, # … #4, and each group of memories comprises pseudo dual-port memory cells of CEILING (M/2) =2, and are numbered #0, #1.

Step 001, simultaneously writing address 0, address 1, address 2 and address 3, firstly reading the values of SMT [0] to SMT [3] to 3'b000, namely writing 4 writing operation data into a memory group #0, determining that the free memory groups for writing operation at the moment are #1, #2, #3 and #4, writing the writing data corresponding to the writing address 0 into two pseudo double-port two-read memories in the memory group #0, and updating SMT [0] = 3' h0; the data corresponding to the other writing addresses are sequentially written into the writing idle memory group, that is, address 1, address 2 and address 3 are written into the memory groups #1, #2 and #3 respectively, and the memory mapping tables SMT [1] =3 ' h1, SMT [2] =3 ' h2, SMT [3] =3 ' h3 are updated.

Step 002, simultaneously reading address 0, reading address 1, reading address 2 and reading address 3, writing address 4, writing address 5, writing address 6 and writing address 7;

reading the memory mapping table according to the read address, and obtaining SMT [0] =3 'h0, SMT [1] =3' h1, SMT [2] =3 'h2, SMT [3] =3' h3, that is, the memory banks #0 to #3 have only one read operation respectively, the data of the address 0 should be obtained from the memory bank #0, specifically, the data is read from the memory bank #0 to the MOD (x, (blocking (M/2))) =mod (0, 2) =0 of the INT (x/(blocking (M/2))) =int (0/2) =0 of the pseudo dual-port two-read memory. Addresses 1-3 may also access corresponding memory cells in a similar manner.

Since the number of read operands of any one set of memories is only 1 and is not greater than CEILING (M/2) =2, no illegal memory set is written, and the writing operation at this time is processed according to the case of writing only. I.e. address 4, address 5, address 6 and address 6 are written to memory banks #0, #1, #2 and #3, respectively, and the memory map table SMT [4] =3 'h0, SMT [5] =3' h1, SMT [6] =3 'h2, SMT [7] =3' h3 is updated.

Step 003, write address 8, address 9, address 10 and address 11, the operation is similar to step 001.

Step 004, write address 12, address 13, address 14 and address 15, the operation is similar to step 001.

Step 005, read address 0,4,8,12, write address 1,3,16,17; according to the memory mapping table, SMT [0] =smt [4] =smt [8] =smt [12] =3' h0, i.e. all the 4 addresses need to access the memory register group #0, the read addresses 0,4,8,12 are respectively numbered as read operations 0,1,2,3, then the read address 0 is to be read from MOD (x, (CEILING (M/2))) =mod (0, 2) =0 of the pseudo-dual-port two-read memory, INT (x/(CEILING (M/2))) =int (0/2) =0 of the read port read data, the address 4 is to be read from MOD (1, 2) =0 of the pseudo-dual-port two-read memory of the memory group #0, the address 8 is to be read from MOD (2, 2) =0 of the pseudo-dual-port two-read memory of the memory group #0, the address 8 is to be read from INT (3/2) =1 of the pseudo-dual-port two-read memory of the pseudo-port two-read memory of the pseudo-0, and the address 12 is to be read from MOD (1, 2) =1 of the pseudo-port two-read memory of the pseudo-port of the memory of the pseudo-0; since the number of read operations of the memory bank #0 is 4> CEILING (M/2) =2, the memory bank #0 is now an illegitimate memory bank for write operations.

According to the memory map table, SMT [1] =3 ' h1, SMT [3] =3 ' h3, SMT [16] =smt [17] =5 ' h0, the free memory banks for write operations are #2 and #4; data of address 1 and address 3 are written to memory banks #1 and #3, respectively, without updating the memory map.

Address 16 and address 17 were originally written to memory bank #0, but memory bank #0 is a write operation illegal memory, it is necessary to write the data of addresses 16 and 17 to free memory banks #2 and #4, respectively, and update the memory map table SMT [16] =3 'h2, SMT [17] =3' h4.

Other operations for a four read four write memory may also occur similar to the operations described above.

FIG. 12 is a schematic diagram showing the area comparison of a multi-port memory device for realizing odd read ports between a pseudo dual-port two-read memory and a normal pseudo dual-port memory according to an embodiment of the present invention; based on the TSMC 7nm technology, the memory developed by Synopsys corporation is evaluated, wherein the pseudo double-port common memory is a double-port high-speed ultra-high-density memory provided by Synopsys corporation, and the pseudo double-port two-read memory is a pseudo double-port two-read memory provided by Synopsys corporation. As can be seen from the following table, the more the number of ports of the multi-port memory is, the higher the area ratio of the memory is saved, and for the six-read and six-write memory, the total area saved is up to 55%, and when the bandwidths are the same, the reduction of the area and the number of the memory obviously also brings about the reduction of the power consumption. It can be seen that the area saving is more when the number of read ports of the multi-port memory is even than when the number of read ports is odd, which is reasonable because each pseudo dual-port two-read memory has two read ports, if the total number of read ports is odd, one of the read ports of one pseudo dual-port two-read memory in each group of memories is wasted, and when the total number of read ports is even, no ports are wasted.

The embodiment of the invention also provides a structural schematic diagram of the data processing device; the device comprises:

the processing module is used for determining a pseudo dual-port two-read memory for executing the target operation according to the memory mapping table; and executing target operation through the determined pseudo double-port two-read memory.

The apparatus may also implement other steps in the method shown in fig. 5, which are not described in detail herein.

The embodiment of the invention also provides electronic equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor; the method provided by one or more of the above technical solutions is implemented when the processor located in the electronic device executes the program.

The method disclosed in the embodiments of the present application may be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities.

Embodiments of the present application also provide a storage medium, particularly a computer storage medium, and more particularly a computer readable storage medium. On which computer instructions, i.e. computer programs, are stored; the computer instructions, when executed by a processor, provide a method of one or more of the above-described aspects.

In several embodiments provided in the present application, it should be understood that the disclosed method and intelligent device may be implemented in other manners. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

In addition, the embodiments described in the present application may be arbitrarily combined without any collision.

The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.

Claims

1. A multi-port memory device, the device comprising: n+1 memory banks, a write operation control unit, a read operation control unit, and a memory map; each memory bank includes: CEILING (M/2) pseudo dual-port two-read memories; m is the number of read ports; the N is the number of write ports; said blocking represents rounding up;

2. The apparatus of claim 1, wherein the pseudo dual port two read memory has a first port and a second port; the first port is a read port; the second port is a read port or a write port.

3. The apparatus according to claim 1 or 2, wherein the capacity of the memory map is W (LOG ₂ (celing (M/2) × (n+1) -1))) bits;

wherein, W is the depth of a single pseudo double-port two-read memory.

4. A method for reading from and writing to a multi-port memory device, characterized by being applied to the multi-port memory device of any one of claims 1 to 3; the method comprises the following steps:

5. The method of claim 4, wherein the target operation is a write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

6. The method of claim 4, wherein the target operation is a read operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

7. The method of claim 4, wherein the target operation is a simultaneous read and write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

8. The method of claim 7, wherein the target operation is a simultaneous read and write operation; the determining, according to the memory mapping table, a pseudo dual-port two-read memory for executing the target operation includes:

9. The method of claim 8, wherein the preset write operation comprises:

10. A read-write apparatus of a multi-port memory device, wherein the multi-port memory device is the multi-port memory device according to any one of claims 1 to 3; the device comprises: