CN115528085A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate; the gate structure is positioned on the substrate, and the source drain doping layers are positioned in the substrate on two sides of the gate structure; the first conductive structure is positioned on the source drain doping layer, and the second conductive structure is positioned on the grid structure; a first filling opening exposing sidewalls of the first conductive structure and the gate structure; and the first filling layer is positioned in the first filling opening and is internally provided with a first air gap. Because no other filling materials are arranged between the first conductive structure and the grid structure, the first filling layer has a larger filling space, and a cavity of a first air gap in the first filling layer is larger. When the cavity of the first air gap is larger, the dielectric constant between the first conductive structure and the gate structure is smaller, so that the parasitic capacitance between the first conductive structure and the gate structure is smaller, and the performance of the finally formed semiconductor structure is improved.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. For example, flash memory is used as a storage device in electronic devices such as digital cameras, notebook computers or tablet computers. Therefore, reducing the size of the flash memory unit and thereby reducing the cost of the flash memory is one of the directions of technological development. For the NOR gate electrically erasable tunnel oxide flash memory, a self-aligned electrical contact (Self-Align Contact) process can be used to manufacture the conductive structure on the surface of the source region and the drain region, so as to meet the requirements of making smaller sized flash memory requirements.

However, the performance of the semiconductor structure formed by the self-aligned electrical contact process in the prior art still needs to be improved.

Contents of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and its forming method, which can effectively improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate includes a base and fins on the base; an isolation layer on the substrate, the isolation layer covers the Part of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; a gate structure on the substrate, the gate structure straddles the fin; Source-drain doped layers in the fins on both sides of the gate structure; a first conductive structure and a second conductive structure, the first conductive structure is located on the source-drain doped layer, and the second conductive structure Located on the gate structure; a first filling opening exposing sidewalls of the first conductive structure and the gate structure; a first filling layer located in the first filling opening , there is a first air gap in the first filling layer.

Optionally, further comprising: a first dielectric layer, the first dielectric layer covers the sidewall of the gate structure, and the first filling opening is located between the first dielectric layer and the gate structure .

Optionally, further comprising: a second dielectric layer located on the first dielectric layer, the second dielectric layer covers the first conductive structure and the second conductive structure, and the second dielectric layer exposes The top surfaces of the first conductive structure and the second conductive structure are exposed.

Optionally, further comprising: a first side wall located on the side wall of the gate structure.

Optionally, the first conductive structure includes: a first conductive plug located on the source-drain doped layer, and a first conductive layer located on the first conductive plug.

Optionally, the gate structure includes: a gate dielectric layer, and a gate layer on the gate dielectric layer; the gate structure includes several first regions, and a first region between the first regions. In the second region, the source-drain doped layer is located on both sides of the second region, and the second conductive structure is located on the second region.

Optionally, further comprising: a second filling opening, the second filling opening communicates with the first filling opening, the second filling opening is located between the first conductive structure and the second conductive structure, And the second filling opening exposes sidewalls of the first conductive structure and the second conductive structure.

Optionally, further comprising: the second filling layer located in the second filling opening, the second filling layer having a second air gap.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base and fins on the base; forming an isolation structure on the substrate layer, the isolation layer covers part of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; forming a gate structure and several source and drain doped layers, the gate The structure spans the fin, and the sidewall of the gate structure has a sacrificial sidewall, and the source-drain doped layer is located in the fin on both sides of the gate structure; forming a first conductive structure and a second conductive structure structure, the first conductive structure is located on the source-drain doped layer, and the second conductive structure is located on the gate structure; removing the sacrificial spacer exposes the first conductive structure and the gate The sidewall of the pole structure forms a first filling opening; a first filling layer is formed in the first filling opening, and a first air gap is formed in the first filling layer.

Optionally, the method for forming the gate structure and the source-drain doped layer includes: forming a dummy gate structure on the substrate; forming a sidewall structure on the sidewall of the dummy gate structure; The gate structure and the sidewall structure are used as a mask to etch the fin, and a source-drain opening is formed in the fin; the source-drain doped layer is formed in the source-drain opening; and a second doped layer is formed on the substrate. A dielectric layer, the first dielectric layer covers the sidewall of the dummy gate structure; the dummy gate structure is removed, and a gate opening is formed in the first dielectric layer; the gate opening is formed in the gate opening grid structure.

Optionally, the sidewall structure includes: a first sidewall located on the sidewall of the dummy gate structure, and a second sidewall located on the sidewall of the first sidewall; After that, it also includes: removing the second side wall.

Optionally, the sacrificial sidewall layer includes: a first sacrificial sidewall layer and a second sacrificial sidewall layer located on the first sacrificial sidewall layer, and the material of the first sacrificial sidewall layer is the same as that of the The materials of the second sacrificial sidewall layer are different.

Optionally, the material of the first sacrificial spacer layer includes silicon carbide; the material of the second sacrificial spacer layer includes silicon oxide.

Optionally, the method for forming the sacrificial spacer includes: forming an initial first sacrificial spacer layer on the sidewall of the dummy gate structure; forming an opening in the initial first sacrificial spacer layer, so that the initial A first sacrificial spacer layer forms the first sacrificial spacer layer; and a second sacrificial spacer layer is formed in the opening.

Optionally, the first conductive structure includes: a first conductive plug located on the source-drain doped layer, and a first conductive layer located on the first conductive plug.

Optionally, the method for forming the first conductive structure includes: forming a first conductive opening in the first dielectric layer, the first conductive opening exposing the top surface of the source-drain doped layer and the Sacrifice the sidewall of the sidewall; form the first conductive plug in the first conductive opening; form a first covering layer in the first conductive opening; form a second dielectric layer on the first dielectric layer layer; forming a second conductive opening in the second dielectric layer, the first cover layer, and the first sacrificial spacer layer, the second conductive opening exposing the top surface of the first conductive plug and the sacrificial spacer a sidewall of the sidewall; forming the first conductive layer in the second conductive opening.

Optionally, the gate structure includes: a gate dielectric layer, a gate layer on the gate dielectric layer, and a second covering layer on the gate layer, the material of the second covering layer is the same as The materials of the first sidewalls are different; the gate structure includes several first regions and second regions located between the first regions, and the source-drain doped layer is located on both sides of the second regions , the second conductive structure is located on the second region.

Optionally, the method for forming the second conductive structure includes: removing the second covering layer and part of the second dielectric layer, forming a third conductive opening, and the third conductive opening exposes the gate structure and the the sidewall of the first sidewall; forming the second conductive structure in the third conductive opening.

Optionally, the method for removing the sacrificial sidewall includes: removing the second sacrificial sidewall layer by using a first etching process; removing the first sacrificial sidewall layer by using a second etching process.

Optionally, the second etching process adopts a remote plasma etching process.

Optionally, the process parameters of the remote plasma etching process include: the etching gas includes NH ₄ , O ₂ , and NF ₃ ; and the etching temperature is greater than 200 degrees Celsius.

Optionally, in the process of forming the first filling opening, it also includes: removing part of the second dielectric layer, forming a second filling opening in the second dielectric layer, and the second filling opening exposes The first filling opening and the second filling opening expose sidewalls of the first conductive structure and the second conductive structure.

Optionally, after forming the first filling layer, the method further includes: forming the second filling layer in the second filling opening, the second filling layer having a second air gap.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The structure of the technical solution of the present invention includes: a first filling opening exposing the sidewalls of the first conductive structure and the gate structure; the first filling opening located in the first filling opening A filling layer, the first filling layer has a first air gap in it. Since there is no other filling substance between the first conductive structure and the gate structure, the first filling layer has a relatively large filling space, so that the first air gap in the first filling layer The cavity is larger. When the cavity of the first air gap is large, the dielectric constant between the first conductive structure and the gate structure is small, so that the gap between the first conductive structure and the gate structure The parasitic capacitance is smaller, thereby improving the performance of the final semiconductor structure formed.

In the forming method of the technical solution of the present invention, a first filling opening is formed by removing the sacrificial sidewall to expose the sidewalls of the first conductive structure and the gate structure; The first filling layer has a first air gap in the first filling layer. Since there is no other filling substance between the first conductive structure and the gate structure, the first filling layer has a relatively large filling space, so that the first air gap in the first filling layer The cavity is larger. When the cavity of the first air gap is large, the dielectric constant between the first conductive structure and the gate structure is small, so that the gap between the first conductive structure and the gate structure The parasitic capacitance is smaller, thereby improving the performance of the final semiconductor structure formed.

Further, the spacer structure includes: a first sidewall located on the sidewall of the dummy gate structure, and a second sidewall located on the sidewall of the first sidewall; after forming the source-drain doped layer, It also includes: removing the second side wall. By removing the second spacer, the space between the first conductive structure and the gate structure can be increased, so that the filling space of the first filling layer is further increased, so that the first filling layer The cavity of the first air gap increases. In this way, the parasitic capacitance between the first conductive structure and the gate structure is reduced, and the performance of the finally formed semiconductor structure is improved.

Further, the second etching process adopts a remote plasma etching process; the process parameters of the remote plasma etching process include: the etching gas includes NH ₄ , O ₂ , and NF ₃ ; the etching temperature is greater than 200 degrees Celsius. The process difficulty of removing the first sacrificial sidewall layer can be effectively reduced by the remote plasma etching process.

Further, the sacrificial sidewall includes: a first sacrificial sidewall layer and a second sacrificial sidewall layer located on the first sacrificial sidewall layer, and the material of the first sacrificial sidewall layer is the same as that of the second sacrificial sidewall layer. The material of the sacrificial side wall layer is different. By forming the first sacrificial spacer layer and the second sacrificial spacer layer of different materials, the purpose is to form a subsequent first conductive layer through a self-aligned electrical contact process, thereby reducing the difficulty of the photolithography process. In addition, in the subsequent process of removing the first sacrificial sidewall layer and the second sacrificial sidewall layer, by first removing the second sacrificial sidewall layer, the exposed first sacrificial sidewall layer can be increased. The surface area of the wall layer can reduce the process difficulty of removing the first sacrificial sidewall layer.

Description of drawings

1 to 3 are structural schematic diagrams of a semiconductor structure;

4 to 16 are schematic structural diagrams of each step of the embodiment of the semiconductor structure forming method of the present invention.

detailed description

As mentioned in the background, the performance of the semiconductor structure formed by the self-aligned electrical contact process in the prior art still needs to be improved. The following will describe in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a top view of a semiconductor structure omitting the filling structure, the first conductive plug, the first conductive layer and the second conductive layer. FIG. 2 is a schematic cross-sectional view along line A-A in FIG. 1, including: A substrate 100 is provided, on which there are fins 101 extending along a first direction X; a gate structure 102 and several source-drain doped layers 103 are formed, and the gate structure 102 extends along a first direction X; Two directions Y span the fin portion 101, the second direction Y is perpendicular to the first direction X, and the gate structure 102 includes a first region I and several first regions arranged along the second direction Y. Two regions II, the first region I is located between the adjacent second regions II, and the source-drain doped layer 103 is located in the fins 101 on both sides of the first region I; in the source Forming a first conductive plug 104 on the drain doped layer 103; forming a sacrificial spacer on the substrate 100, the sacrificial spacer covering the first conductive plug 104 and the sidewall of the gate structure 102 , the sacrificial spacer includes a first sacrificial spacer layer 105 and a second sacrificial sidewall layer 106 on the first sacrificial sidewall layer 105, and the first sacrificial sidewall layer 105 and the second sacrificial spacer layer The materials of the two sacrificial spacer layers 106 are different; a first conductive layer 107 and the second conductive layer 108 are formed, the first conductive layer 107 is located on the first conductive plug 104, and the second conductive layer 108 Located on the first region I; forming a dielectric layer 109 , the dielectric layer 109 covers the sidewalls of the first conductive layer 107 and the second conductive layer 108 .

Please refer to FIG. 3 , the viewing directions of FIG. 3 and FIG. 2 are the same, the second sacrificial spacer layer 106 and part of the dielectric layer 109 are removed to form a filling opening (not marked); a first filling opening is formed in the filling opening. A filling layer 110, the first filling layer 110 has a first air gap 111 therein; a second filling layer 112 is formed on the first filling layer 110, the second filling layer 112 fills the filling opening, and The second filling layer 112 has a second air gap 113 inside.

In this embodiment, by forming the first sacrificial spacer layer 105 and the second sacrificial spacer layer 106 of different materials, the purpose is to form the first conductive layer 107 through a self-aligned electrical contact process, thereby reducing the Difficulty of photolithography process. In addition, by forming the second conductive layer 108 (Contact on active gate, COAG for short) on the first region I of the gate structure 102, the area occupied by the formed transistor can be effectively reduced, thereby improving the integration degree of the semiconductor structure.

Since the first conductive layer 107 is located on the first region I, thereby reducing the distance between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108, the resulting The parasitic capacitance increases. Therefore, in this embodiment, the first conductive plug 104 and the first conductive plug 104 are increased by forming the first filling layer 110 with the first air gap 111 and the second filling layer 112 with the second air gap 113. layer 107 and the second conductive layer 108 and the gate structure 102, thereby reducing the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure The parasitic capacitance between 102.

However, in this embodiment, since the process of removing the first sacrificial spacer layer 105 is relatively difficult, the first sacrificial spacer layer 105 is retained, but the retained first sacrificial spacer layer 105 will occupies part of the space between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure 102, so that the filling space of the first filling layer 110 is reduced, and then The cavity of the first air gap 111 finally formed is smaller. When the cavity of the first air gap 110 is small, the dielectric constant between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure 102 is relatively large, The parasitic capacitance between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure 102 is relatively large, thereby reducing the performance of the final semiconductor structure.

On this basis, the present invention provides a semiconductor structure and a method for forming the same. There is no other filling material between the first conductive structure and the gate structure, so that the first filling layer has a large filling space , so that the cavity of the first air gap in the first filling layer is larger. When the cavity of the first air gap is large, the dielectric constant between the first conductive structure and the gate structure is small, so that the gap between the first conductive structure and the gate structure The parasitic capacitance is smaller, thereby improving the performance of the final semiconductor structure formed.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 16 are structural schematic diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 4 , a substrate is provided, and the substrate includes: a base 200 and a fin 201 on the base 200 .

In other embodiments, the substrate may also be a planar structure.

In this embodiment, there is a device layer (not shown) in the substrate 200, and there are several device structures in the device layer, and the device structures include: PMOS transistors, NMOS transistors, CMOS transistors, resistors, capacitors and One or more of the inductors. The PMOS transistor, NMOS transistor and CMOS transistor all include basic gate, source and drain structures.

In other embodiments, the substrate may not have the device layer.

In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown), with a mask layer (not shown) on the initial substrate, and the mask layer exposes part of the the top surface of the initial substrate; etching the initial substrate by using the mask layer as a mask to form the substrate.

In this embodiment, the material of the fin portion 201 is silicon; in other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Referring to FIG. 5, an isolation layer 202 is formed on the substrate, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top of the fin 201. surface.

In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching and removing part of the initial isolation layer to form the isolation layer 202, The top surface of the isolation layer 202 is lower than the top surface of the fin portion 201 .

The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide

After the isolation layer 202 is formed, a gate structure and several source-drain doped layers are formed, the gate structure is located on the substrate, and the sidewalls of the gate structure have sacrificial sidewalls, the source The drain doped layer is located in the substrate on both sides of the gate structure. Please refer to FIG. 6 to FIG. 11 for the specific forming process.

Referring to FIG. 6 , a dummy gate structure 203 is formed on the substrate.

In this embodiment, the dummy gate structure 203 includes: a dummy gate dielectric layer, and a dummy gate layer (not shown) on the dummy gate dielectric layer.

In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

In this embodiment, the material of the dummy gate layer is polysilicon.

In this embodiment, the dummy gate structure 203 spans the fin portion 201 and covers part of the sidewall and top surface of the fin portion 201 .

Please refer to FIG. 7 , a spacer structure is formed on the sidewall of the dummy gate structure 203; the fin portion 201 is etched using the dummy gate structure 203 and the sidewall structure as a mask, and in the fin portion 201 A source-drain opening (not shown) is formed; the source-drain doped layer 204 is formed in the source-drain opening.

In this embodiment, the sidewall structure includes: a first sidewall 205 located on a sidewall of the dummy gate structure 203 , and a second sidewall 206 located on a sidewall of the first sidewall 205 .

In this embodiment, the material of the first sidewall 205 is silicon oxide; the material of the second sidewall 206 is silicon nitride.

In this embodiment, the method for forming the source-drain doped layer 204 in the source-drain opening includes: using an epitaxial growth process to form an epitaxial layer (not shown) in the source-drain opening; The implantation process of the leaked ions forms an ion implantation region (not shown), and the source-drain doped layer 204 is composed of the ion implantation region and the epitaxial layer.

Please refer to FIG. 8 , after the source-drain doped layer 204 is formed, the second spacer 206 is removed.

In this embodiment, by removing the second sidewall 206, the space between the subsequently formed first conductive structure and the gate structure can be increased, so that the filling space of the subsequently formed first filling layer can be further increased, and the resultant The cavity of the first air gap in the first filling layer is enlarged. In this way, the parasitic capacitance between the first conductive structure and the gate structure is reduced, and the performance of the finally formed semiconductor structure is improved.

Referring to FIG. 9 , sacrificial sidewalls are formed on the sidewalls of the first sidewalls 205 .

In this embodiment, the sacrificial sidewall includes: a first sacrificial sidewall layer 207 and a second sacrificial sidewall layer 208 on the first sacrificial sidewall layer 207, and the first sacrificial sidewall layer The material of 207 is different from that of the second sacrificial sidewall layer 208 .

In this embodiment, the material of the first sacrificial spacer layer 207 includes silicon carbide; the material of the second sacrificial spacer layer 208 includes silicon oxide.

In this embodiment, by forming the first sacrificial spacer layer 207 and the second sacrificial spacer layer 208 of different materials, the purpose is to form a subsequent first conductive layer through a self-aligned electrical contact process, thereby reducing the Difficulty of photolithography process. In addition, in the subsequent process of removing the first sacrificial spacer layer 207 and the second sacrificial spacer layer 208, by first removing the second sacrificial spacer layer 208, the exposed first sacrificial spacer layer 208 can be increased. A surface area of the sacrificial sidewall layer 207 can reduce the process difficulty of removing the first sacrificial sidewall layer 207 .

In this embodiment, the method for forming the sacrificial sidewall includes: forming an initial first sacrificial sidewall layer (not shown) on the sidewall of the first sidewall 205; Openings (not shown) are formed in layers such that the initial first sacrificial spacer layer forms the first sacrificial spacer layer 207 ; and the second sacrificial spacer layer 208 is formed in the opening.

Please refer to Figure 10 and Figure 11, Figure 10 is a top view of the semiconductor structure, Figure 11 is a schematic cross-sectional view along the B-B line in Figure 10, a first dielectric layer 209 is formed on the substrate, and the first dielectric layer 209 covers the The sidewall of the dummy gate structure 203 ; the dummy gate structure 203 is removed, and a gate opening (not shown) is formed in the first dielectric layer 209 ; the gate structure 210 is formed in the gate opening.

In this embodiment, the material of the first dielectric layer 209 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be a low-k dielectric material (refers to a dielectric constant lower than 3.9 dielectric material) or ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity lower than 2.5).

In this embodiment, the gate structure 210 includes: a gate dielectric layer, a gate layer on the gate dielectric layer, and a second covering layer (not shown) on the gate layer, the The material of the second covering layer is different from that of the first spacer 205; the gate structure 210 includes several first regions I, and second regions II located between the first regions I, the source The doped drain layer 204 is located on both sides of the second region II.

After forming the gate structure 210, it also includes: forming a first conductive structure and a second conductive structure, the first conductive structure is located on the source-drain doped layer 204, and the second conductive structure is located on the on the gate structure 210 . Please refer to FIG. 12 to FIG. 14 for the specific forming process.

Referring to FIG. 12, a first conductive opening (not marked) is formed in the first dielectric layer 209, and the first conductive opening exposes the top surface of the source-drain doped layer 204 and the sacrificial sidewall. sidewall; forming the first conductive plug 211 in the first conductive opening; forming a first covering layer 212 in the first conductive opening, and the first covering layer 212 is located on the first conductive plug 211 superior.

In this embodiment, the material of the first conductive plug 211 includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the first conductive plug 211 is tungsten.

Referring to FIG. 13 , a second dielectric layer 213 is formed on the first dielectric layer 209 .

In this embodiment, in this embodiment, the material of the second dielectric layer 213 is silicon oxide; in other embodiments, the material of the second dielectric layer can also be a low-k dielectric material Dielectric materials with a dielectric constant lower than 3.9) or ultra-low-k dielectric materials (referring to dielectric materials with a relative dielectric constant lower than 2.5).

Referring to FIG. 14, a second conductive opening (not marked) is formed in the second dielectric layer 213, the first cover layer 212 and the first sacrificial spacer layer 207, and the second conductive opening exposes the first The top surface of the conductive plug 211 and the sidewall of the sacrificial sidewall; the second covering layer and part of the second dielectric layer 213 are removed to form a third conductive opening (not marked), and the third conductive opening exposes The gate structure 210 and the side wall of the first spacer 205; the first conductive layer 214 is formed in the second conductive opening; the second conductive structure 215 is formed in the third conductive opening .

In this embodiment, the first conductive structure is composed of the first conductive plug 211 and the first conductive layer 214 .

In this embodiment, the third conductive opening exposes the top surface of the gate layer of the gate structure 210 .

In this embodiment, the second conductive structure 215 is located on the second region II of the gate structure 210 , which can effectively reduce the area occupied by the formed transistor, thereby improving the integration of the semiconductor structure.

In this embodiment, both the self-aligned electrical contact process is used in the process of forming the first conductive layer 214 and the second conductive structure 215, which can effectively reduce the difficulty of the photolithography process.

Referring to FIG. 15 , the sacrificial sidewalls are removed to expose sidewalls of the first conductive structure and the gate structure 210 to form a first filling opening 216 .

In this embodiment, the method for removing the sacrificial spacer includes: removing the second sacrificial spacer layer 208 by using a first etching process; removing the first sacrificial spacer layer 207 by using a second etching process.

In this embodiment, the second etching process adopts a remote plasma etching process; the process parameters of the remote plasma etching process include: etching gas including NH ₄ , O ₂ , NF ₃ ; etching temperature Greater than 200 degrees Celsius. The process difficulty of removing the first sacrificial sidewall layer can be effectively reduced by the remote plasma etching process.

Please continue to refer to FIG. 15 , in this embodiment, in the process of forming the first filling opening 216, it also includes: removing part of the second dielectric layer 213, forming a second dielectric layer in the second dielectric layer 213. The filling opening 217 , the second filling opening 217 exposes the first filling opening 216 , and the second filling opening 217 exposes sidewalls of the first conductive structure and the second conductive structure 215 .

Referring to FIG. 16 , a first filling layer 218 is formed in the first filling opening 216 , and a first air gap 219 is formed in the first filling layer 218 .

In this embodiment, the first filling opening 216 is formed by removing the sacrificial sidewall to expose the sidewalls of the first conductive structure and the gate structure 210; A filling layer 218, the first filling layer 218 has a first air gap 219 therein. Since there is no other filling substance between the first conductive structure and the gate structure 210, the first filling layer 218 has a large filling space, and the first filling layer 218 in the first filling layer 218 has a larger filling space. The cavity of the air gap 219 is larger. When the cavity of the first air gap 219 is larger, the dielectric constant between the first conductive structure and the gate structure 210 is smaller, so that the first conductive structure and the gate structure The parasitic capacitance between 210 is small, thereby improving the performance of the final formed semiconductor structure.

Please continue to refer to FIG. 16 , in this embodiment, after forming the first filling layer 218, it further includes: forming the second filling layer 220 in the second filling opening 217, the second filling layer There is a second air gap 221 inside 220 .

Correspondingly, an embodiment of the present invention also provides a semiconductor structure, please continue to refer to FIG. 16 , including: a substrate, the substrate includes: a base 200 and a fin 201 located on the base 200; The isolation layer 202 on the substrate, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201; located on the substrate The gate structure 210 on the gate structure 210; the source-drain doped layer 204 in the fin portion 201 on both sides of the gate structure 210; the first conductive structure and the second conductive structure 215, the first conductive structure is located in the On the source-drain doped layer 204, the second conductive structure 215 is located on the gate structure 210; the first filling opening 216 exposes the first conductive structure and the gate The sidewall of the structure 210 ; the first filling layer 218 located in the first filling opening 216 , and the first filling layer 218 has a first air gap 219 therein.

In this embodiment, it further includes: a first dielectric layer 209, the first dielectric layer 209 covers the sidewall of the gate structure 210, and the first filling opening 216 is located between the first dielectric layer 209 and the between the gate structures 210 .

In this embodiment, it further includes: a second dielectric layer 213 located on the first dielectric layer 209, the second dielectric layer 213 covers the first conductive structure and the second conductive structure 215, and the The second dielectric layer 213 exposes the top surfaces of the first conductive structure and the second conductive structure 215 .

In this embodiment, it further includes: a first sidewall 205 located on the sidewall of the gate structure 210 .

In this embodiment, the first conductive structure includes: a first conductive plug 211 located on the source-drain doped layer 204 , and a first conductive layer 214 located on the first conductive plug 211 .

In this embodiment, the gate structure 210 includes: a gate dielectric layer, and a gate layer located on the gate dielectric layer; the gate structure includes several first regions I, and In the second region II between I, the source-drain doped layer 204 is located on both sides of the second region II, and the second conductive structure 215 is located on the second region II.

In this embodiment, it further includes: a second filling opening 217, the second filling opening 217 communicates with the first filling opening 216, and the second filling opening 217 is located between the first conductive structure and the first filling opening 217. Between the two conductive structures 215 , the second filling opening 217 exposes sidewalls of the first conductive structure and the second conductive structure 215 .

In this embodiment, it further includes: the second filling layer 220 located in the second filling opening 217 , and the second filling layer 220 has a second air gap 221 therein.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (23)

1. A semiconductor structure, comprising:

the substrate comprises a base and a fin part positioned on the base;

the isolation layer is positioned on the substrate, covers partial side walls of the fin parts, and the top surfaces of the isolation layer are lower than the top surfaces of the fin parts;

a gate structure on the substrate, the gate structure spanning the fin;

the source-drain doping layers are positioned in the fin parts on two sides of the grid structure;

the first conductive structure is positioned on the source-drain doping layer, and the second conductive structure is positioned on the grid structure;

a first fill opening exposing sidewalls of the first conductive structure and the gate structure;

and the first filling layer is positioned in the first filling opening and is internally provided with a first air gap.

2. The semiconductor structure of claim 1, further comprising: the first dielectric layer covers the side wall of the grid structure, and the first filling opening is positioned between the first dielectric layer and the grid structure.

3. The semiconductor structure of claim 2, further comprising: and the second dielectric layer is positioned on the first dielectric layer, covers the first conductive structure and the second conductive structure, and exposes the top surfaces of the first conductive structure and the second conductive structure.

4. The semiconductor structure of claim 1, further comprising: and the first side wall is positioned on the side wall of the grid structure.

5. The semiconductor structure of claim 1, wherein the first conductive structure comprises: the semiconductor device comprises a first conductive plug positioned on the source-drain doped layer and a first conductive layer positioned on the first conductive plug.

6. The semiconductor structure of claim 1, wherein the gate structure comprises: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer; the grid structure comprises a plurality of first regions and a second region located between the first regions, the source drain doping layer is located on two sides of the second region, and the second conductive structure is located on the second region.

7. The semiconductor structure of claim 1, further comprising: a second fill opening in communication with the first fill opening, the second fill opening being between the first conductive structure and the second conductive structure, and the second fill opening exposing sidewalls of the first conductive structure and the second conductive structure.

8. The semiconductor structure of claim 7, further comprising: the second filling layer is positioned in the second filling opening, and a second air gap is formed in the second filling layer.

9. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a base and a fin part positioned on the base;

forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part;

forming a grid structure and a plurality of source drain doping layers, wherein the grid structure stretches across the fin parts, the side walls of the grid structure are provided with sacrificial side walls, and the source drain doping layers are located in the fin parts on two sides of the grid structure;

forming a first conductive structure and a second conductive structure, wherein the first conductive structure is positioned on the source-drain doping layer, and the second conductive structure is positioned on the grid structure;

removing the sacrificial side wall to expose the side walls of the first conductive structure and the grid structure to form a first filling opening;

and forming a first filling layer in the first filling opening, wherein the first filling layer is internally provided with a first air gap.

10. The method for forming the semiconductor structure according to claim 9, wherein the method for forming the gate structure and the source-drain doping layer comprises: forming a pseudo gate structure on the substrate; forming a side wall structure on the side wall of the pseudo gate structure; etching the fin part by using the pseudo gate structure and the side wall structure as masks, and forming a source drain opening in the fin part; forming a source-drain doping layer in the source-drain opening;

forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the first dielectric layer; and forming the gate structure in the gate opening.

11. The method for forming a semiconductor structure of claim 10, wherein the sidewall spacer structure comprises: the first side wall is positioned on the side wall of the pseudo gate structure, and the second side wall is positioned on the side wall of the first side wall; after the source-drain doping layer is formed, the method further comprises the following steps: and removing the second side wall.

12. The method for forming a semiconductor structure of claim 9, wherein the sacrificial sidewall spacer comprises: the sacrificial spacer comprises a first sacrificial side wall layer and a second sacrificial side wall layer located on the first sacrificial side wall layer, wherein the first sacrificial side wall layer is made of a material different from that of the second sacrificial side wall layer.

13. The method of forming a semiconductor structure of claim 12, wherein the material of the first sacrificial spacer layer comprises silicon carbide; the material of the second sacrificial side wall layer comprises silicon oxide.

14. The method for forming the semiconductor structure according to claim 12, wherein the method for forming the sacrificial spacer comprises: forming an initial first sacrificial side wall layer on the side wall of the pseudo gate structure; forming an opening in the initial first sacrificial side wall layer, so that the initial first sacrificial side wall layer forms the first sacrificial side wall layer; and forming the second sacrificial side wall layer in the opening.

15. The method of forming a semiconductor structure of claim 10, wherein the first conductive structure comprises: the semiconductor device comprises a first conductive plug positioned on the source drain doping layer and a first conductive layer positioned on the first conductive plug.

16. The method of forming a semiconductor structure of claim 15, wherein the method of forming the first conductive structure comprises: forming a first conductive opening in the first dielectric layer, wherein the first conductive opening exposes the top surface of the source-drain doping layer and the side wall of the sacrificial side wall; forming the first conductive plug in the first conductive opening; forming a first covering layer in the first conductive opening; forming a second dielectric layer on the first dielectric layer; forming a second conductive opening in the second dielectric layer, the first covering layer and the first sacrificial side wall layer, wherein the second conductive opening exposes the top surface of the first conductive plug and the side wall of the sacrificial side wall; and forming the first conductive layer in the second conductive opening.

17. The method of forming a semiconductor structure of claim 16, wherein the gate structure comprises: the gate dielectric layer, the gate layer positioned on the gate dielectric layer and the second covering layer positioned on the gate layer are made of different materials; the grid structure comprises a plurality of first regions and a second region located between the first regions, the source-drain doped layers are located on two sides of the second region, and the second conductive structure is located on the second region.

18. The method of forming a semiconductor structure of claim 17, wherein the method of forming the second conductive structure comprises: removing the second covering layer and part of the second dielectric layer to form a third conductive opening, wherein the gate structure and the side wall of the first side wall are exposed out of the third conductive opening; and forming the second conductive structure in the third conductive opening.

19. The method for forming a semiconductor structure according to claim 9, wherein the removing the sacrificial spacer comprises: removing the second sacrificial side wall layer by adopting a first etching process; and removing the first sacrificial side wall layer by adopting a second etching process.

20. The method of forming a semiconductor structure of claim 19, wherein the second etch process uses a remote plasma etch process.

21. The method of forming a semiconductor structure of claim 20, wherein the process parameters of the remote plasma etch process comprise: the etching gas comprises NH ₄ 、O ₂ 、NF ₃ (ii) a The etching temperature is more than 200 ℃.

22. The method of forming a semiconductor structure of claim 16, further comprising, during the forming the first fill opening: and removing part of the second dielectric layer, and forming a second filling opening in the second dielectric layer, wherein the second filling opening exposes the first filling opening, and the second filling opening exposes the sidewalls of the first conductive structure and the second conductive structure.

23. The method of forming a semiconductor structure of claim 22, further comprising, after forming the first fill layer: and forming the second filling layer in the second filling opening, wherein a second air gap is formed in the second filling layer.

Images