CN115527924A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the bottom dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer and comprise a first interconnection layer and a second interconnection layer which are spaced, and a conductive plug which is in contact with the first interconnection layer is formed in the second dielectric layer; a top dielectric layer located on the bottom dielectric layer; the first metal wire penetrates through the top dielectric layer and is in contact with the conductive plug, and the first metal wire is used as a signal wire; the second metal wire penetrates through the second dielectric layer and the top dielectric layer and is in contact with the second interconnection layer, and the second metal wire is used as a power supply line, so that the power supply line is not required to be electrically connected with the second interconnection layer through a conductive plug, the influence of the resistance of the conductive plug on the electric connection performance between the power supply line and the second interconnection layer is favorably prevented, the electric connection performance between the power supply line and the second interconnection layer is optimized, the IR voltage drop is reduced, and the power supply efficiency of the device is improved.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.

In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or the metal layer and the substrate is realized through the interconnection structure. With the advancement of technology nodes, the size of the interconnection structure becomes smaller and smaller; correspondingly, the process difficulty of forming the interconnection structure is also increasing, and the formation quality of the interconnection structure has a great impact on the back end offline , BEOL) has a great influence on the electrical performance and device reliability, and in severe cases, it will affect the normal operation of semiconductor devices.

Wherein, the metal wires generally include signal wires for transmitting signals, and power supply wires for supplying power to components in the chip.

However, the power supply efficiency of current devices is low.

Contents of the invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the power supply efficiency of the device.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a bottom dielectric layer, and the bottom dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, A plurality of interconnection layers are formed in the first dielectric layer, including a first interconnection layer and a second interconnection layer spaced apart from each other, and the second dielectric layer on the top of the first interconnection layer is formed with a A conductive plug in contact with the first interconnection layer; a top dielectric layer located on the bottom dielectric layer; a first metal line passing through the top dielectric layer on top of the conductive plug and in contact with the conductive plug contact, the first metal line is used as a signal line; the second metal line runs through the second dielectric layer and the top dielectric layer on the top of the second interconnection layer, and is in contact with the second interconnection layer contacts, the second metal wire is used as a power supply wire.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a bottom dielectric layer, and the bottom dielectric layer includes a first dielectric layer and a substrate located on the first dielectric layer. A second dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, including a first interconnection layer and a second interconnection layer spaced apart, and the second dielectric layer on the top of the first interconnection layer A conductive plug in contact with the first interconnection layer is formed in the layer; a top dielectric layer is formed on the bottom dielectric layer; a first interconnection groove penetrating through the top dielectric layer on the top of the conductive plug is formed, and a second interconnection groove penetrating through the second dielectric layer on top of the second interconnection layer and the top dielectric layer, the first interconnection groove exposes the conductive plug, and the second interconnection groove exposes out of the second interconnection layer; fill the first interconnection groove and the second interconnection groove with conductive material, respectively form a first metal line and a second metal line correspondingly, and the first metal line and the The conductive plug is in contact with and serves as a signal line, and the second metal line is in contact with the second interconnection layer and is used as a power supply line.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the semiconductor structure provided by the embodiment of the present invention, the first metal line is in contact with the conductive plug and is used as a signal line, and the second metal line is in contact with the second interconnection layer and is used as a signal line. The power supply line, so that the electrical connection between the power supply line and the second interconnection layer does not need to be electrically connected through a conductive plug, which is beneficial to prevent the impact of the resistance of the conductive plug on the performance of the electrical connection between the power supply line and the second interconnection layer, and optimizes the The electrical connection performance between the power supply line and the second interconnection layer reduces the IR drop (IR drop), and improves the power supply efficiency of the device.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming the first interconnection trench and the second interconnection trench, the first interconnection trench penetrates the top dielectric layer on the conductive plug, so The second interconnection trench penetrates the second dielectric layer and the top dielectric layer on the top of the second interconnection layer, and the second interconnection trench exposes the second interconnection layer, that is, Compared with the depth of , the depth of the second interconnection groove is larger, and the conductive material is filled in the first interconnection groove and the second interconnection groove, corresponding to the steps of forming the first metal line and the second metal line respectively wherein, the first metal line is in contact with the conductive plug and is used as a signal line, and the second metal line is in contact with the second interconnection layer and is used as a power supply line, so that the power supply line and the The second interconnection layer does not need to be electrically connected through a conductive plug, which is beneficial to prevent the impact of the resistance of the conductive plug on the performance of the electrical connection between the power supply line and the second interconnection layer, and optimizes the power supply line and the second interconnection. The electrical connection performance between the layers reduces the IR drop (IR drop), and improves the power supply efficiency of the device.

Description of drawings

Fig. 1 is a structural schematic diagram of a semiconductor structure;

2 is a schematic structural view of an embodiment of a semiconductor structure of the present invention;

3 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

detailed description

It can be seen from the background art that the power supply efficiency of current devices is relatively low. The reason why the power supply efficiency of the device is low is analyzed in combination with a semiconductor structure. FIG. 1 is a schematic structural diagram of a semiconductor structure.

Referring to FIG. 1, the semiconductor structure includes: a base 10, including a substrate (not shown), a gate structure (not shown) on the substrate, source and drain doped regions 11 on both sides of the gate structure, The first dielectric layer 12 that is located on the substrate and covers the source-drain doped region 11 is formed in the first dielectric layer 12 with a plurality of source-drain interconnection layers that are in contact with the source-drain doped region 11, including the first source-drain interconnection layer Interconnection layer 13 and second source-drain interconnection layer 14; second dielectric layer 15, located on the first dielectric layer 12 and covering the source-drain interconnection layer; conductive plug, located in the second dielectric layer 15 And in contact with the source-drain interconnection layer, the conductive plug includes a first conductive plug 16 in contact with the first source-drain interconnection layer 13, and a contact with the second source-drain interconnection layer The second conductive plug 17 in contact with 14; the third dielectric layer 18, located on the second dielectric layer 15 and covering the conductive plug; a plurality of metal lines, located in the third dielectric layer 18, including the A signal line 19(1) in contact with a conductive plug 16, and a power supply line 19(2) in contact with the second conductive plug 17, and the line width of the power supply line 19(2) is larger than the The line width of the signal line 19(1).

In the semiconductor structure, compared with the signal line 19(1), the line width of the power supply line 19(2) is larger, so as to reduce the resistance of the power supply line 19(2), thereby reducing the IR drop (IR drop). Moreover, the power supply line 19(2) and the signal line 19(1) are formed in the same process step, and both the power supply line 19(2) and the signal line 19(1) need to pass between the conductive plug and the corresponding source-drain interconnection layer. To achieve electrical connection between.

However, the power supply line 19(2) is used to supply power to the source-drain doped region 11 through the source-drain interconnection layer, and the electrical connection between the power supply line 19(2) and the source-drain interconnection layer is realized through a conductive plug, and the conductive plug Resistors will degrade the power delivery efficiency of the device.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a bottom dielectric layer, and the bottom dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer layer, a plurality of interconnection layers are formed in the first dielectric layer, including a first interconnection layer and a second interconnection layer spaced apart, and a plurality of interconnection layers are formed in the second dielectric layer on top of the first interconnection layer There is a conductive plug in contact with the first interconnection layer; a top dielectric layer is located on the bottom dielectric layer; a first metal line passes through the top dielectric layer on the top of the conductive plug and connects with the conductive plug plug phase contact, the first metal line is used as a signal line; the second metal line penetrates the second dielectric layer and the top dielectric layer on the top of the second interconnection layer, and is connected to the second interconnection The layers are in contact with each other, and the second metal line is used as a power supply line.

In the semiconductor structure provided by the embodiment of the present invention, the first metal line is in contact with the conductive plug and is used as a signal line, and the second metal line is in contact with the second interconnection layer and is used as a signal line. The power supply line, so that the electrical connection between the power supply line and the second interconnection layer does not need to be electrically connected through a conductive plug, which is beneficial to prevent the impact of the resistance of the conductive plug on the performance of the electrical connection between the power supply line and the second interconnection layer, and optimizes the The electrical connection performance between the power supply line and the second interconnection layer reduces the IR drop (IR drop), and improves the power supply efficiency of the device.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Referring to FIG. 2 , it shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

As shown in FIG. 2, in this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a bottom dielectric layer 101, and the bottom dielectric layer 101 includes a first dielectric layer 130 and is located on the first dielectric layer 130. The second dielectric layer 150, the first dielectric layer 130 is formed with a plurality of interconnection layers, including the first interconnection layer 170 and the second interconnection layer 180 spaced apart, the top of the first interconnection layer 170 A conductive plug 160 in contact with the first interconnection layer 170 is formed in the second dielectric layer 150; a top dielectric layer 102 is located on the bottom dielectric layer 101; a first metal line 210 runs through the conductive The top dielectric layer 102 on the top of the plug 160 is in contact with the conductive plug 160, the first metal line 210 is used as a signal line; the second metal line 220 runs through the second interconnection layer 180 The second dielectric layer 150 and the top dielectric layer 102 on the top are in contact with the second interconnection layer 180 , and the second metal wire 220 is used as a power rail.

The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

According to actual process conditions, the base 100 includes a substrate and functional structures formed on the substrate, for example, the functional structures may include semiconductor devices such as MOS field effect transistors, resistor structures, conductive structures, and the like.

Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) on the substrate, and source and drain structures located on both sides of the gate structure. doped region 140 . The gate structure and the source-drain doped regions 140 located on both sides of the gate structure are used to form a MOS transistor.

The substrate provides the process platform for the formation of transistors. The material of the substrate includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and gallium indium.

The gate structure is used to turn on and off the conduction channel of the transistor. The material of the gate structure includes: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni Any one or more.

In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) located between the gate structure and the channel structure 110 . The gate dielectric layer is used to realize electrical isolation between the gate structure and the channel structure.

In this embodiment, the material of the gate dielectric layer includes: one of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La ₂ O ₃ , Al ₂ O ₃ , silicon oxide, and nitrogen-doped silicon oxide. one or more species.

The source-drain doped region 140 is used as the source or drain of the transistor. As an example, when forming a PMOS transistor, the source-drain doped region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain doped region 140 includes The stress layer doped with N-type ions is made of Si or SiC.

As an embodiment, the substrate 100 further includes a raised portion 105 separated on the substrate, a channel structure 110 located on the raised portion 105, and an isolation layer 115 located on the substrate and surrounding the raised portion 105 The gate structure is located on the isolation layer 115 and crosses the channel structure 110; the source-drain doped region 140 is located in the channel structure 110 on both sides of the gate structure.

The channel structure 110 is used to provide a conduction channel of the field effect transistor. The materials of the raised portion 105 and the channel structure 110 include: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.

In this embodiment, the channel structure 110 is a fin, and the gate structure correspondingly straddles the fin and covers part of the top and part of the sidewall of the fin. Specifically, the fin portion is connected to the raised portion 105 . In other embodiments, when the channel structure is a channel structure layer suspended from the raised portion, the channel structure layer includes one or more channel layers arranged at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layer.

The isolation layer 115 is used for isolating adjacent raised portions 105 and is also used for isolating the substrate and the gate structure. The isolation layer 115 exposes the channel structure 110 . The material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride.

In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source-drain doped region 140 . Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115 .

The bottom dielectric layer 101 is a stacked structure or a single layer structure. In this embodiment, the bottom dielectric layer 101 is taken as an example for illustration.

In the bottom dielectric layer 101 , the first dielectric layer 130 is used to realize electrical isolation between interconnection layers, and the second dielectric layer 150 is used to realize electrical isolation between conductive plugs 160 .

The materials of the first dielectric layer 130 and the second dielectric layer 150 are dielectric materials, such as one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG. As an example, the material of the first dielectric layer 130 is silicon oxide. As an example, the material of the second dielectric layer 180 is carbon silicon hydroxide.

The interconnection layer is used to realize the electrical connection between the functional structures in the substrate 100 and external circuits or other interconnection structures. There are multiple interconnection layers, so that multiple functional structures in the substrate 100 can be electrically connected to external circuits or other interconnection structures.

The material of the interconnection layer is a conductive material, and the material of the interconnection layer includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more. As an example, the material of the interconnection layer is Cu. The resistivity of Cu is low, which is beneficial to reduce the RC delay in the back-end process, and Cu has excellent resistance to electromigration.

As an embodiment, the interconnection layer is located in the first dielectric layer 130 on top of the source-drain doped region 140 and is in contact with the source-drain doped region 140 . That is to say, the interconnection layer serves as a source-drain interconnection layer for realizing the electrical connection between the source-drain doped region 140 and an external circuit or interconnection structure.

In other implementations, according to actual process requirements, the interconnection layer may also be another type of interconnection layer for realizing electrical connection between other components and external circuits or interconnection structures.

In this embodiment, for the convenience of illustration and description, only two device regions in the substrate 100 are shown, and MOS transistors are correspondingly formed in each device region. Correspondingly, the first interconnection layer 170 and the second interconnection layer 170 The layer 180 is respectively used to realize the electrical connection between the source and drain doped regions 140 of the two device regions and external circuits or other interconnection structures.

The conductive plug 160 is used to realize electrical connection between the interconnection layer and external circuits or other interconnection structures. Specifically, in this embodiment, the conductive plug 160 is used to electrically connect the first interconnection layer 170 with an external circuit or other interconnection structures.

The material of the conductive plug 160 is a conductive material. The material of the conductive plug 160 is a conductive material, and the material of the conductive plug 160 includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more of.

The top dielectric layer 102 is used to realize electrical isolation between metal lines. The top dielectric layer 102 covers the conductive plug 160 .

The material of the top dielectric layer 102 is a dielectric material. The material of the top dielectric layer 102 may include one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG. Specifically, the material of the top dielectric layer 102 can be a low-k dielectric material or an ultra-low-k dielectric material, so that the capacitance between metal lines can be effectively reduced, thereby reducing the RC delay of the device. As an example, the material of the top dielectric layer 102 is silicon carbon hydroxide.

The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnection layer 170, therefore, the first metal line 210 is used to implement source-drain doping The electrical connection between the impurity region 140 and external circuits or other interconnection structures. In this embodiment, the first metal line 210 is used as a signal line for realizing signal connection between the source-drain doped region 140 and external circuits or other interconnection structures.

The second metal line 220 is in contact with the second interconnection layer 180, and the second interconnection layer 180 is in contact with the source-drain doped region 140, therefore, the second metal line 220 is used for To realize the electrical connection between the source-drain doped region 140 and external circuits or other interconnection structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source-drain doped region 140 .

The second metal line 220 is in contact with the second interconnection layer 180 and is used as a power supply line, so that the electrical connection between the power supply line and the second interconnection layer 180 does not need to be electrically connected through the conductive plug 160, which is beneficial to prevent The influence of the resistance of the conductive plug on the electrical connection performance between the power supply line and the second interconnection layer 180 optimizes the electrical connection performance between the power supply line and the second interconnection layer 180, reduces the IR drop (IR drop), The power supply efficiency of the device is improved.

Moreover, in this embodiment, the line width of the second metal line 220 is larger than the line width of the first metal line 210, that is, the line width of the power supply line is larger than the line width of the signal line, It is beneficial to reduce the resistance of the power supply line, reduce IRdrop, and further improve the power supply efficiency of the device.

Materials of the first metal wire 210 and the second metal wire 220 are conductive materials. As an example, the material of the first metal line 210 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN The material of the second metal line 220 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN.

The first metal line 210 may include a first anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the first interconnection trench 230 , and a first anti-diffusion barrier layer located on the first anti-diffusion barrier layer and filling the first The first metal layer of the interconnection groove (not shown in the figure); the second metal line 220 may include a second anti-diffusion barrier layer (not shown in the figure) located on the sidewall and bottom of the second interconnection groove 240, and A second metal layer (not shown) located on the second diffusion barrier layer and filling the second interconnection groove.

In this embodiment, the first metal line 210 and the second metal line 220 are formed in the same step, therefore, the structure of the first metal line 210 and the structure of the second metal line 220 are the same, and the first The material of the metal wire 210 is the same as that of the second metal wire 220 .

Specifically, in this embodiment, the material of the first anti-diffusion barrier layer is the same as that of the second anti-diffusion barrier layer, and the material of the first metal layer and the second metal layer is the same.

As an example, the material of the first anti-diffusion barrier layer and the material of the second anti-diffusion barrier layer are TiN; the material of the first metal layer and the second metal layer is Cu, and the resistivity of Cu is relatively high. Low, it is beneficial to reduce the RC delay in the back-end process, and Cu has excellent resistance to electromigration.

The number of the first metal lines 210 may be one or more. The number of the second metal wires 220 may be one or more. It should be noted that, in an actual process, when there are multiple second metal lines 220, some of the second metal lines 220 may not be connected to the second interconnection layer based on the interconnection layer and the actual pattern of the metal lines. Layer 180 is in contact.

Correspondingly, the present invention also provides a method for forming a semiconductor structure. 3 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 3 , a substrate 100 is provided, the substrate 100 includes a bottom dielectric layer 101, the bottom dielectric layer 101 includes a first dielectric layer 130 and a second dielectric layer 150 on the first dielectric layer 130, the first dielectric layer 130 A plurality of interconnection layers are formed in a dielectric layer 130, including a first interconnection layer 170 and a second interconnection layer 180 spaced apart, and the first interconnection layer 170 is formed in the second dielectric layer 180 There is a conductive plug 160 in contact with the first interconnection layer 170 .

The substrate 100 is used to provide a process platform for subsequent processes.

According to actual process conditions, the base 100 includes a substrate and functional structures formed on the substrate, for example, the functional structures may include semiconductor devices such as MOS field effect transistors, resistor structures, conductive structures, and the like.

Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) on the substrate, and source and drain structures located on both sides of the gate structure. doped region 140 . The gate structure and the source-drain doped regions 140 located on both sides of the gate structure are used to form a MOS transistor.

The substrate provides the process platform for the formation of transistors. The material of the substrate includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and gallium indium

The gate structure is used to turn on and off the conduction channel of the transistor. The material of the gate structure includes: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni Any one or more.

In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) located between the gate structure and the channel structure 110 . The gate dielectric layer is used to realize electrical isolation between the gate structure and the channel structure.

The material of the gate dielectric layer includes: one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La ₂ O ₃ , Al ₂ O ₃ , silicon oxide and silicon oxide doped with nitrogen.

The source-drain doped region 140 is used as the source or drain of the transistor. As an example, when forming a PMOS transistor, the source-drain doped region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain doped region 140 includes The stress layer doped with N-type ions is made of Si or SiC.

As an embodiment, the substrate 100 further includes a raised portion 105 separated on the substrate, a channel structure 110 located on the raised portion 105, and an isolation layer 115 located on the substrate and surrounding the raised portion 105 The gate structure is located on the isolation layer 115 and crosses the channel structure 110; the source-drain doped region 140 is located in the channel structure 110 on both sides of the gate structure.

The channel structure 110 is used to provide a conduction channel of the field effect transistor. The materials of the raised portion 105 and the channel structure 110 include: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.

In this embodiment, the channel structure 110 is a fin, and the gate structure correspondingly straddles the fin and covers part of the top and part of the sidewall of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the raised portion, the channel structure layer includes one or more channel layers arranged at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layer.

The isolation layer 115 is used for isolating adjacent raised portions 105 and is also used for isolating the substrate and the gate structure. The isolation layer 115 exposes the channel structure 110 . The material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride.

In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source-drain doped region 140 . Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115 .

The bottom dielectric layer 101 is a stacked structure or a single layer structure. In this embodiment, the bottom dielectric layer 101 is taken as an example for illustration.

In the bottom dielectric layer 101 , the first dielectric layer 130 is used to realize electrical isolation between interconnection layers, and the second dielectric layer 150 is used to realize electrical isolation between conductive plugs 160 .

The materials of the first dielectric layer 130 and the second dielectric layer 150 are dielectric materials, such as one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG. As an example, the material of the first dielectric layer 130 is silicon oxide. As an example, the material of the second dielectric layer 180 is carbon silicon hydroxide.

The interconnection layer is used to realize the electrical connection between the functional structures in the substrate 100 and external circuits or other interconnection structures. There are multiple interconnection layers, so that multiple functional structures in the substrate 100 can be electrically connected to external circuits or other interconnection structures.

The material of the interconnection layer is a conductive material, and the material of the interconnection layer includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more. As an example, the material of the interconnection layer is Cu. The resistivity of Cu is low, which is beneficial to reduce the RC delay in the back-end process, and Cu has excellent resistance to electromigration.

As an embodiment, the interconnection layer is located in the first dielectric layer 130 on top of the source-drain doped region 140 and is in contact with the source-drain doped region 140 . That is to say, the interconnection layer serves as a source-drain interconnection layer for realizing the electrical connection between the source-drain doped region 140 and an external circuit or interconnection structure.

In other implementations, according to actual process requirements, the interconnection layer may also be another type of interconnection layer for realizing electrical connection between other components and external circuits or interconnection structures.

In this embodiment, for the convenience of illustration and description, only two device regions in the substrate 100 are shown, and MOS transistors are correspondingly formed in each device region. Correspondingly, the first interconnection layer 170 and the second interconnection layer 170 The layer 180 is respectively used to realize the electrical connection between the source and drain doped regions 140 of the two device regions and external circuits or other interconnection structures.

The conductive plug 160 is used to realize electrical connection between the interconnection layer and external circuits or other interconnection structures. Specifically, in this embodiment, the conductive plug 160 is used to electrically connect the first interconnection layer 170 with an external circuit or other interconnection structures.

The material of the conductive plug 160 is a conductive material. The material of the conductive plug 160 is a conductive material, and the material of the conductive plug 160 includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more of.

Continuing to refer to FIG. 3 , a top dielectric layer 102 is formed on the bottom dielectric layer 101 . The top dielectric layer 102 covers the conductive plug 160 .

Subsequently, a plurality of metal lines are formed in the top dielectric layer 102, and the top dielectric layer 102 is used to realize electrical isolation between the metal lines.

The material of the top dielectric layer 102 is a dielectric material. The material of the top dielectric layer 102 may include one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG. Specifically, the material of the top dielectric layer 102 can be a low-k dielectric material or an ultra-low-k dielectric material, so that the capacitance between metal lines can be effectively reduced, thereby reducing the RC delay of the device. As an example, the material of the top dielectric layer 102 is silicon carbon hydroxide.

Referring to FIG. 4 to FIG. 8, the first interconnect groove 230 penetrating through the top dielectric layer 102 on the top of the conductive plug 160, and the second dielectric layer 150 and the The second interconnection groove 240 (as shown in FIG. 7 ) of the top dielectric layer 102, the first interconnection groove 230 exposes the conductive plug 160, and the second interconnection groove 240 exposes the second interconnect layer 180 .

The first interconnection groove 230 is used to provide a space for forming the first metal line.

The first interconnection groove 230 penetrates through the top dielectric layer 102 on the top of the conductive plug 160 and exposes the conductive plug 160 so that the subsequent first metal line can contact the conductive plug 160 .

The second interconnection groove 240 is used to provide a space for forming the second metal line.

The second interconnect groove 240 penetrates the second dielectric layer 150 and the top dielectric layer 102 on the top of the second interconnect layer 180, and exposes the second interconnect layer 180, so that the subsequent second metal line can The second interconnection layer 180 is in contact.

Moreover, in this embodiment, the first metal line is used as a signal line, the second metal line is used as a power supply line, and the second interconnection groove 240 runs through the first interconnection groove 240 on the top of the second interconnection layer 180 . The second dielectric layer 150 and the top dielectric layer 102, and expose the second interconnection layer 180, so that the subsequent power supply line is in direct contact with the second interconnection layer 180, and the connection between the power supply line and the second interconnection layer 180 There is no need to realize the electrical connection through the conductive plug, which is beneficial to prevent the impact of the resistance of the conductive plug on the performance of the electrical connection between the power supply line and the second interconnection layer 180, and optimizes the electrical connection between the power supply line and the second interconnection layer 180. connection performance, reducing the IR drop (IR drop), and improving the power supply efficiency of the device.

In this embodiment, the opening line width of the second interconnection groove 240 is greater than the opening line width of the first interconnection groove 230, correspondingly, the first metal line is subsequently formed in the first interconnection groove 230, and the After the second metal line is formed in the second interconnection groove 240, the line width of the second metal line is greater than the line width of the first metal line, that is, compared with the line width of the signal line, the power supply line The larger line width is beneficial to reduce the resistance of the power supply line and reduce IR drop, thereby improving the power supply efficiency of the device.

The number of the first interconnection slots 230 may be one or more. The number of the second interconnection slots 240 may be one or more. It should be noted that, in an actual process, when there are multiple second interconnection grooves 240, based on the interconnection layer and the actual pattern of the interconnection grooves, part of the second interconnection grooves 240 may not expose the The second interconnection layer 180 .

The steps of forming the first interconnection trench 230 and the second interconnection trench 240 in this embodiment will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 4 , a plurality of trenches penetrating through the top dielectric layer 102 are formed, including a first interconnect groove 230 located on the top of the conductive plug 160 and exposing the conductive plug 160, and a first interconnect groove 230 located on the top of the conductive plug 160, and a groove located at the second interconnection. The first initial trench 260 above the connecting layer 180 , the first initial trench 260 exposes the second dielectric layer 102 .

In this embodiment, the opening line width of the first initial trench 260 is larger than the opening line width of the first interconnection trench 230, so as to form the second dielectric layer 102 penetrating through the bottom of the first initial trench 260. The second initial trench, the opening line width of the second interconnection trench formed by the second initial trench and the first initial trench 260 is relatively large, correspondingly making the second metal line subsequently formed in the second interconnection trench The line width is larger.

Specifically, in this embodiment, the step of forming a plurality of trenches penetrating the top dielectric layer 102 includes: forming a hard mask layer 250 on the top dielectric layer 102, and forming a hard mask layer 250 in the hard mask layer 250 A plurality of mask openings (not marked); using the hard mask layer 250 as a mask, etching the top dielectric layer 102 along the mask openings to form a plurality of trenches penetrating through the top dielectric layer 102 .

The hard mask layer 250 is used as an etch mask for forming the trenches. The mask openings are used to define the size, shape and location of the trenches.

The hard mask layer 250 is selected from a material having etching selectivity with the materials of the top dielectric layer 102 and the bottom dielectric layer 101 , so as to ensure that the hard mask layer 250 can function as an etching mask.

As an embodiment, the material of the hard mask layer 250 is titanium nitride.

In this embodiment, using the hard mask layer 250 as a mask, an anisotropic etching process is used to etch the top dielectric layer 102 along the opening of the mask to form a plurality of trenches. The anisotropic etching process is beneficial to improve the accuracy of pattern transfer, thereby improving the controllability of the profile of the groove and the dimensional accuracy of the groove. Specifically, the anisotropic etching process may be an anisotropic dry etching process.

Referring to FIG. 5 to FIG. 8 , a second initial trench 270 penetrating through the second dielectric layer 102 at the bottom of the first initial trench 260 is formed, and the second initial trench 270 exposes the second interconnection layer 180 , the second initial trench 270 and the first initial trench 260 are used to form the second interconnection trench 240 .

The second initial trench 270 is formed to increase the depth of the second interconnection trench, so that the second interconnection trench can expose the second interconnection layer 180 .

As an embodiment, the step of forming the second initial trench 270 includes:

As shown in FIG. 5 , a sacrificial layer 245 is formed on the bottom and sidewalls of the trench, and the sacrificial layer 245 located on the sidewall of the first interconnection groove 230 is in contact with and fills the first interconnection groove. 230 , the sidewalls of the sacrificial layer 245 located on the sidewalls of the first initial trench 260 are separated.

The sacrificial layer 245 is used to form a shielding layer in the first interconnection groove 230 through a subsequent etching process, so that in the process of subsequent etching of the second dielectric layer 150 at the bottom of the first initial trench 260 The shielding layer can shield and protect the second dielectric layer 150 at the bottom of the first interconnection groove 230 .

In this embodiment, the sacrificial layer 245 fills the first interconnection trench 230, and the sidewall of the sacrificial layer 245 located on the sidewall of the first initial trench 260 is separated, that is, along the In the direction of the sidewall or bottom of an initial trench 260, the sacrificial layer 245 located on the sidewall of the first initial trench 260 is thinner, and the sacrificial layer 245 in the first interconnection trench 230 is contacted together, Along the direction perpendicular to the bottom of the first interconnection groove 230, the sacrificial layer 245 located in the first interconnection groove 230 is thicker, so that during the subsequent etching of the sacrificial layer 245, the While the sacrificial layer in the first initial trench 260 is removed, the sacrificial layer 245 located in the first interconnection groove 230 can also retain a part of its thickness as the shielding layer.

In this embodiment, since the opening line width of the first initial trench 260 is larger than the opening line width of the first interconnection trench 230, during the process of forming the sacrificial layer 245, along with the The thickness of the sacrificial layer 245 material on the bottom of the trench and the sidewall gradually increases, and the sacrificial layer 245 material on the opposite sidewall of the first interconnection trench 230 gradually contacts, and by controlling the thickness of the sacrificial layer 245 to be less than 0.5 times The opening line width of the first initial trench 260 is adjusted so that the sidewalls of the sacrificial layer 245 on opposite sidewalls of the first initial trench 260 are still separated from each other.

In this embodiment, the sacrificial layer 245 is also formed on the top and sidewalls of the hard mask layer 250 .

The sacrificial layer 245 is selected from a material that has etching selectivity with the top dielectric layer 102 and the bottom dielectric layer 101, so that after the sacrificial layer 245 is subsequently etched to form the shielding layer, the shielding layer can be used for the first interconnection trench. The second dielectric layer 150 at the bottom of 230 plays the role of protection and shielding.

In addition, after the subsequent formation of the second initial trench, the sacrificial layer 245 needs to be removed, and the sacrificial layer 245 is also selected from a material that is easy to be removed, so as to reduce the difficulty of subsequent removal of the sacrificial layer 245, improve process compatibility, and reduce the removal rate. The probability that the process of the sacrificial layer 245 will cause damage to other film structures (for example: top dielectric layer, bottom dielectric layer).

In this embodiment, the material of the sacrificial layer 245 includes amorphous carbon or amorphous germanium.

As an example, the material of the sacrificial layer 245 is amorphous carbon. Amorphous carbon is an easy-to-obtain material, which is conducive to reducing the process cost of forming the sacrificial layer 245. Moreover, the amorphous carbon can be subsequently removed by an oxidation process, which is conducive to reducing the difficulty of the subsequent process of removing the sacrificial layer 245, simplifying The process flow is improved, the process manufacturing efficiency is improved, and it is also beneficial to reduce the impact of the sacrificial layer 245 on subsequent process processes and semiconductor structures.

In this embodiment, forming the sacrificial layer 245 includes a chemical vapor deposition (CVD) process. The chemical vapor deposition process has good coverage, strong process compatibility and low process cost.

In other embodiments, based on the material of the sacrificial layer and actual process requirements, other processes may also be used to form the sacrificial layer 245 .

As shown in FIG. 6 , the sacrificial layer 245 is etched to remove the sacrificial layer 245 located on the sidewall and bottom of the first initial trench 260 , leaving the sacrificial layer filled in the first interconnection groove 230 245 is used as the shielding layer 265.

During subsequent etching of the second dielectric layer 150 at the bottom of the first initial trench 260 , the shielding layer 265 is used to shield and protect the second dielectric layer 150 at the bottom of the first interconnection groove 230 .

In this embodiment, the sacrificial layer 245 is etched using an isotropic etching process.

The isotropic etching process has isotropic etching characteristics, and can etch the sacrificial layer 245 located on the sidewall and bottom of the first initial trench 260 . Moreover, in this embodiment, since the sacrificial layer 245 located on the sidewall of the first initial trench 260 is separated from each other, the sacrificial layer 245 located in the first interconnection groove 230 fills the first interconnection groove 230, so , while the sacrificial layer 245 located in the first initial trench 260 is removed by the isotropic etching process, a part of the thickness of the sacrificial layer 245 located in the first interconnection groove 230 can also be reserved for use as the shielding layer 265 .

Moreover, in this embodiment, no photomask or mask is needed in the process of forming the shielding layer 265 , which is also beneficial to save process cost and simplify the process flow.

Specifically, the isotropic etching process may be one or both of an isotropic dry etching process and a wet etching process.

As shown in FIG. 7 , using the blocking layer 265 as a mask, the second dielectric layer 150 at the bottom of the first initial trench 260 is etched to form a The second initial trench 270 of the second interconnection layer 180 , the second initial trench 270 and the first initial trench 260 constitute the second interconnection trench 240 . The second initial trench 270 communicates with the first initial trench 260 .

In this embodiment, the process of etching the second dielectric layer 150 at the bottom of the first initial trench 260 includes an anisotropic etching process. The anisotropic etching process is beneficial to improve the accuracy of pattern transfer, thereby improving the profile quality and dimensional accuracy of the second initial trench 270 .

As shown in FIG. 8 , after forming the second initial trench 270 and before filling the first interconnection trench 230 and the second interconnection trench 240 with conductive material, the method for forming the semiconductor structure further includes: The shielding layer 265 is removed.

The shielding layer 265 is removed, thereby exposing the space of the first interconnection groove 230 , so that the first interconnection groove 230 is subsequently filled with conductive material.

In this embodiment, the shielding layer 265 is made of amorphous carbon, and the sacrificial layer 124 is removed by an oxidation process. The oxygen-containing gas in the oxidation process can react with the amorphous carbon material to generate carbon dioxide gas, which is discharged out of the reaction chamber. The removal process is simple, the process compatibility is high, and the side effects are small, which is conducive to reducing process costs and increasing production capacity.

In other embodiments, when the material of the sacrificial layer is amorphous germanium, a wet etching process is used to remove the sacrificial layer. Specifically, the wet etching process is performed using HCl vapor. In other implementations, when the material of the sacrificial layer is other materials, the sacrificial layer is removed in a corresponding process.

In this embodiment, after forming the second initial trench 270 , forming the semiconductor structure further includes: removing the hard mask layer 250 . The hard mask layer 250 is removed to reduce the thickness of the subsequent conductive material to be filled, thereby reducing the difficulty of filling the subsequent conductive material.

It should be noted that the above step of forming the second initial trench 270 is only an example. The step of forming the second initial trench 270 is not limited thereto. For example: in other embodiments, the step of forming the second initial trench includes: forming a patterned layer on the top dielectric layer, the patterned layer fills the first interconnection layer and exposes the a first initial trench; using the patterned layer as a mask to etch the second dielectric layer at the bottom of the first initial trench.

It should also be noted that in this embodiment, the second interconnection is formed by forming the first interconnection groove and the first initial trench, and then connecting the second initial trench with the first initial trench. Slots are illustrated as examples. That is to say, in this embodiment, the first interconnection groove and the second interconnection groove are respectively formed in different steps. The process steps of forming the first interconnection trench and the second interconnection trench are not limited thereto.

In other embodiments, based on the actual process, the first interconnection trench and the second interconnection trench may also be formed in the same step.

Referring to FIG. 9, conductive material is filled in the first interconnection groove 230 and the second interconnection groove 240, respectively corresponding to form a first metal line 210 and a second metal line 220, the first metal line 210 and the The conductive plug 160 is in contact with and serves as a signal line, and the second metal line 220 is in contact with the second interconnection layer 180 and is used as a power rail.

The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnection layer 170, therefore, the first metal line 210 is used to implement source-drain doping The electrical connection between the impurity region 140 and external circuits or other interconnection structures. In this embodiment, the first metal line 210 is used as a signal line for realizing signal connection between the source-drain doped region 140 and external circuits or other interconnection structures.

The second metal line 220 is in contact with the second interconnection layer 180, and the second interconnection layer 180 is in contact with the source-drain doped region 140, therefore, the second metal line 220 is used for To realize the electrical connection between the source-drain doped region 140 and external circuits or other interconnection structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source-drain doped region 140 .

The second metal line 220 is in contact with the second interconnection layer 180 and is used as a power supply line, so that the electrical connection between the power supply line and the second interconnection layer 180 does not need to be electrically connected through the conductive plug 160, which is beneficial to prevent The influence of the resistance of the conductive plug on the electrical connection performance between the power supply line and the second interconnection layer 180 optimizes the electrical connection performance between the power supply line and the second interconnection layer 180, reduces the IR drop (IR drop), The power supply efficiency of the device is improved.

Moreover, in this embodiment, the opening line width of the second interconnection groove 240 is greater than the opening line width of the first interconnection groove 230, and correspondingly, the line width of the second metal line 220 is greater than that of the first interconnection groove. The line width of a metal line 210, that is, the line width of the power supply line is larger than the line width of the signal line, which is beneficial to reduce the resistance of the power supply line, reduce IR drop, and further improve the power supply efficiency of the device.

Both the first metal wire 210 and the second metal wire 220 are conductive materials. As an example, the material of the first metal line 210 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN The material of the second metal line 220 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN.

The first metal line 210 may include a first anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the first interconnection trench 230 , and a first anti-diffusion barrier layer located on the first anti-diffusion barrier layer and filling the first The first metal layer of the interconnection groove (not shown in the figure); the second metal line 220 may include a second anti-diffusion barrier layer (not shown in the figure) located on the sidewall and bottom of the second interconnection groove 240, and A second metal layer (not shown) located on the second diffusion barrier layer and filling the second interconnection groove.

In this embodiment, the first metal line 210 and the second metal line 220 are formed in the same step, therefore, the structure of the first metal line 210 and the structure of the second metal line 220 are the same, and the first The material of the metal wire 210 is the same as that of the second metal wire 220 .

Specifically, in this embodiment, the material of the first anti-diffusion barrier layer is the same as that of the second anti-diffusion barrier layer, and the material of the first metal layer and the second metal layer is the same.

As an example, the material of the first anti-diffusion barrier layer and the material of the second anti-diffusion barrier layer are TiN; the material of the first metal layer and the second metal layer is Cu, and the resistivity of Cu is relatively high. Low, it is beneficial to reduce the RC delay in the back-end process, and Cu has excellent resistance to electromigration.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure, characterized in that, comprising: A base, the base includes a bottom dielectric layer, the bottom dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, including a first interconnection layer and a second interconnection layer spaced apart, a conductive plug in contact with the first interconnection layer is formed in the second dielectric layer on top of the first interconnection layer; a top dielectric layer located on the bottom dielectric layer; a first metal line, passing through the top dielectric layer on the top of the conductive plug and in contact with the conductive plug, the first metal line is used as a signal line; A second metal line runs through the second dielectric layer and the top dielectric layer at the top of the second interconnection layer, and is in contact with the second interconnection layer, and the second metal line is used as a power supply line. 2. The semiconductor structure according to claim 1, wherein the line width of the second metal line is larger than the line width of the first metal line. 3. The semiconductor structure according to claim 1, wherein the material of the interconnection layer comprises Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, One or more of Ti and TiN; the material of the conductive plug includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more. 4. The semiconductor structure according to claim 1, wherein the material of the first metal wire comprises Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN One or more of , Ti and TiN; the material of the second metal wire includes Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN one or more of. 5. The semiconductor structure according to claim 1, wherein the material of the bottom dielectric layer comprises one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG; the top dielectric layer The material of the layer includes one or more of SiOCH, SiOC, SiO ₂ , FSG, BSG, PSG and BPSG. 6. The semiconductor structure according to claim 1, wherein the base further comprises: a substrate, a gate structure on the substrate, and source-drain doping on both sides of the gate structure Area; The bottom dielectric layer is located above the substrate and covers the source-drain doped region; The interconnection layer is located in the first dielectric layer on the top of the source-drain doped region and is in contact with the source-drain doped region. 7. The semiconductor structure according to claim 6, wherein the material of the substrate comprises: monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and gallium indium one or more; The material of the gate structure includes: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni Any one or more. 8. The semiconductor structure according to claim 6, wherein the substrate further comprises a gate dielectric layer located between the gate structure and the channel structure; the material of the gate dielectric layer comprises: HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La ₂ O ₃ , Al ₂ O ₃ , one or more of silicon oxide and nitrogen-doped silicon oxide. 9. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate includes a bottom dielectric layer, the bottom dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer , comprising a first interconnection layer and a second interconnection layer spaced apart, a conductive plug in contact with the first interconnection layer is formed in the second dielectric layer on the top of the first interconnection layer; forming a top dielectric layer on the bottom dielectric layer; forming a first interconnect trench penetrating through the top dielectric layer on top of the conductive plug, and a second interconnect trench penetrating the second dielectric layer and the top dielectric layer on top of the second interconnect layer, the The first interconnection groove exposes the conductive plug, and the second interconnection groove exposes the second interconnection layer; Conductive material is filled in the first interconnection groove and the second interconnection groove to form a first metal line and a second metal line respectively, and the first metal line is in contact with the conductive plug and is used as a A signal line, the second metal line is in contact with the second interconnection layer and is used as a power supply line. 10 . The method for forming a semiconductor structure according to claim 9 , wherein an opening line width of the second interconnection trench is larger than an opening linewidth of the first interconnection trench. 11 . 11. The method for forming a semiconductor structure according to claim 9, wherein the step of forming the first interconnection trench and the second interconnection trench comprises: forming a plurality of trenches penetrating through the top dielectric layer, including a first interconnect groove on the top of the conductive plug and exposing the conductive plug, and a first initial trench above the second interconnect layer, the first initial trench exposes out the second medium layer; forming a second initial trench penetrating through the second dielectric layer at the bottom of the first initial trench, the second initial trench exposes the second interconnection layer, the second initial trench and the first initial trench An initial trench is used to form the second interconnect trench. 12. The method for forming a semiconductor structure according to claim 11, wherein the opening line width of the first initial trench is larger than the opening line width of the first interconnection groove; The step of forming the second initial trench includes: forming a sacrificial layer on the bottom and sidewalls of the trench, and the sacrificial layer located on the sidewall of the first interconnection trench is in contact with and fills the first interconnection trench. interconnection grooves, the sidewalls of the sacrificial layer located on the sidewalls of the first initial trenches are separated; Etching the sacrificial layer, removing the sacrificial layer located on the sidewall and bottom of the first initial trench, and leaving the sacrificial layer filled in the first interconnection groove as a shielding layer; Using the blocking layer as a mask, etching the second dielectric layer at the bottom of the first initial trench to form the second initial trench below the first initial trench. 13. The method for forming a semiconductor structure according to claim 11, wherein the step of forming the second initial trench comprises: forming a patterned layer on the top dielectric layer, the patterned layer filling the the first interconnection layer and expose the first initial trench; and use the patterned layer as a mask to etch the second dielectric layer at the bottom of the first initial trench. 14. The method for forming a semiconductor structure according to claim 12, characterized in that, after forming the second initial trench, before filling the first interconnection trench and the second interconnection trench with a conductive material, The method for forming the semiconductor structure further includes: removing the shielding layer. 15. The method for forming a semiconductor structure according to claim 12, wherein forming the sacrificial layer comprises a chemical vapor deposition process. 16. The method for forming a semiconductor structure according to claim 12, wherein an isotropic etching process is used to etch the sacrificial layer. 17. The method for forming a semiconductor structure according to claim 12, wherein the process of etching the second dielectric layer at the bottom of the first initial trench comprises an anisotropic etching process. 18. The method for forming a semiconductor structure according to claim 12, wherein the material of the sacrificial layer comprises amorphous carbon or amorphous germanium. 19. The method for forming a semiconductor structure according to claim 12, wherein the step of forming a plurality of trenches penetrating through the top dielectric layer comprises: forming a hard mask layer on the top dielectric layer, the A plurality of mask openings are formed in the hard mask layer; Using the hard mask layer as a mask, etching the top dielectric layer along the mask opening to form a plurality of trenches penetrating through the top dielectric layer; In the step of forming the sacrificial layer, the sacrificial layer is also formed on the top and sidewalls of the hard mask layer. 20. The method for forming a semiconductor structure according to any one of claims 9-19, wherein the base further comprises a substrate, a gate structure on the substrate, and a Source and drain doped regions on both sides; The bottom dielectric layer is located above the substrate and covers the source-drain doped region; the interconnection layer is located in the first dielectric layer on top of the source-drain doped region and is doped with the source-drain area in contact.

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