CN115425116A - Manufacturing method of passivation contact structure, battery, assembly and system - Google Patents

Abstract

The application is applicable to the technical field of solar cells, and provides a method for making a passivation contact structure, a cell, a component, and a system. The method for making the passivation contact structure includes: making a passivation layer on a silicon substrate; making an intrinsic layer on the passivation layer; making a co-doped source layer on the intrinsic layer, and the co-doped source layer includes a variety of doped Impurity source: The intrinsic layer is co-doped by the co-doped source layer, the intrinsic layer is transformed into a co-doped layer, and the silicon substrate forms an inner diffusion layer. In this way, co-doping the intrinsic layer by using a co-doping source layer including multiple doping sources can improve the doping effect and improve the passivation performance. Furthermore, the formed inner diffusion layer can provide field passivation, thereby reducing recombination and lowering cell decay.

Description

Manufacturing method, battery, component and system of a passivation contact structure

technical field

The present application belongs to the technical field of solar cells, and in particular relates to a method for making a passivation contact structure, a cell, an assembly, and a system.

Background technique

Solar cell power generation is a sustainable clean energy source, which can convert sunlight into electrical energy by using the photovoltaic effect of semiconductor p-n junctions.

The passivation contact structure in the related art is usually doped with a dopant source, so as to form a carrier selective contact. However, the doping effect and passivation effect are poor. For example, the atomic size difference between boron and silicon is large, making boron difficult to dope in silicon. Moreover, the diffusion coefficient and separation coefficient of boron in the silicon dioxide passivation layer are low, so that boron accumulates in the silicon dioxide passivation layer, deteriorating its passivation performance.

Based on this, how to improve the doping effect and passivation performance of the passivation contact structure has become an urgent problem to be solved.

Contents of the invention

The present application provides a method for making a passivation contact structure, a battery, a component, and a system, aiming at solving the problem of how to improve the doping effect and passivation performance of the passivation contact structure.

In the first aspect, the method for making a passivation contact structure provided by the present application includes:

Make a passivation layer on the silicon substrate;

forming an intrinsic layer on the passivation layer;

making a co-doped source layer on the intrinsic layer, the co-doped source layer including multiple doping sources;

The intrinsic layer is co-doped by using the co-doped source layer, the intrinsic layer is transformed into a co-doped layer, and the silicon substrate forms an inner diffusion layer.

Optionally, the passivation contact structure is a P-type passivation contact structure, the co-doped source layer includes a P-type co-doped source layer, and the P-type co-doped source layer includes a boron source, an aluminum source, At least two doping sources among the gallium source and the indium source.

Optionally, the passivation contact structure is an N-type passivation contact structure, the co-doped source layer includes an N-type co-doped source layer, and the N-type co-doped source layer includes a phosphorus source, an arsenic source, At least two dopant sources in the antimony source.

Optionally, making a co-doped source layer on the intrinsic layer includes:

The co-doped source layer is fabricated on the intrinsic layer by using at least one of spin coating process, PECVD process, APCVD process, LPCVD process, evaporation process, and magnetron sputtering process.

Optionally, using the co-doped source layer to co-dope the intrinsic layer includes:

The intrinsic layer is co-doped using the co-doped source layer by using a laser doping process.

Optionally, using the co-doped source layer to co-dope the intrinsic layer includes:

The intrinsic layer is co-doped using the co-doped source layer by using a thermal diffusion process.

Optionally, one side of the silicon substrate includes a plurality of alternating first regions and second regions, and the co-doped source layer includes a P-type co-doped source layer and an N-type co-doped source layer, and the The doped layer includes a P-type co-doped layer and an N-type co-doped layer, and the inner diffusion layer includes a P-type inner diffusion layer and an N-type inner diffusion layer;

Making a co-doped source layer on the intrinsic layer, comprising:

forming the P-type co-doped source layer on the intrinsic layer corresponding to the first region;

forming the N-type co-doped source layer on the intrinsic layer corresponding to the second region;

Co-doping the intrinsic layer by using the co-doped source layer includes:

Co-doping the intrinsic layer by using the P-type co-doped source layer in the first region, and converting the intrinsic layer corresponding to the first region into a P-type co-doped layer, forming the P-type inner diffusion layer on the silicon substrate corresponding to the first region;

Co-doping the intrinsic layer by using the N-type co-doped source layer in the second region, and converting the intrinsic layer corresponding to the first region into an N-type co-doped layer, The N-type inner diffusion layer is formed on the silicon substrate corresponding to the first region.

In the second aspect, in the solar cell provided by the present application, the passivation contact structure of the solar cell is made by any one of the manufacturing methods for the passivation contact structure described above.

In a third aspect, the battery assembly provided by the present application includes the above-mentioned solar battery.

In a fourth aspect, the photovoltaic system provided by the present application includes the above-mentioned battery assembly.

The manufacturing method, battery, component, and system of the passivation contact structure of the embodiment of the present application use a co-doping source layer including multiple doping sources to co-dope the intrinsic layer, which can improve the doping effect and improve the passivation performance . Furthermore, the formed inner diffusion layer can provide field passivation, thereby reducing recombination and lowering cell decay.

Description of drawings

1 is a schematic flow diagram of a method for manufacturing a passivation contact structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a scene of a manufacturing method of a passivation contact structure according to an embodiment of the present application;

3 is a schematic flow diagram of a method for manufacturing a passivation contact structure according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a scene of a manufacturing method of a passivation contact structure according to an embodiment of the present application;

Description of main component symbols:

Silicon substrate 101, first region 110, second region 120, passivation layer 11, intrinsic layer 12, co-doped source layer 13, P-type co-doped source layer 131, N-type co-doped source layer 132, Doped layer 14 , P-type co-doped layer 141 , N-type co-doped layer 142 , inner diffusion layer 15 , P-type inner diffusion layer 151 , and N-type inner diffusion layer 152 .

detailed description

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In the present application, co-doping the intrinsic layer by using a co-doping source layer including multiple doping sources can improve the doping effect and passivation performance. Furthermore, the formed inner diffusion layer can provide field passivation, thereby reducing recombination and lowering cell decay.

Embodiment one

Please refer to Fig. 1 and Fig. 2, the manufacturing method of the passivation contact structure of the embodiment of the present application, including:

Step S11: forming a passivation layer 11 on the silicon substrate 101;

Step S12: forming an intrinsic layer 12 on the passivation layer 11;

Step S13: forming a co-doped source layer 13 on the intrinsic layer 12, the co-doped source layer 13 includes multiple doping sources;

Step S14 : Co-doping the intrinsic layer 12 with the co-doped source layer 13 , the intrinsic layer 12 is transformed into a co-doped layer 14 , and the silicon substrate 101 forms an inner diffusion layer 15 .

In the manufacturing method of the passivation contact structure of the embodiment of the present application, the intrinsic layer 12 is co-doped by using the co-doping source layer 13 including multiple doping sources, which can improve the doping effect and improve the passivation performance. Furthermore, the formed inner diffusion layer 15 can provide field passivation, thereby reducing recombination and lowering cell degradation.

Specifically, the silicon substrate 101 is a P-type silicon substrate. It can be understood that in other embodiments, the silicon substrate 101 may be an N-type silicon substrate.

Specifically, in step S11, the passivation layer 11 includes an intrinsic amorphous silicon layer, an intrinsic polysilicon layer, an intrinsic nanocrystalline silicon layer, an intrinsic mixed crystal silicon layer, a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, layer, a silicon carbide layer, and a silicon oxycarbonitride layer.

Specifically, in step S11 , a passivation layer 11 may be formed on the entire surface of the silicon substrate 101 . In this way, the entire surface of the passivation layer 11 is covered, so that the passivation effect is better. It can be understood that, in other embodiments, the passivation layer 11 may also be formed locally on the silicon substrate 101 .

Further, the passivation layer 11 may have a porous structure. In this way, the doped layer 14 can be accommodated in the hole of the passivation layer 11 to form a conductive channel, so that the resistivity of the passivation layer 11 is better. Furthermore, the passivation layer 11 can be formed by additional chemical etching, dry etching or thermal diffusion shock. In this way, the passivation layer 11 has a porous structure. It can be understood that in other embodiments, the passivation layer 11 can also be distributed continuously.

Specifically, in step S11, the number of passivation layers 11 is one layer. It can be understood that in other embodiments, the number of passivation layers 11 may be 2 layers, 3 layers, 4 layers or other numbers. When the number of passivation layers 11 is multiple layers, the types of passivation layers 11 may be the same or different.

Specifically, in step S12, the intrinsic layer 12 includes an amorphous silicon layer, a polycrystalline silicon layer, a nanocrystalline silicon layer, a mixed crystal silicon layer, a silicon carbide layer, a silicon dioxide layer, a silicon oxycarbide layer, a silicon oxynitride layer, At least one of the silicon oxycarbonitride layers.

It can be understood that, in the case of forming the inner diffusion layer 15, the inner diffusion layer 15 includes a doped crystalline silicon layer, a doped amorphous silicon layer, a doped polysilicon layer, a doped nanocrystalline silicon layer, a doped mixed crystal silicon layer, At least one of a doped silicon carbide layer, a doped silicon dioxide layer, a doped silicon oxycarbide layer, a doped silicon oxynitride layer, and a doped silicon oxycarbonitride layer.

Specifically, in step S12 , the intrinsic layer 12 may be formed on the entire surface of the passivation layer 11 . In this way, the entire surface of the intrinsic layer 12 covers the passivation layer 11 , which facilitates the subsequent lamination of the co-doped source layer 13 and the doping of the intrinsic layer 12 with the co-doped source layer 13 and laser. It can be understood that, in other embodiments, the intrinsic layer 12 may also be formed locally on the passivation layer 11 .

Specifically, in step S12, the number of intrinsic layers 12 is one layer. It can be understood that in other embodiments, the number of intrinsic layers 12 may be 2 layers, 3 layers, 4 layers or other numbers. When the number of intrinsic layers 12 is multiple layers, the types of intrinsic layers 12 may be the same or different.

Specifically, in step S12, the temperature for depositing the intrinsic layer 12 is 400°C-440°C. For example, it is 400°C, 405°C, 410°C, 420°C, 430°C, 440°C. Preferably, the temperature for depositing the intrinsic layer 12 is 420°C. In this way, the temperature is lower and will not cause damage to the silicon substrate 101 .

Specifically, in step S13, the co-doping source layer 13 may include two, three, four or other numbers of doping sources. The specific number of doping sources in the co-doping source layer 13 is not limited here.

Specifically, in step S13, the number of layers of the co-doped source layer 13 may be one or more. Each co-doped source layer 13 may include one kind of doping source, or may include multiple kinds of doping sources. Further, when each layer of co-doping source layer 13 includes multiple doping sources, multiple doping sources can be mixed and distributed in the co-doping source layer 13, or multiple doping sources can be mixed in the co-doping source Layer 13 is divided into regions. The number and specific distribution of the dopant sources are not limited here.

Specifically, in step S13 , the co-doped source layer 13 can be prepared on the entire surface of the intrinsic layer 12 . In this way, the distribution area of the co-doped source layer 13 is larger, which is convenient for subsequent doping by laser. Moreover, no mask is required to prepare the co-doped source layer 13 on the entire surface, which is beneficial to improve the production efficiency.

It can be understood that in other embodiments, the co-doped source layer 13 can also be prepared in a partial region of the intrinsic layer 12 . In other words, the co-doped source layer 13 is formed with hollowed-out regions distributed intermittently on the intrinsic layer 12 .

Specifically, in step S14 , the entire region of the intrinsic layer 12 may be doped, or a partial region of the intrinsic layer 12 may be doped. It can be understood that the area of the co-doped layer 14 and the inner diffusion layer 15 can be controlled by controlling the area of the co-doped source layer 13 , so as to control the area of the passivation contact structure. The specific region of co-doping is not limited here.

Specifically, steps S11 - S14 may be performed on both sides of the silicon substrate 101 to form passivation contact structures with two polarities. The solar cell thus produced is a double-sided contact solar cell. Please note that both sides of the silicon substrate 101 can form a localized passivation contact structure; one side can form a localized passivation contact structure, and the other side can form a whole-surface passivation contact structure; both sides can form a whole-surface passivation contact structure. Domain passivation contact structure.

It can be understood that in other embodiments, passivation contact structures with two polarities can also be formed on one side of the silicon substrate 101 . The solar cell thus produced is a back contact solar cell.

Specifically, after step S14, the co-doped source layer 13 may also be removed. In this way, the co-doped source layer 13 can avoid adverse effects on the subsequent steps of manufacturing solar cells.

Further, acid solution may be used to remove the co-doped source layer 13 . Furthermore, the acid solution is hydrofluoric acid. In this way, the co-doped source layer 13 can be efficiently removed.

Furthermore, the concentration of the acid solution is 0.1%-50%. For example, it is 0.1%, 0.5%, 1%, 10%, 25%, 40%, 50%. In this way, the concentration of the acid solution is in an appropriate range, which can avoid the poor effect of removing the co-doped source layer 13 caused by too low concentration of the acid solution, and avoid damage to the silicon wafer caused by too high concentration of the acid solution.

Furthermore, the acid solution can be applied to the dopant source layer 13, and the dopant source layer 13 can also be immersed in the acid solution. The specific way of using the acid solution is not limited here.

Specifically, after removing the co-doped source layer 13, the remaining intrinsic layer 12 may also be removed. In this way, it is possible to prevent the remaining intrinsic layer 12 from adversely affecting the subsequent steps of fabricating the solar cell.

Further, alkaline solution may be used to remove the remaining intrinsic layer 12 . In this way, the difference in etching rates between the intrinsic layer 12 and the co-doped layer 14 can be utilized to remove the intrinsic layer 12 and retain the co-doped layer 14 .

Furthermore, the lye is NaOH solution, KOH solution or a mixture thereof. In this way, the remaining intrinsic layer 12 can be efficiently removed.

Furthermore, the concentration of the lye is 1%-50%. For example, 1%, 5%, 10%, 25%, 40%, 50%. In this way, the concentration of the lye is in an appropriate range, which can avoid the poor effect of removing the intrinsic layer 12 caused by the too low concentration of the lye, and avoid damage to the silicon wafer caused by the too high concentration of the lye.

Furthermore, the alkali solution can be applied to the intrinsic layer 12, and the intrinsic layer 12 and the co-doped layer 14 can also be immersed in an acid solution. The specific way of using the lye is not limited here. It can be understood that in other embodiments, the remaining intrinsic layer 12 may also be retained.

Specifically, before step S11, the silicon substrate 101 may be cleaned and textured. In this way, the suede is formed to reduce the reflection of sunlight, which is conducive to improving the photoelectric conversion rate of the battery.

Specifically, after step S14, a surface passivation layer and a circuit may also be fabricated. In this way, a solar cell is realized.

Further, the surface passivation layer can be fabricated on both sides. The surface passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The number of layers of the surface passivation layer can be 1 layer, 2 layers, 3 layers or other numbers. The specific position distribution, specific type and specific quantity of the surface passivation layer are not limited here.

Further, the circuit can be made by screen printing process. In this way, the efficiency and precision are higher, which is conducive to improving the quality of the solar cell. It can be understood that in other embodiments, sputtering, electroplating and other processes can also be used to fabricate circuits.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment two

In some optional embodiments, the passivation contact structure is a P-type passivation contact structure, the co-doped source layer 13 includes a P-type co-doped source layer 131, and the P-type co-doped source layer 131 includes a boron source, an aluminum source , gallium source, indium source at least two doping sources.

In this way, at least two doping sources are used to form the P-type co-doped source layer 131, and the P-type co-doped source layer 131 is used as a hole selective contact layer, which can improve the doping effect and passivation of the P-type passivation contact structure. performance. Moreover, a variety of doping sources are provided to adapt to more application scenarios.

In one example, the P-type co-doped source layer 131 is a boron-aluminum co-doped source layer; in another example, the P-type co-doped source layer 131 is a boron-gallium co-doped source layer; in yet another example , the P-type co-doped source layer 131 is a boron-indium co-doped source layer; in another example, the P-type co-doped source layer 131 is an aluminum-gallium co-doped source layer; in another example, the P-type co-doped source layer The doping source layer 131 is an aluminum-indium co-doping source layer; in another example, the P-type co-doping source layer 131 is a gallium-indium co-doping source layer; in another example, the P-type co-doping source layer 131 is a boron-aluminum-gallium co-doped source layer; in another example, the P-type co-doped source layer 131 is a boron-aluminum-indium co-doped source layer; in another example, the P-type co-doped source layer 131 is Boron indium gallium co-doped source layer; in another example, the P-type co-doped source layer 131 is an aluminum indium gallium co-doped source layer; in yet another example, the P-type co-doped source layer 131 is boron-aluminum InGa co-doped source layer.

Preferably, the P-type co-doped source layer 131 is a boron-gallium co-doped source layer. In this way, the atomic size of gallium and silicon is similar, the diffusion coefficient of the passivation layer 11 is high, and the separation coefficient of gallium ([Ga]Si/[Ga]SiO2) is high, which can prevent gallium from gathering in the passivation layer 11, thereby avoiding The deterioration of passivation performance is conducive to improving doping efficiency and passivation performance. Since boron is doped and gallium is doped at the same time, the recombination of B-O pairs formed in the inner diffusion layer 15 in the silicon substrate 101 can be reduced, thereby reducing battery attenuation. It can be understood that if only boron is doped, the inner diffusion layer will form B-O pair recombination in the silicon substrate, resulting in battery attenuation.

Preferably, the P-type co-doped source layer 131 is an Al-In co-doped source layer. In this way, the doping efficiency and passivation performance can also be improved, and the battery attenuation can be reduced.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment three

In some optional embodiments, the passivation contact structure is an N-type passivation contact structure, the co-doped source layer 13 includes an N-type co-doped source layer 132, and the N-type co-doped source layer 132 includes a phosphorus source, an arsenic source , at least two doping sources in the antimony source.

In this way, at least two doping sources are used to form the N-type co-doped source layer 132, and the N-type co-doped source layer 132 is used as an electron selective contact layer, which can improve the doping effect and passivation of the N-type passivation contact structure. performance. Moreover, a variety of doping sources are provided to adapt to more application scenarios.

In one example, the N-type co-doped source layer 132 is a phosphorus-arsenic co-doped source layer; in another example, the N-type co-doped source layer 132 is a phosphorus-antimony co-doped source layer; in yet another example , the N-type co-doped source layer 132 is an arsenic-antimony co-doped source layer; in another example, the N-type co-doped source layer 132 is a phosphorus-arsenic-antimony co-doped source layer.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment four

In some optional embodiments, step S13 includes:

Co-doped source layer 13 is formed on intrinsic layer 12 by using at least one of spin coating process, PECVD process, APCVD process, LPCVD process, evaporation process, and magnetron sputtering process.

In other words, one, two, three, four, five or all of the aforementioned processes can be used to fabricate the co-doped source layer 13 .

In this way, various manufacturing methods of the co-doped source layer 13 are provided, which can adapt to more application scenarios.

Specifically, the spin-coating process can coat the liquid doping source on the intrinsic layer 12, so that the co-doping source layer 13 has a higher density and a more uniform thickness, which is beneficial to improving the effect of subsequent co-doping.

Specifically, the PECVD process is a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition). The basic temperature required by the PECVD process is low, which can avoid high temperature damage to the silicon wafer. Moreover, the film formation quality of the PECVD process is good, which is conducive to improving the quality of the co-doped source layer 13, so that the effect of subsequent co-doping is better.

Specifically, the APCVD process is atmospheric pressure chemical vapor deposition (Atmospheric Pressure Chemical Vapor Deposition), which has a fast reaction speed and can improve the production efficiency of the co-doped source layer 13, thereby improving the production efficiency of the passivation contact structure.

Specifically, the LPCVD process is Low Pressure Chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition).

Specifically, the evaporation process can make the co-doped source layer 13 have higher purity and compactness, which is beneficial to improve the effect of subsequent co-doping.

Specifically, the magnetron sputtering process can fabricate the co-doped source layer 13 in a large area, and make the co-doped source layer 13 have stronger adhesion, which is beneficial to improve the effect of subsequent co-doping.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment five

In some optional embodiments, step S14 includes:

The intrinsic layer 12 is co-doped by using the laser doping process and using the co-doped source layer 13 .

In this way, laser co-doping can form a passivation contact structure without high-temperature annealing, which can reduce damage to the silicon substrate 101 caused by high temperature, and reduce the manufacturing cost of the passivation contact structure.

Specifically, the whole region of the intrinsic layer 12 can be co-doped by laser, or a partial region of the intrinsic layer 12 can be co-doped by laser. It can be understood that the area of the co-doped layer 14 and the inner diffusion layer 15 can be controlled by controlling the area of laser doping, thereby controlling the area of the passivation contact structure. The specific region of laser doping is not limited here.

Specifically, laser doping is performed at room temperature. In this way, there is no high temperature diffusion of 800-1000° C., which will not cause the doping process to deteriorate the bulk lifetime of the silicon substrate 101 , and the laser doping acts on the intrinsic layer 12 without harmful effects on the silicon substrate 101 .

Specifically, the laser can be purple light or green light. Further, the wavelength of the laser can be 430nm-540nm. For example, it is 430nm, 450nm, 480nm, 500nm, 520nm, 540nm. In this way, the wavelength of the laser is in an appropriate range, and the poor doping effect caused by too small or too large wavelength is avoided.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment six

In some optional embodiments, step S14 includes:

The intrinsic layer 12 is co-doped with the co-doped source layer 13 by using a thermal diffusion process.

In this way, the intrinsic layer 12 can also be co-doped with the co-doped source layer 13 .

Specifically, the temperature of the thermal diffusion process is 800-1000°C. For example, it is 800°C, 820°C, 850°C, 900°C, 950°C, or 1000°C. In this way, the temperature of the thermal diffusion process is in an appropriate range, so that the effect of co-doping is better.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment seven

3 and 4, in some optional embodiments, one side of the silicon substrate 101 includes a plurality of staggered first regions 110 and second regions 120, and the co-doped source layer 13 includes a P-type co-doped source Layer 131 and N-type co-doped source layer 132, doping layer 14 includes P-type co-doped layer 141 and N-type co-doped layer 142, and inner diffusion layer 15 includes P-type inner diffusion layer 151 and N-type inner diffusion layer 152; Step S13 includes:

Step S131: forming a P-type co-doped source layer 131 on the intrinsic layer 12 corresponding to the first region 110;

Step S132: forming an N-type co-doped source layer 132 on the intrinsic layer 12 corresponding to the second region 120;

Step S14 includes:

Step S141: Use the P-type co-doped source layer 131 in the first region 110 to co-dope the intrinsic layer 12, and the intrinsic layer 12 corresponding to the first region 110 is transformed into a P-type co-doped layer 141. The silicon substrate 101 corresponding to a region 110 forms a P-type inner diffusion layer 151;

Step S142: Use the N-type co-doped source layer 132 in the second region 120 to co-dope the intrinsic layer 12, and the intrinsic layer 12 corresponding to the first region 110 is transformed into an N-type co-doped layer 142. An N-type inner diffusion layer 152 is formed on the silicon substrate 101 corresponding to a region 110 .

In this way, a passivation contact structure with two polarities is formed on one side of the silicon substrate 101, and the solar cell manufactured in this way is a back contact solar cell. Moreover, the passivation layer 11 and the intrinsic layer 12 are only grown once, the process is relatively simple, and the patterning of the two passivation contact structures can be realized efficiently.

Specifically, "one side of the silicon substrate 101 includes a plurality of interlaced first regions 110 and second regions 120" means that on one side of the silicon substrate 101, a first region 110 is formed between adjacent two first regions 110. In the second area 120 , the first area 110 is formed between two adjacent second areas 120 .

Please note that only part of the structure of the silicon substrate 101 is shown in FIG. 2. The number of regions 120 is limited.

Specifically, the P-type co-doped source layer 131 and the N-type co-doped source layer 132 are in contact with each other. In this way, reducing the use of masks is beneficial to improving production efficiency, and patterning can be realized through subsequent lasers. It can be understood that, in other embodiments, for example, in the case of using a thermal diffusion process for doping, a gap may also be formed between the P-type co-doped source layer 131 and the N-type co-doped source layer 132 . In this way, it is ensured that the subsequently formed P-type passivation contact structure and N-type passivation contact structure are separated by the silicon substrate 101 and/or the intrinsic layer 12 .

Specifically, in step S131, the P-type co-doped source layer 131 can be fully prepared on the intrinsic layer 12 of the first region 110, and the P-type co-doped source layer 131 can also be locally prepared on the intrinsic layer 12 of the first region 110. type co-doped source layer 131 .

Specifically, in step S132, the N-type co-doped source layer 132 can be fully prepared on the intrinsic layer 12 of the second region 120, and the N-type co-doped source layer 132 can also be locally prepared on the intrinsic layer 12 of the second region 120. type co-doped source layer 132 .

Specifically, in step S141, local doping can be performed on the middle region of the first region 110, and a P-type co-doped layer 141 is formed in the intrinsic layer 12 corresponding to the middle region of the first region 110. The silicon substrate 101 corresponding to the middle region of 110 forms a P-type inner diffusion layer 151; in step S142, the middle region of the second region 120 can be locally doped, and the intrinsic Layer 12 forms an N-type co-doped layer 142 , and an N-type inner diffusion layer 152 is formed in the silicon substrate 101 corresponding to the middle region of the second region 120 . In this way, the P-type passivation contact structure and the N-type passivation contact structure are separated by the silicon substrate 101 and/or the intrinsic layer 12 to avoid short circuit.

It can be understood that, in other embodiments, the first region 110 can also be fully doped with a laser, and the P-type co-doped layer 141 is formed in the entire region of the intrinsic layer 12 corresponding to the first region 110. The silicon substrate 101 corresponding to the entire region 110 forms a P-type inner diffusion layer 151; in step S142, the second region 120 can be locally doped with a laser, and the intrinsic layer 12 corresponding to the second region 120 An N-type co-doped layer 142 is formed in a part of the region, and an N-type inner diffusion layer 152 is formed in the silicon substrate 101 corresponding to a part of the second region 120 . In this way, by locally doping the second region 120, a space is formed between the P-type co-doped layer 141 and the N-type co-doped layer 142, and the P-type inner diffusion layer 151 and the N-type co-doped layer 142 are separated. space between.

In other embodiments, the first region 110 can also be locally doped by laser, and the P-type co-doped layer 141 is formed in the partial region of the intrinsic layer 12 corresponding to the first region 110, and the first region 110 A P-type inner diffusion layer 151 is formed on the silicon substrate 101 corresponding to a part of the region; in step S142, the second region 120 can be fully doped with a laser, and formed in the entire region of the intrinsic layer 12 corresponding to the second region 120. The N-type co-doped layer 142 forms an N-type inner diffusion layer 152 on the silicon substrate 101 corresponding to the entire second region 120 . In this way, by locally doping the first region 110, a space is formed between the P-type co-doped layer 141 and the N-type co-doped layer 142, and the P-type inner diffusion layer 151 and the N-type co-doped layer 142 are separated. space between.

Specifically, in step S131, a P-type co-doped source layer 131 can be formed on the intrinsic layer 12 corresponding to the first region 110 and the second region 120; the P-type co-doped source layer 131 in the second region 120 can be removed . It can be understood that, in other embodiments, the second region 120 may also be covered with a mask, and then the P-type co-doped source layer 131 is prepared, so as to realize the preparation of the P-type co-doped source layer 131 in the first region 110 .

Similarly, in step S132, an N-type co-doped source layer 132 can be formed on the intrinsic layer 12 corresponding to the first region 110 and the second region 120; the N-type co-doped source layer 132 in the first region 110 can be removed . It can be understood that in other embodiments, the first region 110 may also be covered with a mask, and then the N-type co-doped source layer 132 is prepared, so as to realize the preparation of the N-type co-doped source layer 132 in the second region 120 .

Please note that step S131 and step S132 can be performed at the same time, or step S131 can be performed first, and then step S132 can be performed. Step S141 and step S142 can be performed at the same time, or step S141 can be performed first, and then step S142 can be performed. It is also possible to execute step S131 and step S141 first, and then execute step S132 and step S142, or to execute step S132 and step S142 first, and then execute step S131 and step S141. The specific order of each step is not limited here.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment Eight

In the solar cell of the embodiment of the present application, the passivation contact structure is made by using the manufacturing method of any one of the passivation contact structure of the first embodiment to the seventh embodiment.

In the solar cell of the embodiment of the present application, the intrinsic layer 12 is co-doped by using the co-doping source layer 13 including multiple doping sources, which can improve the doping effect and passivation performance. Furthermore, the formed inner diffusion layer 15 can provide field passivation, thereby reducing recombination and lowering cell degradation.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment nine

The battery assembly of the embodiment of the present application includes the solar cell of the eighth embodiment.

In the battery assembly of the embodiment of the present application, the intrinsic layer 12 is co-doped by using the co-doping source layer 13 including multiple doping sources, which can improve the doping effect and passivation performance. Furthermore, the formed inner diffusion layer 15 can provide field passivation, thereby reducing recombination and lowering cell degradation.

In this embodiment, the solar cells in the battery module can be connected in series to form a battery string, so as to realize the serial confluence output of the current, for example, by setting up welding strips (bus bars, interconnection bars), conductive backplanes, etc. and so on to realize the serial connection of battery slices.

It is understood that in such an embodiment, the cell assembly may also include a metal frame, a back sheet, a photovoltaic glass, and an adhesive film. The adhesive film can be filled between the front and back of the solar cell, photovoltaic glass, adjacent battery sheets, etc. As a filler, it can be a transparent colloid with good light transmission performance and aging resistance. For example, the adhesive film can be EVA adhesive film Or POE film, which can be selected according to the actual situation, and is not limited here.

Photovoltaic glass can be covered on the adhesive film on the front of the solar cell. Photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and has superior physical, mechanical and optical properties. For example, ultra-clear glass The light transmittance can reach more than 92%, which can protect the solar cell without affecting the efficiency of the solar cell as much as possible. At the same time, the adhesive film can bond the photovoltaic glass and the solar cell together, and the existence of the adhesive film can seal and insulate the solar cell and prevent water and moisture.

The back sheet can be attached to the adhesive film on the back of the solar cell. The back sheet can protect and support the solar cell. It has reliable insulation, water resistance and aging resistance. There are multiple options for the back sheet, usually tempered Glass, plexiglass, aluminum alloy TPT composite film, etc., the details can be set according to specific conditions, and are not limited here. The whole composed of backplane, solar cell, adhesive film and photovoltaic glass can be set on the metal frame, and the metal frame is the main external support structure of the whole battery module, and can support and install the battery module stably. The frame mounts the battery pack where it needs to be mounted.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

Embodiment ten

The photovoltaic system of the embodiment of the present application includes the battery assembly of the ninth embodiment.

In the photovoltaic system of the embodiment of the present application, the intrinsic layer 12 is co-doped by using the co-doping source layer 13 including multiple doping sources, which can improve the doping effect and passivation performance. Furthermore, the formed inner diffusion layer 15 can provide field passivation, thereby reducing recombination and lowering cell degradation.

In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, and solar cars. , solar buildings and more. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited thereto, that is to say, the photovoltaic system can be applied in all fields that need to use solar energy for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system can include photovoltaic arrays, combiner boxes and inverters. The photovoltaic array can be an array combination of multiple battery components. For example, multiple battery components can form multiple photovoltaic arrays. The photovoltaic arrays are connected The combiner box can combine the current generated by the photovoltaic array. The combined current flows through the inverter and converts it into the alternating current required by the mains grid, and then connects to the mains network to realize solar power supply.

For other explanations and illustrations about this embodiment, reference may be made to other parts of this document, and details are not repeated here to avoid redundancy.

The above are only preferred embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the application should be included in the protection scope of the application. Inside. Moreover, the specific features, structures, materials or features described in each embodiment or example of the present application may be combined in any one or more embodiments or examples in an appropriate manner.

Claims (10)

1. A method for fabricating a passivated contact structure, comprising:

manufacturing a passivation layer on a silicon substrate;

manufacturing an intrinsic layer on the passivation layer;

manufacturing a co-doping source layer on the intrinsic layer, wherein the co-doping source layer comprises a plurality of doping sources;

and co-doping the intrinsic layer by using the co-doping source layer, converting the intrinsic layer into a co-doping layer, and forming an inner diffusion layer on the silicon substrate.

2. The method for manufacturing the passivation contact structure according to claim 1, wherein the passivation contact structure is a P-type passivation contact structure, the co-doping source layer comprises a P-type co-doping source layer, and the P-type co-doping source layer comprises at least two doping sources selected from a boron source, an aluminum source, a gallium source and an indium source.

3. The method for manufacturing the passivation contact structure of claim 1, wherein the passivation contact structure is an N-type passivation contact structure, the co-doping source layer comprises an N-type co-doping source layer, and the N-type co-doping source layer comprises at least two doping sources selected from a phosphorus source, an arsenic source and an antimony source.

4. The method of claim 1, wherein fabricating a co-dopant source layer on the intrinsic layer comprises:

and manufacturing the co-doping source layer on the intrinsic layer by adopting at least one of a spin coating process, a PECVD process, an APCVD process, an LPCVD process, an evaporation process and a magnetron sputtering process.

5. The method of claim 1, wherein co-doping the intrinsic layer with the co-dopant source layer comprises:

and co-doping the intrinsic layer by using the co-doping source layer by adopting a laser doping process.

6. The method of claim 1, wherein co-doping the intrinsic layer with the co-dopant source layer comprises:

and co-doping the intrinsic layer by using the co-doping source layer by adopting a thermal diffusion process.

7. The method for manufacturing the passivated contact structure according to claim 1, wherein one side of the silicon substrate comprises a plurality of first regions and second regions which are staggered, the co-doping source layers comprise P-type co-doping source layers and N-type co-doping source layers, the doping layers comprise P-type co-doping layers and N-type co-doping layers, and the inter-diffusion layers comprise P-type inter-diffusion layers and N-type inter-diffusion layers;

fabricating a co-dopant source layer on the intrinsic layer, comprising:

manufacturing the P type co-doping source layer on the intrinsic layer corresponding to the first region;

manufacturing the N-type co-doping source layer on the intrinsic layer corresponding to the second region;

codoping the intrinsic layer with the codoping source layer, comprising:

co-doping the intrinsic layer by using the P-type co-doping source layer in the first region, converting the intrinsic layer corresponding to the first region into a P-type co-doping layer, and forming the P-type inner diffusion layer on the silicon substrate corresponding to the first region;

and co-doping the intrinsic layer by using the N-type co-doping source layer in the second region, converting the intrinsic layer corresponding to the first region into an N-type co-doping layer, and forming the N-type inner diffusion layer on the silicon substrate corresponding to the first region.

8. A solar cell, wherein the passivated contact structure of the solar cell is manufactured by the method for manufacturing the passivated contact structure according to any one of claims 1 to 7.

9. A battery module comprising the solar cell of claim 8.

10. A photovoltaic system comprising the cell assembly of claim 9.

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