CN115274560B

CN115274560B - Method for manufacturing semiconductor structure and semiconductor structure

Info

Publication number: CN115274560B
Application number: CN202110482618.6A
Authority: CN
Inventors: 于业笑; 刘忠明
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2024-08-02
Anticipated expiration: 2041-04-30
Also published as: CN115274560A

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, wherein the manufacturing method comprises the following steps: providing a substrate, wherein an active region is arranged in the substrate, and the top surface of the active region comprises a central region and edge regions at least positioned on two opposite sides of the central region; etching the substrate to form a contact hole, wherein the contact hole exposes the top surface of the active region; forming a contact stud, wherein the contact stud is positioned in the contact hole, contacts the central region of the active region, and exposes at least one edge region of the active region; etching part of the active region by taking the contact column as a mask so that the active region is provided with a protruding part, and the protruding part is opposite to the contact column; and forming a contact layer, wherein the contact layer fills the contact hole and contacts with the side wall of the protruding part. The embodiment of the invention can improve the operation rate of the semiconductor structure.

Description

Method for manufacturing semiconductor structure and semiconductor structure

Technical Field

Embodiments of the present invention relate to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.

Background

A DRAM (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory widely used in computer systems, and generally includes structures such as capacitors, bit lines, word lines, and active areas, and the main principle of the DRAM is to represent a binary bit (bit) by using the charge stored in the capacitors.

The development of DRAM pursues high integration density and high speed, however, as the size of semiconductor structures is reduced, the charge transfer amount inside DRAM is smaller. When the amount of transferred charge per unit time is small, the operation rate of the DRAM is slow. Thus, the current operating speed of semiconductor structures is still to be further improved.

Disclosure of Invention

The technical problem solved by the embodiment of the invention is to provide a manufacturing method of a semiconductor structure and the semiconductor structure so as to improve the operation rate of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein an active region is arranged in the substrate, and the top surface of the active region comprises a central region and edge regions at least positioned on two opposite sides of the central region; etching the substrate to form a contact hole, wherein the contact hole exposes the top surface of the active region; forming a contact stud, wherein the contact stud is positioned in the contact hole, contacts the central region of the active region, and exposes at least one edge region of the active region; etching part of the active region by taking the contact column as a mask so that the active region is provided with a protruding part, and the protruding part is opposite to the contact column; and forming a contact layer, wherein the contact layer fills the contact hole and contacts with the side wall of the protruding part.

In addition, before forming the contact post, the method further comprises the following steps: forming a side wall layer positioned on the side wall of the contact hole, wherein the orthographic projection of the side wall layer in the same contact hole on the top surface of the active region is at least adjacent to the central region; the method for forming the contact post comprises the following steps: forming a contact column filling the contact hole, wherein the contact column is contacted with the side wall layer; after the contact posts are formed, before the protruding portions are formed, the method further comprises the steps of: and removing the side wall layer.

In addition, the side wall layer at least exposes the central area, and the contact column is formed by an epitaxial growth method, wherein the material of the contact column is a semiconductor material; the method for forming the contact layer comprises the following steps: and forming a contact layer filling the contact hole, wherein the contact layer is contacted with the contact column.

In addition, the active region is provided with doping ions, and the doping type of the doping ions is N type or P type; the forming of the contact post further comprises: carrying out ion doping treatment on the contact column, wherein the doping type of the ion doping treatment is the same as that of the doping ions in the active region; after the ion doping treatment, the method further comprises the following steps: and carrying out annealing treatment on the contact column.

In addition, the side wall layer at least exposes the central region; and forming the contact column on the top surface of the active region exposed by the side wall layer through a deposition process, wherein the contact column is contacted with the side wall layer.

In addition, the material of the contact post is conductive material; the method for forming the contact layer comprises the following steps: and forming the contact layer filling the contact hole, wherein the contact layer is contacted with the contact column.

In addition, the material of the contact post is an insulating material; after forming the protruding portion, before forming the contact layer, the method further includes: and removing the contact posts.

In addition, the side wall layer also covers the bottom of the contact hole, and the side wall layer in the same contact hole encloses a groove; the step of forming the contact stud includes: forming a first contact column filling the groove through a deposition process; after the first contact post is formed, the side wall layer positioned on the side wall of the contact hole is removed, the side wall layer positioned at the bottom of the contact hole is used as a second contact post, the second contact post is opposite to the first contact post, and the second contact post and the first contact post form the contact post.

In addition, the material of the side wall layer comprises titanium nitride; and removing the side wall layer by wet etching, wherein the wet etching reagent comprises hydrogen peroxide and sulfuric acid.

In addition, in the step of etching part of the active region, the ratio of the etching depth to the etching width of the active region is 5:1.

In addition, after the contact layer is formed, the method further comprises: forming an initial bit line conductive layer and an initial bit line cover layer which are stacked on the contact layer; and patterning the initial bit line conductive layer and the initial bit line cover layer to form a bit line conductive layer and a bit line cover layer.

The embodiment of the invention also provides a semiconductor structure, which comprises: the substrate is internally provided with an active area, and the top surface of the active area comprises a central area and edge areas at least positioned at two sides of the central area; the active area is provided with a protruding part, the top surface of the protruding part is positioned in the central area, and the top surface of the protruding part is at least higher than one edge area; and the contact layer is contacted with the side wall of the convex part.

In addition, the method further comprises the steps of: the top surface of the boss is higher than the two edge regions.

In addition, in the direction perpendicular to the top surface of the substrate, the thickness of the protruding part is 8-12 nm; the width of the convex part is 8-12 nm in the direction vertical to the side wall of the substrate.

In addition, the method further comprises the steps of: and the contact column is opposite to and in contact with the convex part, and the contact layer is also positioned on the side wall of the contact column.

In addition, the doping ions are arranged in the active region and the contact column, and the doping type of the doping ions of the active region is the same as that of the doping ions of the contact column.

In addition, the method further comprises the steps of: and a bit line conducting layer and a bit line covering layer which are arranged on the contact layer in a laminated mode.

Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:

In the embodiment of the invention, a contact post is formed on the top surface of the active region, the contact post is contacted with the central region of the active region, and at least one edge region of the active region is exposed; etching part of the active region by taking the contact column as a mask so as to enable the active region to be provided with a convex part; compared with a plane, the convex part not only has a top surface, but also has two opposite side surfaces, so that the convex part can increase the surface area of the active region; and forming a contact layer in contact with the side wall of the protruding part, wherein the larger surface area of the protruding part can reduce the contact resistance between the active region and the contact layer, so that the charge transmission quantity is increased, and the running speed of the semiconductor structure is improved.

In addition, the contact pillars are formed on the active region by an epitaxial growth method, and the doping ion types of the contact pillars are the same as those of the active region, so that the contact pillars can be regarded as part of the active region, and the contact area between the contact layer and the active region is further increased, so that the running speed of the semiconductor structure is greatly improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 20 are schematic structural views corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

Fig. 21 to 24 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As known from the background art, the operation speed of semiconductor structures is still to be further improved. Referring to fig. 1, fig. 1 is a schematic view of a semiconductor structure. The semiconductor structure includes: the substrate 40, the contact structure 420, the bit line conductive layer 450 and the bit line capping layer 460, wherein the substrate 40 comprises an active region 401 and an isolation structure 402 for isolating the active region 401. The active region 401 is electrically connected to the bit line conductive layer 450 through the contact structure 420.

The surface of active region 401 in contact with contact structure 420 is planar, i.e., there is no raised structure. As the dimensions of semiconductor structures shrink, the area of the surface of active region 401 in contact with contact structure 420 becomes smaller, thereby increasing the contact resistance of active region 401 with contact structure 420; when the contact resistance is large, the amount of transferred charge of the active region 401 and the bit line conductive layer 450 is small, i.e., the current is small, and the small current limits the operation rate of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: forming a contact pillar on the top surface of the active region, wherein the top surface of the active region comprises a central region and an edge region, the contact pillar is contacted with the central region of the active region and exposes at least one edge region of the active region; etching part of the active region by taking the contact column as a mask so as to enable the active region to be provided with a convex part; a contact layer is formed in contact with the sidewalls of the raised portions. Compared with a plane, the convex part can increase the contact area of the active region and the contact layer, thereby reducing the contact resistance, further increasing the charge transmission quantity and improving the operation speed of the semiconductor structure.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments.

An embodiment of the present invention provides a method for manufacturing a semiconductor structure, and fig. 2 to 20 are schematic structural diagrams corresponding to each step in the method for manufacturing a semiconductor structure according to the present embodiment. The following will make a detailed description with reference to the accompanying drawings.

Referring to fig. 2-4, fig. 3 and 4 are top views of the active region of fig. 2, providing a substrate 10 having an active region 101 therein, the top surface of the active region 101 including a central region 1011 and edge regions 1012 located at least on opposite sides of the central region 1011.

Specifically, the material of the substrate 10 may include silicon, silicon carbide, silicon nitride, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), silicon carbide, silicon germanium, gallium arsenide, indium gallium, or the like; in the present embodiment, the material of the substrate 10 is a silicon material.

The material of the active region 101 is a semiconductor, and the material type of the semiconductor may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, or the like. In this embodiment, the material of the active region 101 is silicon, and the active region 101 has doped ions, and the doping type of the doped ions is N-type or P-type. The N-type doping ions can be phosphorus, arsenic or antimony, and the P-type doping ions can be boron, indium or gallium.

In this embodiment, referring to fig. 3, the top surface of the active region 101 includes a central region 1011 and two edge regions 1012, and the central region 1011 is located between the two edge regions 1012.

In other embodiments, referring to fig. 4, the top surface of active region 101 includes a central region 1011 and an edge region 1012 surrounding central region 1011.

With continued reference to fig. 2, the substrate 10 may further have an isolation structure 102 therein, where the isolation structure 102 is used to isolate adjacent active regions 101, and the isolation structure 102 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride.

In this embodiment, the substrate 10 further has a first insulating layer 103, a conductive layer 104, and a second insulating layer 105 stacked thereon. The first insulating layer 103 can protect the surface of the substrate 10 to avoid the surface of the substrate 10 from being damaged in the subsequent etching process; the material of the first insulating layer 103 is an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride. The conductive layer 104 is electrically connected with a bit line conductive layer formed later; the material of the conductive layer 104 may be polysilicon. The second insulating layer 105 can protect the surface of the conductive layer 104 to avoid the conductive layer 104 from being damaged in the subsequent etching process; the material of the second insulating layer 105 may be silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride.

Referring to fig. 5, the substrate 10 is etched to form contact holes 106, and the contact holes 106 expose the top surfaces of the active regions 101.

Specifically, the portion of the active region 101 and the portion of the isolation structure 102 within the substrate 10 are removed by dry etching. In this embodiment, before etching the substrate 10, portions of the first insulating layer 103, the conductive layer 104, and the second insulating layer 105 are also etched so that the contact hole 106 also penetrates the first insulating layer 103, the conductive layer 104, and the second insulating layer 105.

In this embodiment, the bottom of the contact hole 106 is a plane, i.e. the top surface of the exposed active region 101 is a plane, in other words, the center region 1011 (refer to fig. 3) and the edge region 1012 (refer to fig. 3) of the exposed active region 101 are at the same height.

Referring to fig. 6-10, a sidewall layer 110 is formed on a sidewall of the contact hole 106, and an orthographic projection of the sidewall layer 110 in the same contact hole 106 on a top surface of the active region 101 is at least adjacent to the central region 1011.

The sidewall layer 110 is used to define specific positions of subsequently formed contact pillars, that is, other regions in the contact hole 106 except for the region occupied by the sidewall layer 110 are regions occupied by the contact pillars.

The material of the side wall layer 110 has larger density, and the side wall layer 110 has a smooth surface, so that the subsequently formed contact column has better surface morphology, and the contact resistance between the contact column and the subsequently formed contact layer can be reduced. In addition, the material of the sidewall layer 110 has greater adhesion with the contact hole 106, so that the firmness of the sidewall layer 110 can be improved. In this embodiment, the material of the sidewall layer 110 is titanium nitride. In other embodiments, the material of the sidewall layer may also be silicon nitride.

Specifically, referring to fig. 6, an initial sidewall layer 111 is formed at the bottom and sidewall of the contact hole 106, and the initial sidewall layer 111 is further located on the top surface of the second insulating layer 105.

In this embodiment, the initial sidewall layer 111 is formed by an atomic layer deposition process. The atomic layer deposition process can improve the uniformity of the thickness of the initial sidewall layer 111 and improve the density of the initial sidewall layer 111.

In this embodiment, the initial sidewall layer 111 is not filled in the contact hole 106.

Referring to fig. 7-8, fig. 8 is an enlarged view of a partial structure of fig. 7, a portion of the initial sidewall layer 111 (refer to fig. 6) located on the top surface of the second insulating layer 105 and at the bottom of the contact hole 106 is removed, the remaining initial sidewall layer 111 is used as the sidewall layer 110, and the sidewall layer 110 at least exposes the central region 1011.

In this embodiment, for two sidewall layers 110 in the same contact hole 106, orthographic projections of the two sidewall layers 110 on the top surface of the active region 101 are respectively adjacent to two sides of the central region 1011, that is, the two sidewall layers 110 are respectively located right above the two edge regions 1012 and expose the central region 1011; this allows the subsequently formed contact pillars to be located directly above the central region 1011.

In other embodiments, referring to fig. 9, for two sidewall layers 110 within the same contact hole 106, the orthographic projection of one sidewall layer 110 on the top surface of the active region 101 is adjacent to one side of the central region 1011, and the orthographic projection of the other sidewall layer 110 on the top surface of the active region 101 is adjacent to one side of the edge region 1012; that is, one sidewall layer 110 is located directly above one edge region 1012, and the other sidewall layer 110 is located directly above the isolation structure 102, exposing the central region 1011 and the other edge region 1012; this allows for the subsequently formed contact pillars to be located directly above the center region 1011 and one of the edge regions 1012.

In another embodiment, referring to fig. 10, fig. 10 is a partial top view of a semiconductor structure, wherein a sidewall layer 110 is located directly above an edge region 1012 and surrounds a central region 1011; in this manner, subsequently formed contact pillars may be located directly above center region 1011 and exposing edge regions 1012 surrounding center region 1011.

In this embodiment, a portion of the initial sidewall layer 111 is removed by dry etching. Specifically, the initial sidewall layer 111 may be etched by using a maskless etching process until the central region 1011 is exposed, so as to form the sidewall layer 110.

Referring to fig. 11, contact pillars 120 are formed, the contact pillars 120 are located within the contact holes 106 (refer to fig. 7), and the contact pillars 120 are in contact with the central region 1011 of the active region 101 and expose at least one edge region 1012 of the active region 101. The contact pillars 120 are also in contact with the sidewall layer 110.

The contact pillars 120 serve as masks for subsequently forming the protruding portions of the active regions 101, and the contact pillars 120 serve as masks for etching the active regions 101, so that the surface area of the active regions 101 can be increased, and the contact resistance between the active regions 101 and subsequently formed contact layers can be reduced.

In this embodiment, the contact pillars 120 expose two edge regions 1012, i.e., the active regions 101 corresponding to the two edge regions 1012 are etched later, so that two opposite sidewalls of the protruding portion are exposed. In other embodiments, the contact pillar may also expose an edge region, i.e., an active region corresponding to the edge region is etched later, so that one sidewall of the protruding portion is exposed. In another embodiment, the contact studs may also be exposed in an edge region surrounding the central region, i.e. all sidewalls of subsequently formed protrusions are exposed.

In this embodiment, the material of the contact pillars 120 is a semiconductor material. Preferably, the material of the contact pillars 120 is the same as that of the active region 101, e.g., both materials may be silicon. When the material of the contact stud 120 is the same as that of the active region 101, the interface between the contact stud and the active region has fewer defects, so that the contact resistance can be reduced, the amount of charge transferred can be increased, and the operation rate of the semiconductor structure can be further increased.

In this embodiment, the contact pillars 120 may be formed by epitaxial growth. As can be seen from the foregoing, since the sidewall layer 110 exposes at least the central region 1011, a single crystal layer having the same crystal orientation as the active region 101 can be grown at least in the central region 1011 by epitaxial growth. The epitaxial growth method can reduce the contact resistance of the contact pillars 120 and the active region 101, thereby improving the operation rate of the semiconductor structure. More specifically, the contact pillars 120 are formed using a selective epitaxial process.

In this embodiment, the selective epitaxy process may be a vapor phase epitaxy process, specifically, a gas such as hydrogen, silicon tetrachloride, trichlorosilane, silane or dichlorosilane is introduced into a reaction chamber, and a high-temperature chemical reaction is performed in the reaction chamber, so that the silicon-containing reaction gas is reduced or thermally decomposed, and the generated silicon atoms epitaxially grow at least on the central region 1011.

By adopting the selective epitaxy process, the contact pillars 120 grow in the contact holes 106 from bottom to top, which is beneficial to improving the hole filling capability of the contact pillars 120 for filling the contact holes 106 and improving the quality of the formed contact pillars 120, so that the contact pillars 120 can better play a role of serving as a mask in the subsequent process, and the undesired area in the active area 101 is prevented from being damaged by etching. In addition, the quality of the contact pillars 120 formed using the selective epitaxial process is good, such that the contact pillars 120 can remain as part of the semiconductor structure later.

Further, the contact pillars 120 may have dopant ions therein, which may further reduce the resistance of the contact pillars 120. In addition, the doping type of the doping ions of the contact pillars 120 can be the same as the doping type of the doping ions in the active region 101, which is beneficial to increasing the affinity between the contact pillars 120 and the active region 101 and further reducing the contact resistance. Preferably, the doping ions of the contact pillars 120 are the same as the doping ions of the active region 101, such as phosphorus or boron. It can be appreciated that when the material and the doping ions of the contact pillars 120 are the same as those of the active region 101, the contact pillars 120 can be considered as a part of the active region 101, and after the contact layer is formed subsequently, the contact surface between the contact layer and the active region 101 not only includes the sidewalls of the protruding portion, but also includes the sidewalls of the contact pillars 120, so that the contact area between the contact layer and the active region can be further increased, and the operation rate of the semiconductor structure can be greatly improved.

In some embodiments, in-situ doping (in-situ doping) may be performed during the process steps of forming the contact pillars 120 using an epitaxial process to provide dopant ions within the contact pillars 120.

In other embodiments, the material of the contact pillars may also be other conductive materials, such as single metals, metal compounds, or alloys, etc.; alternatively, the contact posts may be of an insulating material and the contact posts removed after the projections are formed.

It should be noted that in other embodiments, the contact pillars may also be formed using a deposition process. Specifically, the process steps for forming the contact pillars include: forming a contact film filling the contact hole by adopting a deposition process, wherein the contact film is also positioned on the top surface of the second insulating layer; and flattening the contact film by adopting a flattening process, removing the contact film higher than the top surface of the second insulating layer, and taking the rest contact film as a contact post. Specifically, the deposition process may be an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

Referring to fig. 12, the sidewall layer 110 (refer to fig. 11) is removed.

Specifically, the sidewall layer 110 may be removed by wet etching. In this embodiment, the material of the sidewall layer 110 is titanium nitride, and correspondingly, the wet etching reagent may include hydrogen peroxide and sulfuric acid; the hydrogen peroxide and the sulfuric acid have a larger etching selectivity ratio to the side wall layer 110 and the contact pillars 120, so that damage to the contact pillars 120 can be reduced while the side wall layer 110 is completely removed.

In some embodiments, referring to fig. 13, the contact pillars 120 are subjected to an ion doping process having the same doping type as the doping ions in the active region 101. In particular, the ion doping process may be an ion implantation technique.

The ion doping process enables the contact pillars 120 to maintain the same or similar physicochemical properties as the active region 101, i.e., the contact pillars 120 can be regarded as a part of the active region 101, so that the contact area between the active region and a subsequently formed contact layer can be greatly increased, thereby improving the operation rate of the semiconductor structure.

It will be appreciated that in some embodiments, in-situ ion doping may be performed during the foregoing process steps for forming the contact pillars 120, and accordingly, no additional ion doping treatment may be required after forming the contact pillars 120.

After the ion doping treatment, it may further include: the contact pillars 120 are annealed. The annealing treatment can reduce the damage to the repair contact pillars 120 in the ion doping process, thereby reducing the resistance of the contact pillars 120; furthermore, the annealing process can also activate the dopant ions within the contact pillars 120.

In other embodiments, the annealing treatment and the crystallization treatment of the subsequent contact layer may be integrated in the same process step, so as to shorten the process time and reduce the production cost.

It should be noted that, in other embodiments, the ion doping treatment may also be performed on the contact column before the sidewall layer is removed.

Referring to fig. 14, a portion of the active region 101 is etched using the contact pillars 120 as a mask such that the active region 101 has protrusions 1013, and the protrusions 1013 are directly opposite the contact pillars 120.

After etching the active region 101, there is a height difference between different regions of the top surface of the active region 101. In this embodiment, the center region 1011 (refer to fig. 20) is higher than the two edge regions 1012 (refer to fig. 20). In other embodiments, the central region may also be flush with one edge region and higher than the other edge region. In another embodiment, the central region is higher than the peripheral region surrounding its periphery. It can be appreciated that in the above embodiments, the area of the exposed surface of the active region is increased, so that the contact area between the active region and the subsequently formed contact layer can be increased, thereby reducing the contact resistance and improving the operation rate of the semiconductor structure.

Preferably, in the step of etching a portion of the active region 101, the ratio of the etching depth to the etching width of the active region 101 is 5:1. In other words, etching the active region 101 forms a groove adjoining the boss 1013, the ratio of the depth of the groove to the opening size of the groove being 5:1. it can be appreciated that if the ratio of the etching depth to the etching width of the active region 101 is too large, the difficulty of filling the contact layer in the groove later may be increased, that is, the density of the contact layer may be reduced, so that the contact effect between the contact layer and the protrusion 1013 may be affected; if the ratio of the etching depth to the etching width of the active region 101 is too small, the contact area between the subsequently formed contact layer and the protrusion 1013 is small. When the ratio of the etching depth to the etching width of the active region 101 is 5:1, the filling difficulty of the contact layer can be reduced, the contact area between the contact layer and the protruding portion 1013 can be increased to a greater extent, and the running speed of the semiconductor structure can be further effectively improved.

In this embodiment, the boss 1013 is formed by dry etching. It will be appreciated that since the active region 101 is of a similar material to the contact pillars 120, a portion of the contact pillars 120 will be consumed during etching of the active region 101, and thus the thickness of the contact pillars 120 in a direction perpendicular to the top surface of the substrate 10 may be suitably increased during formation of the contact pillars 120.

Referring to fig. 15, a contact layer 130 is formed, and the contact layer 130 fills the contact hole 106 (refer to fig. 14) and contacts the sidewall of the boss 1013.

In this embodiment, the contact layer 130 is further in contact with the contact pillars 120, and a portion of the contact layer 130 is further located on the top surface of the second insulating layer 105.

As can be seen from the foregoing, the protrusion 1013 increases the area of the exposed surface of the active region 101, so that the contact layer 130 has a smaller contact resistance with the active region 101, thereby improving the operation rate of the semiconductor structure.

In this embodiment, the material of the contact layer 130 may be polysilicon. The contact layer 130 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that, in other embodiments, the material of the contact pillars is an insulating material, and accordingly, before forming the contact layer, the contact pillars may be removed, so as to increase the volume of the formed contact layer and reduce the resistance of the contact layer.

Referring to fig. 16, after forming the contact layer 130, further includes: the contact layer 130 is etched back so that the top surface of the contact layer 130 is flush with the top surface of the conductive layer 104.

During the etch back, portions of the contact pillars 120 may also be etched so that the top surfaces of the contact pillars 120 are flush with the top surface of the conductive layer 104. It will be appreciated that if the larger thickness of the contact pillars 120 is consumed during the formation of the projections 1013 described above such that the top surface of the contact layer 130 is already flush with the top surface of the conductive layer 104, then there is no need to etch the contact pillars 120 during the etching back of the contact layer 130.

In other embodiments, the top surfaces of the contact pillars may also be lower than the top surfaces of the conductive layer.

Referring to fig. 17, the second insulating layer 105 is removed (refer to fig. 16).

In this embodiment, the second insulating layer 105 is removed by wet etching, and in other embodiments, the second insulating layer may be removed by dry etching.

In some embodiments, the method of manufacturing may further comprise: the contact layer 130 is subjected to crystallization treatment, which may rearrange the lattice structure inside the contact layer 130, thereby reducing the resistance of the contact layer 130. It is noted that the crystallization process may also be integrated in the same process step as the aforementioned annealing process of the contact pillars 120, in particular, the contact layer 130 and the contact pillars 120 are subjected to a high temperature of 500-600 ℃ in the furnace tubes of the heat treatment apparatus.

The subsequent process steps further comprise: a bit line structure is formed. The process steps for forming the bit line structure include the steps of:

Referring to fig. 18, an initial bit line conductive layer 151 and an initial bit line capping layer 161 are formed on the contact layer 130 in a stacked arrangement.

In this embodiment, an initial bit line barrier layer 141 is also formed between the contact layer 130 and the initial conductive layer 151.

The material of the initial bit line conductive layer 151 may be tungsten, tantalum, molybdenum, gold, or silver. The material of the initial bit line cover layer 161 may be silicon nitride, silicon oxide, or silicon carbonitride. The material of the initial bit line barrier layer 141 may be titanium nitride or tantalum nitride. In this embodiment, the initial bit line conductive layer 151 and the initial bit line barrier layer 141 are formed by a physical vapor deposition method, and the initial bit line capping layer 161 is formed by a chemical vapor deposition method.

Referring to fig. 19 to 20, fig. 20 is an enlarged view of a partial structure of fig. 19, and an initial bit line conductive layer 151 (refer to fig. 18) and an initial bit line capping layer 161 (refer to fig. 18) are subjected to patterning process to form a bit line conductive layer 150 and a bit line capping layer 160.

In this embodiment, the initial bit line barrier 141 (see fig. 18) is also patterned to form the bit line barrier 140. In addition, during the patterning process, a portion of the contact layer 130 is also removed. The bit line conductive layer 150, bit line capping layer 160, bit line barrier layer 140, contact pillars 120, and remaining contact layer 130 together comprise a bit line structure 180.

The patterning process may be performed by dry etching.

After patterning, the remaining contact layer 130 is located on the sidewalls of the contact pillars 120 and the protrusions 1013. The protrusion 1013 may increase the contact area between the contact layer 130 and the active region 101, thereby reducing the contact resistance and increasing the operation rate of the semiconductor structure.

With continued reference to fig. 19-20, a protective layer 170 is formed on the sidewalls and top surface of the bit line structure 180.

Part of the protection layer 170 is also located in the contact hole and on the surface of the first insulating layer 103. The protective layer 170 is used to isolate the bit line structure from subsequently formed capacitor contact structures. In this embodiment, the protection layer 170 has a single-layer structure. In other embodiments, the protective layer may also be a multi-layer structure. The material of the protective layer 170 may be titanium nitride, silicon oxide, silicon carbide, or silicon carbonitride.

In summary, the contact pillars 120 are formed by epitaxial growth in this embodiment, so that the contact resistance between the contact pillars 120 and the active region 101 can be reduced; the material and doping ion type of the contact pillars 120 are the same as those of the active region 101, so that the contact pillars 120 can be regarded as a part of the active region 101, thereby increasing the contact area of the contact layer 130 with the active region 101; the active region 101 is etched using the contact pillars 120 as a mask to form the protrusions 1013, and the protrusions 1013 can further increase the contact area between the active region 101 and the contact layer 130. Therefore, the embodiment can increase the amount of electric charge transferred, thereby increasing the operation rate of the semiconductor structure.

Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which is substantially the same as the foregoing embodiment, and is mainly different from the method for forming a contact pillar in the foregoing embodiment, and the contact pillar in the present embodiment has a double-layer structure. The same or similar parts as those of the previous embodiment are referred to the detailed description of the previous embodiment, and will not be repeated here. Fig. 21 to 24 are schematic structural diagrams corresponding to each step in the method for manufacturing a semiconductor structure according to an embodiment of the present invention. The following will make a detailed description with reference to the accompanying drawings.

Referring to fig. 21, a substrate 30 is provided, the substrate 30 having an active region 301 therein, the top surface of the active region 301 including a central region and edge regions located at least on opposite sides of the central region. The substrate 30 further has an isolation structure 302 therein, and the substrate 30 further has a first insulating layer 303, a conductive layer 304, and a second insulating layer 305 stacked thereon. The substrate 30 is etched to form contact holes exposing the top surfaces of the active regions 301.

With continued reference to fig. 21, a sidewall layer 310 is formed on the sidewall of the contact hole, where the sidewall layer 310 also covers the bottom of the contact hole and the sidewall layer in the same contact hole encloses a recess. In this embodiment, the groove is opposite to the central region, and the sidewall layers 310 on the sidewalls of the contact holes are opposite to the edge regions on both sides of the central region; in other embodiments, the groove may also be opposite to the central region and one edge region, and the sidewall layer located on the sidewall of the contact hole is opposite to the other edge region; in another embodiment, the recess is opposite the central region and the sidewall layer on the sidewall of the contact hole is opposite the edge region surrounding the central region.

In this embodiment, the sidewall layer 310 is made of a conductive material, such as polysilicon, titanium nitride, tungsten, gold, silver or copper. In other embodiments, the sidewall layer may also be an insulating material, such as silicon nitride or silicon carbonitride.

Referring to fig. 21-22, contact pillars 320 filling the contact holes are formed, and the contact pillars 320 are in contact with the sidewall layer 310. The formation step of the contact post 320 will be described in detail below.

Referring to fig. 21, first contact pillars 321 filling the recesses are formed by a deposition process. In this embodiment, the first contact pillars 321 are formed by a chemical vapor deposition process, and in other embodiments, the first contact pillars may also be formed by a physical vapor deposition and atomic layer deposition process.

In this embodiment, the material of the first contact post 321 is a conductive material, such as polysilicon, titanium nitride, tungsten, gold, silver, or copper. In other embodiments, the first contact stud may also be an insulating material, such as silicon nitride or silicon carbonitride.

Referring to fig. 22, after the first contact post 321 is formed, the sidewall layer 310 (refer to fig. 21) located on the sidewall of the contact hole is removed, the sidewall layer 310 located at the bottom of the contact hole serves as a second contact post 322, the second contact post 322 faces the first contact post 321, and the second contact post 322 and the first contact post 321 constitute a contact post 320.

In this embodiment, since the first contact stud 321 and the second contact stud 322 are both made of a conductive material, that is, the entire contact stud 320 is conductive, the contact stud 320 can be used as a mask for etching the active region 301 later, and can also form a contact structure of a bit line structure. In other embodiments, if the second contact pillars and the first contact pillars are insulating material, the contact pillars only serve as a mask for etching the active region, and the contact pillars are removed after etching the active region, prior to forming the contact layer.

Referring to fig. 23, a portion of the active region 301 is etched using the contact pillars 320 as a mask such that the active region 301 has raised portions 3013, and the raised portions 3013 are directly opposite the contact pillars 320.

The protruding portion 3013 can increase the contact area of the active region 301 and a subsequently formed contact layer, thereby increasing the amount of charge transferred per unit time, and thus increasing the operation rate of the semiconductor structure.

Referring to fig. 24, a contact layer 330 filling the contact hole is formed, and the contact layer 330 is in contact with the contact stud 320. The contact layer 330 is also located on the top surface of the second insulating layer 305.

It should be noted that, in other embodiments, if the material of the contact pillar is an insulating material, after the forming of the protruding portion, before the forming of the contact layer, the method further includes: and removing the contact pillars. I.e. the contact layer formed fills the entire contact hole.

The forming of the contact layer 330 further includes: etching back the contact layer 330 and the contact pillars 320 so that the top surfaces of the contact layer 330 and the contact pillars 320 are flush with the top surface of the conductive layer 304; removing the second insulating layer 305; the removal of the second insulating layer 305 further includes: forming an initial bit line conductive layer and an initial bit line capping layer stacked on the contact layer 330; patterning the initial bit line conductive layer and the initial bit line capping layer to form the bit line conductive layer and the bit line capping layer. During the patterning process, a portion of contact layer 330 is also removed.

In summary, in the embodiment, the first contact post 321 is directly formed in the groove surrounded by the sidewall layer 310, and the sidewall layer 310 located right below the first contact post 321 is used as the second contact post 322, so that the step of removing the sidewall layer 310 at the bottom of the contact hole can be omitted, thereby simplifying the production process. In addition, the active region 301 is etched using the contact pillars 320 as a mask to form the raised portions 3013, and the raised portions 3013 can increase the contact area between the active region 301 and the contact layer 330. Therefore, the embodiment can increase the amount of electric charge transferred, thereby increasing the operation rate of the semiconductor structure.

In another embodiment, a semiconductor structure is provided, and the semiconductor structure in this embodiment may be formed by the method for manufacturing a semiconductor structure provided in the foregoing embodiment. Fig. 19 is a schematic view of a semiconductor structure provided in this embodiment, fig. 20 is a partial structure method diagram of fig. 19, and referring to fig. 19-20, the semiconductor structure includes: the substrate 10, the substrate 10 has an active region 101 therein, and the top surface of the active region 101 includes a central region 1011 and edge regions 1012 at least on two sides of the central region 1011; active region 101 has a protrusion 1013, a top surface of protrusion 1013 is located in central region 1011, and a top surface of protrusion 1013 is higher than at least one edge region 1012; and a contact layer 130, the contact layer 130 contacting the sidewall of the protrusion 1013. The same or similar parts as those of the previous embodiment are referred to the detailed description of the previous embodiment, and will not be repeated here. The following will make a detailed description with reference to the accompanying drawings.

The material of the substrate 10 may include silicon, silicon carbide, silicon nitride, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), silicon carbide, silicon germanium, gallium arsenide, indium gallium, or the like; in the present embodiment, the material of the substrate 10 is a silicon material.

The raised portion 1013 on top of the active region 101 can increase the surface area with the active region 101, thereby reducing the contact resistance with the contact layer 130, and thereby increasing the operating rate of the semiconductor structure. In this embodiment, the top surface of the boss 1013 is higher than the two edge regions 1012; i.e., for the top surface of active region 101, central region 1011 is higher than both edge regions 1012. In other embodiments, the top surface of the boss is located at the central region and one edge region and higher than the other edge region; i.e. for the top surface of the active region, the central region is flush with one edge region and higher than the other edge region. In another embodiment, the top surface of the boss is higher than the edge area surrounding its periphery; i.e. for the top surface of the active region, the central region is higher than the edge regions surrounding it.

The thickness of the protrusion 1013 is 8 to 12nm in a direction perpendicular to the top surface of the substrate 10; the width of the protrusion 1013 is 8 to 12nm in a direction perpendicular to the sidewall of the substrate 10. When the thickness and width of the protrusion 1013 are within the above ranges, it is ensured that the protrusion 1013 increases the surface area of the active region 101 to a large extent, and thus the amount of charge transferred to a large extent, thereby increasing the operation rate of the semiconductor structure.

The substrate 10 further has an isolation structure 102 therein, and the substrate 10 further has a first insulating layer 103 and a conductive layer 104 thereon. For a specific description of the above structure, reference is made to the foregoing embodiments.

The contact layer 130 is used to form a contact structure for the bit line structure 180 to electrically connect the bit line conductive layer 150 with the active region 101. The material of the contact layer 130 is a conductive material, such as polysilicon.

In this embodiment, the semiconductor structure further includes: and a contact stud 120, the contact stud 120 being in facing and contacting relation with the protrusion 1013, the contact layer 130 being further located on a side wall of the contact stud 120.

In this embodiment, the contact pillars 120 have a single-layer structure. In other embodiments, the contact stud may also be a bilayer structure, the contact stud comprising a first contact structure and a second contact structure arranged in a stack.

Further, the contact pillars 120 may have dopant ions therein, which may further reduce the resistance of the contact pillars 120. In addition, the doping type of the doping ions of the contact pillars 120 can be the same as the doping type of the doping ions in the active region 101, which is beneficial to increasing the affinity between the contact pillars 120 and the active region 101 and further reducing the contact resistance. Preferably, the doping ions of the contact pillars 120 are the same as the doping ions of the active region 101, such as phosphorus or boron. It is understood that when the material and the doping ions of the contact pillars 120 are the same as those of the active region 101, the contact pillars 120 can also be considered as a part of the active region 101, and the contact surface between the contact layer 130 and the active region 101 includes not only the sidewalls of the protruding portion 1013 but also the sidewalls of the contact pillars 120, so that the contact area between the contact layer 130 and the active region 101 can be further increased, and the operation rate of the semiconductor structure can be greatly improved.

In other embodiments, the material of the contact pillars may also be other conductive materials, such as single metals, metal compounds, or alloys, etc.; or the semiconductor structure is not provided with a contact pillar, and the upper surface of the active region is only contacted with the contact layer.

The semiconductor structure further includes: the contact layer 130 stacks the bit line conductive layer 150 and the bit line capping layer 160. Bit line barrier layer 140 is also between bit line conductive layer 150 and contact layer 130. The contact layer 130, the contact pillars 120, the bit line conductive layer 150, the bit line cover layer 160, and the bit line barrier layer 140 comprise a bit line structure 180. The sidewalls of the bit line structure 180 also have a protective layer 170. For a specific description of the above structure, please refer to the foregoing embodiments, and the description thereof is omitted herein.

In summary, in the present embodiment, the material and the doping ion type of the contact pillars 120 are the same as those of the active region 101, so the contact pillars 120 can be regarded as a part of the active region 101, and the contact area between the contact layer 130 and the active region 101 is increased; the protrusion 1013 on top of the active region 101 can further increase the contact area of the active region 101 with the contact layer 130. Therefore, the embodiment can increase the amount of electric charge transferred, thereby increasing the operation rate of the semiconductor structure.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is therefore intended to be limited only by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein an active region is arranged in the substrate, and the top surface of the active region comprises a central region and edge regions at least positioned on two opposite sides of the central region;

etching the substrate to form a contact hole, wherein the contact hole exposes the top surface of the active region;

forming a contact stud, wherein the contact stud is positioned in the contact hole, contacts the central region of the active region, and exposes at least one edge region of the active region;

etching part of the active region by taking the contact column as a mask so that the active region is provided with a protruding part, and the protruding part is opposite to the contact column;

And forming a contact layer, wherein the contact layer fills the contact hole and contacts with the side wall of the protruding part.

2. The method of manufacturing a semiconductor structure of claim 1, further comprising, prior to forming the contact pillars: forming a side wall layer positioned on the side wall of the contact hole, wherein the orthographic projection of the side wall layer in the same contact hole on the top surface of the active region is at least adjacent to the central region;

The method for forming the contact post comprises the following steps: forming a contact column filling the contact hole, wherein the contact column is contacted with the side wall layer;

After the contact posts are formed, before the protruding portions are formed, the method further comprises the steps of: and removing the side wall layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein the sidewall layer at least exposes the central region, and the contact pillars are formed by an epitaxial growth method, and a material of the contact pillars is a semiconductor material;

the method for forming the contact layer comprises the following steps: and forming a contact layer filling the contact hole, wherein the contact layer is contacted with the contact column.

4. The method of claim 3, wherein the active region has a doping ion, and the doping ion is of a type N or P;

the forming of the contact post further comprises: carrying out ion doping treatment on the contact column, wherein the doping type of the ion doping treatment is the same as that of the doping ions in the active region;

After the ion doping treatment, the method further comprises the following steps: and carrying out annealing treatment on the contact column.

5. The method of claim 2, wherein the sidewall layer exposes at least the central region;

And forming the contact column on the top surface of the active region exposed by the side wall layer through a deposition process, wherein the contact column is contacted with the side wall layer.

6. The method of manufacturing a semiconductor structure of claim 5, wherein the material of the contact pillars is a conductive material; the method for forming the contact layer comprises the following steps: and forming the contact layer filling the contact hole, wherein the contact layer is contacted with the contact column.

7. The method of manufacturing a semiconductor structure of claim 5, wherein the material of the contact stud is an insulating material; after forming the protruding portion, before forming the contact layer, the method further includes: and removing the contact posts.

8. The method of claim 2, wherein the sidewall layer further covers a bottom of the contact hole, and the sidewall layer in the same contact hole encloses a recess;

the step of forming the contact stud includes: forming a first contact column filling the groove through a deposition process;

After the first contact post is formed, the side wall layer positioned on the side wall of the contact hole is removed, the side wall layer positioned at the bottom of the contact hole is used as a second contact post, the second contact post is opposite to the first contact post, and the second contact post and the first contact post form the contact post.

9. The method of claim 2, wherein the sidewall layer material comprises titanium nitride; and removing the side wall layer by wet etching, wherein the wet etching reagent comprises hydrogen peroxide and sulfuric acid.

10. The method of claim 1, wherein in the step of etching a portion of the active region, a ratio of an etching depth to an etching width of the active region is 5:1.

11. The method of manufacturing a semiconductor structure according to claim 1, further comprising, after forming the contact layer: forming an initial bit line conductive layer and an initial bit line cover layer which are stacked on the contact layer; and patterning the initial bit line conductive layer and the initial bit line cover layer to form a bit line conductive layer and a bit line cover layer.

12. A semiconductor structure, comprising:

The substrate is internally provided with an active area, and the top surface of the active area comprises a central area and edge areas at least positioned at two sides of the central area; the active area is provided with a protruding part, the top surface of the protruding part is positioned in the central area, and the top surface of the protruding part is at least higher than one edge area;

a contact layer in contact with a sidewall of the protrusion;

And the contact column is opposite to and in contact with the convex part, and the contact layer is also positioned on the side wall of the contact column.

13. The semiconductor structure of claim 12, further comprising: the top surface of the boss is higher than the two edge regions.

14. The semiconductor structure of claim 13, wherein the thickness of the protruding portion is 8-12 nm in a direction perpendicular to the top surface of the substrate; and in the direction perpendicular to the side wall of the substrate, the width of the protruding part is 8-12 nm.

15. The semiconductor structure of claim 12, wherein the active region and the contact pillar each have a doping ion therein, and wherein the doping ion of the active region has a doping type that is the same as a doping type of the doping ion of the contact pillar.

16. The semiconductor structure of claim 12, further comprising: and a bit line conducting layer and a bit line covering layer which are arranged on the contact layer in a laminated mode.