CN114551335A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, comprising: a substrate, the substrate comprising a base and a device structure; a conductive layer on the device structure; a composite layer on the conductive layer, the composite layer comprising a first film layer; on the substrate The dielectric layer has a first opening in the dielectric layer; the second opening is located in the first film layer, and the sidewall of the second opening is recessed relative to the sidewall of the first opening; the conductive layer located in the first opening and the second opening plug. Since the sidewall of the second opening is recessed relative to the sidewall of the first opening, during the planarization process to form the conductive plug, the flow path of the planarization solution can be effectively increased, thereby reducing the electrical conductivity of the planarization solution. In addition, the growth of the conductive plug in the second opening can be restricted, so that the structure formed by the conductive plug in the second opening is more dense, and the flow of the planarization solution to the conductive plug is further reduced. layer damage.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

As the production of integrated circuits develops to VLSI, the circuit density inside the integrated circuit is getting larger and larger, and the number of components included is also increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection.

In order to meet the requirements of interconnect lines after shrinking components, the design of multi-layer metal interconnect lines with two or more layers has become a method commonly used in VLSI technology. At present, the conduction between different metal layers or between the metal layers and the devices in the substrate is realized through conductive plugs in the dielectric layer between the metal layers and the metal layers or between the metal layers and the substrate.

At present, the conductive plug made by the selective tungsten growth process can effectively increase the volume of the conductive plug, thereby increasing the contact area of the bottom of the conductive plug, so as to achieve the purpose of reducing the contact resistance.

However, the performance of the conductive plug made by the selective tungsten growth process in the prior art needs to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate includes a base and a device structure located on the base; a conductive layer located on the device structure; located on the conductive layer At least one composite layer of the device, the composite layer includes a first film layer on the conductive layer; a dielectric layer on the substrate, the dielectric layer covers the device structure and the composite layer, so The dielectric layer has a first opening; a second opening located in the first film layer, the sidewall of the second opening is recessed relative to the sidewall of the first opening; located between the first opening and the the conductive plug in the second opening.

Optionally, the composite layer further includes: a barrier layer on the first film layer, the barrier layer has a third opening, and the sidewall of the second opening is opposite to the side of the third opening The wall is recessed, and the conductive plug is also located in the third opening.

Optionally, the composite layer further includes: a second film layer on the barrier layer, the second film layer has a fourth opening, and the sidewall of the fourth opening is opposite to the third opening The sidewall is recessed, and the conductive plug is also located in the fourth opening.

Optionally, the materials of the first film layer and the barrier layer are different; the materials of the second film layer and the barrier layer are different.

Optionally, the material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

Optionally, the material of the barrier layer includes carbon-doped silicon nitride.

Optionally, the material of the conductive plug includes tungsten.

Optionally, the material of the conductive layer includes cobalt.

Optionally, the device structure includes a transistor structure.

Optionally, the transistor structure includes: a gate structure on the substrate; and source and drain doped layers in the substrate on both sides of the gate structure.

Optionally, the conductive layer is located on the source-drain doped layer or the gate structure.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate comprising a base and a device structure on the base; forming a conductive layer on the device structure forming at least one composite layer on the conductive layer, the composite layer comprising a first film layer located on the conductive layer; forming a dielectric layer on the substrate, the dielectric layer covering the device structure and the composite layer, the dielectric layer has a first opening; a second opening is formed in the first film layer, and the sidewall of the second opening is recessed relative to the sidewall of the first opening. Conductive plugs are formed in the first opening and the second opening.

Optionally, the composite layer further includes: a barrier layer on the first film layer, the barrier layer has a third opening, and the sidewall of the second opening is opposite to the side of the third opening The wall is recessed, and the conductive plug is also located in the third opening.

Optionally, the composite layer further includes: a second film layer on the barrier layer, the second film layer has a fourth opening, and the sidewall of the fourth opening is opposite to the third opening The sidewall is recessed, and the conductive plug is also located in the fourth opening.

Optionally, the materials of the first film layer and the barrier layer are different; the materials of the second film layer and the barrier layer are different.

Optionally, the material of the first film layer includes aluminum nitride; the material of the second film layer includes aluminum nitride.

Optionally, the material of the barrier layer includes carbon-doped silicon nitride.

Optionally, the formation process of the second opening includes an isotropic wet etching process.

Optionally, the formation process of the fourth opening includes an isotropic wet etching process.

Optionally, the formation process of the third opening includes an anisotropic dry etching process.

Optionally, the method for forming the conductive plug includes: using a metal selective growth process in the first opening, the second opening, the third opening and the fourth opening, and on the top surface of the dielectric layer forming initial conductive plugs; performing planarization treatment on the initial conductive plugs until the top surface of the dielectric layer is exposed, and forming the conductive plugs.

Optionally, the material of the conductive plug includes tungsten.

Optionally, the planarization process includes a chemical mechanical polishing process.

Optionally, the material of the conductive layer includes cobalt.

Optionally, the device structure includes a transistor structure.

Optionally, the transistor structure includes: a gate structure on the substrate; and source and drain doped layers in the substrate on both sides of the gate structure.

Optionally, the conductive layer is located on the source-drain doped layer or the gate structure.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the structure of the technical solution of the present invention, through the second opening located in the first film layer, the sidewall of the second opening is recessed relative to the sidewall of the first opening. In the subsequent process of forming the conductive plug through the planarization treatment, the flow path of the planarization treatment solution can be effectively increased, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution; The sidewall of the second opening is recessed relative to the sidewall of the first opening, so that the growth of the conductive plug in the second opening is limited, so that the conductive plug is formed in the second opening The structure is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer, thereby reducing the etching damage of the planarization treatment solution to the conductive layer.

Further, the composite layer further includes: a barrier layer on the first film layer, the barrier layer has a third opening therein, and the sidewall of the second opening is recessed relative to the sidewall of the third opening . The barrier layer further increases the flow path of the planarization treatment solution, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution.

Further, the composite layer further includes: a second film layer on the barrier layer, the second film layer has a fourth opening, and the side wall of the fourth opening is opposite to the side of the third opening The wall is recessed, and the conductive plug is also located in the fourth opening. The second film layer further increases the flow path of the planarization treatment solution, thereby reducing the etching damage of the planarization treatment solution to the conductive layer. In addition, since the sidewall of the fourth opening is recessed relative to the sidewall of the third opening, the growth of the conductive plug in the fourth opening is limited, so that the conductive plug is located in the fourth opening. The structure formed by the fourth opening is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution.

In the formation method of the technical solution of the present invention, by forming the second opening in the first film layer, the side wall of the second opening is recessed relative to the side wall of the first opening. In the subsequent process of forming the conductive plug through the planarization treatment, the flow path of the planarization treatment solution can be effectively increased, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution; The sidewall of the second opening is recessed relative to the sidewall of the first opening, so that the growth of the conductive plug in the second opening is limited, so that the conductive plug is formed in the second opening The structure is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer, thereby reducing the etching damage of the planarization treatment solution to the conductive layer.

Further, the composite layer further includes: a barrier layer on the first film layer, the barrier layer has a third opening therein, and the sidewall of the second opening is recessed relative to the sidewall of the third opening . The barrier layer further increases the flow path of the planarization treatment solution, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution.

Further, the composite layer further includes: a second film layer on the barrier layer, the second film layer has a fourth opening, and the side wall of the fourth opening is opposite to the side of the third opening The wall is recessed, and the conductive plug is also located in the fourth opening. The second film layer further increases the flow path of the planarization treatment solution, thereby reducing the etching damage of the planarization treatment solution to the conductive layer. In addition, since the sidewall of the fourth opening is recessed relative to the sidewall of the third opening, the growth of the conductive plug in the fourth opening is limited, so that the conductive plug is located in the fourth opening. The structure formed by the fourth opening is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution.

Description of drawings

1 to 2 are schematic structural diagrams of a semiconductor structure;

FIG. 3 to FIG. 10 are schematic structural diagrams of each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

As mentioned in the background art, the performance of the conductive plug made by the selective tungsten growth process in the prior art needs to be improved. The following will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a substrate is provided, the substrate includes a base 100 and a device structure 101 on the base 100; a conductive layer 102 is formed on the device structure 101; a dielectric layer 103 is formed on the substrate , the dielectric layer 103 covers the device structure 101 and the conductive layer 102 ; a conductive opening 104 is formed in the dielectric layer 103 , and the conductive opening 104 exposes part of the top surface of the conductive layer 102 .

Referring to FIG. 2, initial conductive plugs (not shown) are formed in the conductive openings 104 and on the top surface of the dielectric layer 103; the initial conductive plugs are planarized until the dielectric is exposed Up to the top surface of layer 103, conductive plugs 105 are formed.

In this embodiment, the initial conductive plug is formed by selective growth of metal tungsten. However, since tungsten can only grow on the metal surface, the formed initial conductive plug is connected to the sidewall of the conductive opening 104 . The bonding between them is not very good, so that there is a gap between the initial conductive plug and the side wall of the conductive opening. The grinding alkaline solution used will flow to the conductive layer 102 along the sidewall of the conductive opening 104 , thereby causing certain damage to the conductive layer 102 , so that the conductive layer 102 and the conductive plug 105 are separated. The reduced contact may even lead to the problem that the conductive plug 105 is not in contact with the conductive layer 102 at all (as shown in part A in FIG. 2 ), thereby reducing the performance of the finally formed semiconductor structure.

On this basis, the present invention provides a semiconductor structure and a method for forming the same. By forming a second opening in the first film layer, the sidewall of the second opening is recessed relative to the sidewall of the first opening. . In the subsequent process of forming the conductive plug through the planarization treatment, the flow path of the planarization treatment solution can be effectively increased, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution; The sidewall of the second opening is recessed relative to the sidewall of the first opening, so that the growth of the conductive plug in the second opening is limited, so that the conductive plug is formed in the second opening The structure is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer, thereby reducing the etching damage of the planarization treatment solution to the conductive layer.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 10 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 3 , a substrate is provided, and the substrate includes a base 200 and a device structure 201 on the base 200 .

In this embodiment, the substrate 200 has a plurality of fins (not shown) separated from each other, and an isolation layer (not shown) covering part of the fins, and the top surface of the isolation layer is lower than the fins top surface of the part. In other embodiments, the substrate may further have several active regions, and an isolation layer is provided between adjacent active regions.

In this embodiment, the device structure 201 includes a transistor structure including: a gate structure (not labeled) on the substrate, the gate structure spans the fin, and the The gate structure covers part of the sidewalls and the top surface of the fin; source and drain doped layers (not marked) in the substrate on both sides of the gate structure.

Referring to FIG. 4 , a conductive layer 202 is formed on the device structure 201 .

In this embodiment, the conductive layer 202 is located on the source and drain doped layers. In other embodiments, the conductive layer may also be located on the gate structure.

In this embodiment, the material of the conductive layer 202 is cobalt.

Referring to FIG. 5 , at least one composite layer is formed on the conductive layer 202 , and the composite layer includes a first film layer 203 on the conductive layer 202 .

In this embodiment, the composite layer further includes: a barrier layer 204 located on the first film layer 203 .

In this embodiment, the composite layer further includes: a second film layer 205 located on the barrier layer 204 .

In this embodiment, the materials of the first film layer 203 and the barrier layer 204 are different; the materials of the second film layer 205 and the barrier layer 204 are different. By selecting different materials, in the subsequent etching process, the etching selectivity ratio between different film layers is increased, and the damage to other film layers is reduced.

In this embodiment, the material of the first film layer 203 includes aluminum nitride; the material of the second film layer 205 includes aluminum nitride.

In this embodiment, the material of the barrier layer 204 includes carbon-doped silicon nitride.

Referring to FIG. 6 , after the composite layer is formed, a dielectric layer 206 is formed on the substrate, the dielectric layer 206 covers the device structure 201 and the composite layer, and the dielectric layer 206 has a first Opening 207.

In this embodiment, the method for forming the dielectric layer 206 includes: forming an initial dielectric layer (not shown) on the composite layer; forming a patterned layer (not shown) on the initial dielectric layer, so that The patterned layer exposes part of the top surface of the initial dielectric layer; the initial dielectric layer is etched with the patterned layer as a mask until the top surface of the composite is exposed, forming the dielectric layer 206 .

In this embodiment, the material of the dielectric layer 206 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-K dielectric material (low-K dielectric material refers to a material with a relative permittivity lower than 3.9). dielectric material) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5).

After forming the dielectric layer 206, the method further includes: forming a second opening in the first film layer 203, and the sidewall of the second opening is recessed relative to the sidewall of the first opening 207; A third opening is formed in the barrier layer 204, and the sidewall of the second opening is recessed relative to the sidewall of the third opening; a fourth opening is formed in the second film layer 205, and the sidewall of the fourth opening is The wall is recessed relative to the side wall of the third opening. Please refer to FIG. 7 to FIG. 9 for the specific forming process.

Referring to FIG. 7 , the second film layer 205 is etched using the dielectric layer 206 as a mask, and the fourth opening 208 is formed in the second film layer 205 .

In this embodiment, the formation process of the fourth opening 208 includes an isotropic wet etching process.

Referring to FIG. 8 , the barrier layer 204 is etched using the dielectric layer 206 and the second film layer 205 as masks, and the third opening 209 is formed in the barrier layer 204 .

In this embodiment, the formation process of the third opening 209 includes an anisotropic dry etching process.

Referring to FIG. 9 , the first film layer 203 is etched using the dielectric layer 206 , the second film layer 205 and the barrier layer 204 as masks, and the second opening 210 is formed in the first film layer 203 .

In this embodiment, the formation process of the second opening 210 includes an isotropic wet etching process.

In this embodiment, by forming the second opening 210 in the first film layer 203 , the sidewall of the second opening 210 is recessed relative to the sidewall of the first opening 207 . In the subsequent process of forming the conductive plug through the planarization treatment, the flow path of the planarization treatment solution can be effectively increased, thereby reducing the etching damage to the conductive layer caused by the planarization treatment solution; The sidewall of the second opening 210 is recessed relative to the sidewall of the first opening 207 , so that the growth of the conductive plug in the second opening 210 is restricted, so that the conductive plug is in the first opening 210 . The structure formed by the two openings 210 is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer 202, thereby reducing the etching damage to the conductive layer 202 caused by the planarization treatment solution.

The barrier layer 204 further increases the flow path of the planarization solution, thereby reducing the etching damage to the conductive layer 202 caused by the planarization solution.

The second film layer 205 further increases the flow path of the planarization treatment solution, thereby reducing the etching damage of the planarization treatment solution to the conductive layer. In addition, since the sidewall of the fourth opening 208 is recessed relative to the sidewall of the third opening 209 , the growth of the conductive plug in the fourth opening 208 is restricted, thereby making the conductive plug The structure formed by plugging in the fourth opening 208 is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer 202 , and further reduces the etching damage to the conductive layer 202 caused by the planarization treatment solution.

Referring to FIG. 10 , conductive plugs 211 are formed in the first opening 207 and the second opening 210 .

In this embodiment, the conductive plug 211 is also located in the third opening 209 and the fourth opening 208 .

In this embodiment, the method for forming the conductive plug 211 includes: adopting a metal selective growth process in the first opening 207 , the second opening 210 , the third opening 209 and the fourth opening 208 , and in the An initial conductive plug (not shown) is formed on the top surface of the dielectric layer 206; the initial conductive plug is planarized until the top surface of the dielectric layer 206 is exposed, and the conductive plug is formed 211.

In this embodiment, the material of the conductive plug 211 includes tungsten.

In this embodiment, the planarization process includes a chemical mechanical polishing process.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to FIG. 10 , including: a substrate, the substrate includes a base 200 and a device structure 201 located on the base 200; Conductive layer 202 on 201; at least one composite layer on the conductive layer 202, the composite layer including a first film layer 203 on the conductive layer 202; dielectric layer 206 on the substrate , the dielectric layer 206 covers the device structure 201 and the composite layer, the dielectric layer 206 has a first opening 207; the second opening 210 located in the first film layer 203, the second opening The side wall of 210 is recessed relative to the side wall of the first opening 207 ; the conductive plugs 211 are located in the first opening 207 and the second opening 210 .

In this embodiment, the sidewall of the second opening 210 is recessed relative to the sidewall of the first opening 207 through the second opening 210 in the first film layer 203 . In the subsequent process of forming the conductive plug 211 through the planarization treatment, the flow path of the planarization treatment solution can be effectively increased, thereby reducing the etching damage to the conductive layer by the planarization treatment solution; The sidewall of the second opening 210 is recessed relative to the sidewall of the first opening 207 , so that the growth of the conductive plug 211 in the second opening 210 is restricted, so that the conductive plug 211 is The structure formed by the second opening 210 is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer 202, thereby reducing the etching damage to the conductive layer 202 caused by the planarization treatment solution.

In this embodiment, the composite layer further includes: a barrier layer 204 located on the first film layer 203, the barrier layer 204 has a third opening 209 inside, and the sidewall of the second opening 210 is opposite to The sidewall of the third opening 209 is recessed, and the conductive plug 211 is also located in the third opening 209 . The barrier layer 204 further increases the flow path of the planarization solution, thereby reducing the etching damage to the conductive layer 202 caused by the planarization solution.

In this embodiment, the composite layer further includes: a second film layer 205 located on the barrier layer 204 , the second film layer 205 has a fourth opening 208 inside, and the sidewall of the fourth opening 208 Relative to the sidewall of the third opening 209 , the conductive plug 211 is also located in the fourth opening 208 . The second film layer 205 further increases the flow path of the planarization treatment solution, thereby reducing the etching damage of the planarization treatment solution to the conductive layer 202 . In addition, since the sidewall of the fourth opening 208 is recessed relative to the sidewall of the third opening 209 , the growth of the conductive plug 211 in the fourth opening 208 is limited, thereby making the conductive plug 211 limited. The structure formed by the plug 211 in the fourth opening 208 is more compact, which further reduces the flow of the planarization treatment solution to the conductive layer 202, thereby reducing the etching damage of the planarization treatment solution to the conductive layer 202 .

In this embodiment, the materials of the first film layer 203 and the barrier layer 204 are different; the materials of the second film layer 205 and the barrier layer 204 are different.

In this embodiment, the material of the first film layer 203 includes aluminum nitride; the material of the second film layer 205 includes aluminum nitride.

In this embodiment, the material of the barrier layer 204 includes carbon-doped silicon nitride.

In this embodiment, the material of the conductive plug 211 includes tungsten.

In this embodiment, the material of the conductive layer 202 includes cobalt.

In this embodiment, the device structure 201 includes a transistor structure.

In this embodiment, the transistor structure includes: a gate structure on the substrate 200 ; source and drain doped layers in the substrate on both sides of the gate structure.

In this embodiment, the conductive layer 202 is located in the source-drain doped layer. In other embodiments, the conductive layer may also be located on the gate structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (27)

1. a semiconductor structure, is characterized in that, comprises: a substrate, the substrate comprising a base and a device structure on the base; a conductive layer on the device structure; at least one composite layer on the conductive layer, the composite layer including a first film layer on the conductive layer; a dielectric layer on the substrate, the dielectric layer covering the device structure and the composite layer, and a first opening is provided in the dielectric layer; a second opening located in the first film layer, the sidewall of the second opening is recessed relative to the sidewall of the first opening; conductive plugs located within the first opening and the second opening. 2 . The semiconductor structure according to claim 1 , wherein the composite layer further comprises: a barrier layer located on the first film layer, the barrier layer has a third opening therein, and the second opening has a third opening. 3 . The side wall is recessed relative to the side wall of the third opening, and the conductive plug is also located in the third opening. 3 . The semiconductor structure of claim 2 , wherein the composite layer further comprises: a second film layer located on the barrier layer, the second film layer has a fourth opening therein, and the fourth film layer is 3 . The sidewall of the opening is recessed relative to the sidewall of the third opening, and the conductive plug is also located in the fourth opening. 4 . The semiconductor structure of claim 3 , wherein the materials of the first film layer and the barrier layer are different; and the materials of the second film layer and the barrier layer are different. 5 . 5 . The semiconductor structure of claim 4 , wherein the material of the first film layer comprises aluminum nitride; the material of the second film layer comprises aluminum nitride. 6 . 6. The semiconductor structure of claim 4, wherein the material of the barrier layer comprises carbon-doped silicon nitride. 7. The semiconductor structure of claim 1, wherein the material of the conductive plug comprises tungsten. 8. The semiconductor structure of claim 1, wherein the material of the conductive layer comprises cobalt. 9. The semiconductor structure of claim 1, wherein the device structure comprises a transistor structure. 10 . The semiconductor structure of claim 9 , wherein the transistor structure comprises: a gate structure on the substrate; and source-drain doped layers in the substrate on both sides of the gate structure. 11 . 11. The semiconductor structure of claim 10, wherein the conductive layer is located on the source-drain doped layer or the gate structure. 12. A method for forming a semiconductor structure, comprising: providing a substrate including a base and a device structure on the base; forming a conductive layer on the device structure; forming at least one composite layer on the conductive layer, the composite layer comprising a first film layer on the conductive layer; forming a dielectric layer on the substrate, the dielectric layer covering the device structure and the composite layer, and a first opening is formed in the dielectric layer; A second opening is formed in the first film layer, and the sidewall of the second opening is recessed relative to the sidewall of the first opening. Conductive plugs are formed in the first opening and the second opening. 13 . The method for forming a semiconductor structure according to claim 12 , wherein the composite layer further comprises: a barrier layer located on the first film layer, the barrier layer has a third opening in the barrier layer, and the first film layer is 13 . The sidewalls of the second openings are recessed relative to the sidewalls of the third opening, and the conductive plug is also located in the third opening. 14 . The method for forming a semiconductor structure according to claim 13 , wherein the composite layer further comprises: a second film layer located on the barrier layer, the second film layer having a fourth opening therein, 14 . The side wall of the fourth opening is recessed relative to the side wall of the third opening, and the conductive plug is also located in the fourth opening. 15 . The method for forming a semiconductor structure according to claim 14 , wherein the materials of the first film layer and the barrier layer are different; and the materials of the second film layer and the barrier layer are different. 16 . 16. The method for forming a semiconductor structure according to claim 15, wherein the material of the first film layer comprises aluminum nitride; the material of the second film layer comprises aluminum nitride. 17 . The method for forming a semiconductor structure according to claim 15 , wherein the material of the barrier layer comprises carbon-doped silicon nitride. 18 . 18. The method for forming a semiconductor structure according to claim 12, wherein the forming process of the second opening comprises an isotropic wet etching process. 19 . The method for forming a semiconductor structure according to claim 14 , wherein the forming process of the fourth opening comprises an isotropic wet etching process. 20 . 20 . The method for forming a semiconductor structure according to claim 13 , wherein the formation process of the third opening comprises an anisotropic dry etching process. 21 . 21. The method for forming a semiconductor structure according to claim 14, wherein the method for forming the conductive plug comprises: adopting a metal selective growth process on the first opening, the second opening, the third opening and the forming initial conductive plugs in the fourth opening and on the top surface of the dielectric layer; performing a planarization process on the initial conductive plugs until the top surface of the dielectric layer is exposed to form the conductive plugs . 22. The method for forming a semiconductor structure according to claim 12, wherein the material of the conductive plug comprises tungsten. 23. The method for forming a semiconductor structure according to claim 21, wherein the planarization process comprises a chemical mechanical polishing process. 24. The method for forming a semiconductor structure according to claim 12, wherein the material of the conductive layer comprises cobalt. 25. The method of forming a semiconductor structure of claim 12, wherein the device structure comprises a transistor structure. 26. The method for forming a semiconductor structure according to claim 25, wherein the transistor structure comprises: a gate structure located on the substrate; source-drain dopant located in the substrate on both sides of the gate structure Miscellaneous layers. 27. The method for forming a semiconductor structure according to claim 26, wherein the conductive layer is located on the source-drain doped layer or the gate structure.

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