CN114113893A - Method for rapidly testing fault of interconnection line inside micro-system chip - Google Patents
Method for rapidly testing fault of interconnection line inside micro-system chip Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
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Abstract
本发明涉及一种微系统芯片内部互联线故障快速测试方法，包括故障定位算法、微系统芯片测试板、ATE、测试机台程序，测试方法通过调用故障定位算法生成相应的配置向量和测试向量，同时基于ATE平台设计的测试机台程序调用配置向量对微系统芯片进行配置，包括如下步骤：按照待测微系统芯片需求焊接微系统芯片测试板；连接微系统芯片、微系统芯片测试板和测试机；依据微系统芯片互联测试算法生成配置向量和测试向量；测试机将配置向量通过JTAG接口烧写入内部芯片；测试机对管脚输入相应的信号；对比测试向量和响应向量是否一致进而判断芯片是否故障。本发明测试方法在不增加成本的基础上，将微系统芯片内部互联线故障精准定位并且能够快速实现。
The invention relates to a rapid testing method for interconnecting line faults in a microsystem chip, comprising a fault location algorithm, a microsystem chip test board, an ATE, and a test machine program. The test method generates corresponding configuration vectors and test vectors by invoking the fault location algorithm. At the same time, the test machine program designed based on the ATE platform calls the configuration vector to configure the micro system chip, including the following steps: welding the micro system chip test board according to the requirements of the micro system chip to be tested; connecting the micro system chip, the micro system chip test board and the test board The configuration vector and test vector are generated according to the micro-system chip interconnection test algorithm; the test machine writes the configuration vector into the internal chip through the JTAG interface; the test machine inputs the corresponding signal to the pin; compares the test vector and the response vector to determine whether they are consistent Whether the chip is faulty. The testing method of the present invention accurately locates the faults of the interconnection lines in the micro-system chip and can be realized quickly without increasing the cost.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a method for rapidly testing faults of interconnection lines in a micro-system chip.
Background
The microsystem chip is formed by integrating a plurality of functional chips including a processor, a memory and the like into a package, thereby realizing a basically complete function. The microsystem chip does not need a PCB board as a carrier for connecting chips, and the problem that the system performance is bottleneck due to inherent deficiency of the PCB can be solved. The microsystem chip has the characteristics of short development period, multiple functions, low power consumption, better performance, low cost price, small volume and light weight, and is widely applied to the fields of aerospace and the like.
Microsystem chip interconnect testing, in short, involves configuring the internal sub-module chips into corresponding test patterns and then applying specific test vectors. A good test method is to quickly locate a specific failed interconnect line at as high a fault coverage as possible.
However, the microsystem chip is usually tested by a functional verification method, but it is difficult to precisely locate the fault location when the functional test fails.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the problem that the fault position is difficult to accurately position under the condition of functional test failure in the prior art, thereby providing a method for rapidly testing the fault of the interconnection line in the micro-system chip.
In order to solve the technical problems, the invention provides a method for rapidly testing the fault of an interconnection line in a micro system chip, which comprises a fault positioning algorithm, a micro system chip test board, ATE (automatic test equipment) and a test machine program, wherein the test method generates a corresponding configuration vector and a test vector by calling the fault positioning algorithm, the test machine program designed on the basis of an ATE platform calls the configuration vector to configure the micro system chip, and the test machine program calls the test vector to judge the fault of the interconnection line in the micro system chip, and the method comprises the following steps:
step S1: welding a micro system chip test board according to the requirement of a micro system chip to be tested;
step S2: connecting the micro-system chip, the micro-system chip test board and the tester;
step S3: generating a configuration vector and a test vector according to a micro system chip interconnection test algorithm;
step S4: the tester writes the configuration vector into the internal chip through the JTAG interface;
step S5: the testing machine inputs corresponding signals to the pins;
step S6: and comparing whether the test vector is consistent with the response vector so as to judge whether the chip fails.
In an embodiment of the present invention, the fault location algorithm is to configure a chip into a corresponding test model and generate a test vector by analyzing a boundary scan file of the chip and a netlist file of a microsystem.
In an embodiment of the present invention, the microsystem chip to be tested, the microsystem chip test board and the ATE are hardware components of the test method.
In one embodiment of the invention, the ATE test platform is built by using an edwang 93000 tester.
In an embodiment of the present invention, the test machine program calls the configuration vector to perform fault model configuration on the micro system chip, and calls the test vector to perform testing on the internal interconnection line of the micro system chip.
Compared with the prior art, the technical scheme of the invention has the following advantages: according to the method for rapidly testing the faults of the interconnection lines in the micro-system chip, the faults of the interconnection lines in the micro-system chip are accurately positioned and can be rapidly realized on the basis of not increasing the cost by directly testing the faults of the interconnection lines in the micro-system chip through ATE.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.
FIG. 1 is a schematic block diagram of a method for rapidly testing a fault of an internal interconnection line of a micro system chip according to the present invention;
FIG. 2 is a schematic diagram of a comparative architecture of an internal interconnection network of a typical microsystem chip;
FIG. 3 is a schematic diagram comparing the boundary scan configuration of a typical chip;
FIG. 4 is a general flow chart of the test of the method for rapidly testing the fault of the internal interconnection line of the microsystem chip.
Detailed Description
As shown in fig. 1 and fig. 4, this embodiment provides a method for rapidly testing a fault of an interconnection line in a microsystem chip, including a fault location algorithm, a microsystem chip test board, ATE, and a test machine program, where the test method generates a corresponding configuration vector and a test vector by calling the fault location algorithm, and at the same time, the test machine program designed based on an ATE platform calls the configuration vector to configure the microsystem chip, and the test machine program calls the test vector to perform fault judgment on the interconnection line in the microsystem chip, and the method includes the following steps:
step S1: welding a micro system chip test board according to the requirement of a micro system chip to be tested;
step S2: connecting the micro-system chip, the micro-system chip test board and the tester;
step S3: generating a configuration vector and a test vector according to a micro system chip interconnection test algorithm;
step S4: the tester writes the configuration vector into the internal chip through the JTAG interface;
step S5: the testing machine inputs corresponding signals to the pins;
step S6: and comparing whether the test vector is consistent with the response vector so as to judge whether the chip fails.
Further, taking a typical microsystem chip as an example, fig. 2 is an internal interconnection network of the typical microsystem chip. FIG. 3 is a diagram of a typical chip boundary scan architecture. Assuming that the PINA of the DSP of FIG. 2 and the connection between the FPGA and the PINB are to be tested, the following procedures are required:
the first step is as follows: analyzing an EXTEST instruction of the DSP through a boundary scan file BSDL of the DSP;
the second step is that: analyzing an EXTEST instruction of the FPGA through a boundary scan file BSDL of the FPGA;
the third step: firstly, controlling the PINA to be output and the PINB to be input through a boundary scan EXTEST instruction;
the fourth step: PINA output is high, and PINB recognition is high;
the fifth step: PINA output is low, and PINB recognition is low;
and a sixth step: secondly, controlling the PINB to be output and the PINA to be input through a boundary scan EXTEST instruction;
the seventh step: the output of the PINB is high, and the PINA recognition is high;
eighth step: PINB output is low and PINA recognition is low.
Furthermore, the DSP of the first step is a digital signal processing chip, a Harvard structure with separated programs and data is adopted in the DSP chip, a special hardware multiplier is provided, pipeline operation is widely adopted, special DSP instructions are provided, and various digital signal processing algorithms can be rapidly realized. The BSDL file is a description of IEEE1149.1 or JTAG design spreadsheet in an IC, the EXTEST instruction means that the IC works in a boundary scan external test mode, namely, the operation of the IC influences the normal work of a chip and is used for chip external test, an output pin in the test mode has BSC update latch driving, BSCscan latches captured input data shift operation, test excitation can be input from TDI, and test response can be observed from TDO. After the shift operation, the new test stimulus is stored into the update latch of the BSC. The FPGA of the second step is a product which is further developed on the basis of programmable devices such as PAL, GAL and the like, and appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), thereby not only solving the defects of the custom circuit, but also overcoming the defect that the gate circuit number of the original programmable device is limited.
The PINA and the PINB in the third step refer to a port pin with a boundary register.
The fourth and fifth steps are identified by the boundary scan command by changing the output high and low of the PINA, the PINB.
The sixth step is reverse test, which inverts the port states of the PINA and the PINB and changes the input state into the output state
And the output state is changed into the input state.
The seventh step and the eighth step are identified by changing the output high and low of the PINB through a boundary scanning instruction.
The fault location algorithm is to configure the chip into a corresponding test model and generate a test vector by analyzing a boundary scan file of the chip and a netlist file of the microsystem.
The micro-system chip to be tested, the micro-system chip test board and the ATE are hardware components of the test method.
The ATE test platform is built by an Edwarden 93000 tester.
And the test machine platform program calls the configuration vector to carry out fault model configuration on the micro system chip and calls the test vector to test the internal interconnection line of the micro system chip.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.
Claims (5)
1. A quick test method for the fault of the interconnection line in the micro system chip comprises a fault positioning algorithm, a micro system chip test board, ATE and a test machine program, wherein the test method generates a corresponding configuration vector and a test vector by calling the fault positioning algorithm, the test machine program designed based on an ATE platform calls the configuration vector to configure the micro system chip, and the test machine program calls the test vector to judge the fault of the interconnection line in the micro system chip, and the quick test method is characterized by comprising the following steps:
step S1: welding a micro system chip test board according to the requirement of a micro system chip to be tested;
step S2: connecting the micro-system chip, the micro-system chip test board and the tester;
step S3: generating a configuration vector and a test vector according to a micro system chip interconnection test algorithm;
step S4: the tester writes the configuration vector into the internal chip through the JTAG interface;
step S5: the testing machine inputs corresponding signals to the pins;
step S6: and comparing whether the test vector is consistent with the response vector so as to judge whether the chip fails.
2. The method for rapidly testing the fault of the interconnection line inside the micro-system chip according to claim 1, wherein the method comprises the following steps: the fault location algorithm is to configure the chip into a corresponding test model and generate a test vector by analyzing a boundary scan file of the chip and a netlist file of the microsystem.
3. The method for rapidly testing the fault of the interconnection line inside the micro-system chip according to claim 1, wherein the method comprises the following steps: the micro-system chip to be tested, the micro-system chip test board and the ATE are hardware components of the test method.
4. The method for rapidly testing the fault of the interconnection line inside the micro-system chip according to claim 1, wherein the method comprises the following steps: the ATE test platform is built by an Edwarden 93000 tester.
5. The method for rapidly testing the fault of the interconnection line inside the micro-system chip according to claim 1, wherein the method comprises the following steps: and the test machine platform program calls the configuration vector to carry out fault model configuration on the micro system chip and calls the test vector to test the internal interconnection line of the micro system chip.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115453324A (en) * | 2022-09-22 | 2022-12-09 | 电子科技大学(深圳)高等研究院 | SIP chip internal interconnection testing method based on ATE |
| CN116500422A (en) * | 2023-05-08 | 2023-07-28 | 海光集成电路设计(北京)有限公司 | A chip parallel test system and test method based on a system-level test platform |
| CN116859226A (en) * | 2023-09-04 | 2023-10-10 | 中国电子科技集团公司第五十八研究所 | Test circuit for 2.5D double-core interconnection packaging system |
| CN117151032A (en) * | 2023-10-27 | 2023-12-01 | 零壹半导体技术(常州)有限公司 | Test method for detecting PCB (printed circuit board) by ATE (automatic test equipment) based on Kelvin |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117151032B (en) * | 2023-10-27 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | Test method for detecting PCB (printed circuit board) by ATE (automatic test equipment) based on Kelvin |
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