Disclosure of Invention
The application provides a microelectrode measuring device, which comprises a measuring body, wherein the measuring body is connected with a pre-amplification module, the pre-amplification module is connected with an acquisition processing module, the acquisition processing module is connected with a voltage stimulation module, and the voltage stimulation module is connected with the measuring body; the acquisition processing module is also connected with an upper computer.
Preferably, a high-impedance solid-state switch is arranged between the voltage stimulation module and the measuring body.
As a preferred scheme, the pre-amplification module comprises a first-stage input amplifier, a second-stage amplifier and a final-stage amplifier which are connected in sequence.
Preferably, the measuring body comprises 64 channel microelectrodes, and the 64 microchannel electrodes form a microelectrode array.
As a preferred scheme, the acquisition processing module comprises an FPGA chip, and the FPGA chip is respectively connected with the AD chip and the USB chip.
A microelectrode measurement method comprises the following steps:
s1: the measuring body generates weak voltage signals with low driving force;
s2: transmitting the signal to a pre-amplification module;
s3: the pre-amplification module amplifies the signal, and the signal has certain driving capability while being amplified;
s4: the acquisition processing module samples signals;
s5: the acquisition processing module sends the sampling data to an upper computer;
s6: the acquisition processing module generates a stimulation waveform according to the input of the upper computer;
s7: the voltage stimulation module stimulates the microelectrode of the measuring body.
As a preferable scheme, the method further comprises the following steps of S8: the acquisition circuit does not need to be disconnected in the process of generating the stimulation voltage.
As a preferable scheme, the S3 is specifically:
s31: directly amplifying the signal by 100 times, and enabling the signal to have certain driving capability while amplifying the signal;
s32: and amplifying for the second time, wherein the signal is amplified to be suitable for the amplitude sampled by the acquisition processing module.
As a preferable scheme, the S4 is specifically:
s41: 100Kfps sampling and 16-bit sampling precision are realized by using a multi-channel ADC (analog to digital converter);
s42: sampling at 50kfps and 25kfps is realized through FPGA extraction;
preferably, the space between S6 and S7 further includes S6.1:
s6.1: and when the output range of the acquisition processing module does not meet the requirement, the pre-amplification module is controlled to amplify.
The invention not only needs to measure the weak voltage of each channel of the measuring body, but also needs to apply voltage stimulation to each channel, and the measured result is displayed, processed and stored by an upper computer; the microelectrode sampling device can sample signals of each path of microelectrode, can apply stimulation signals to each path of microelectrode, program a plurality of microelectrodes at the same time, control the sampling rate of equipment, control the amplification factor of the equipment, and transmit the sampled data through a USB3.0 interface; the invention has simple structure and convenient use, controls each parameter through the simple structure and improves the accuracy of measurement.
Detailed Description
The following detailed description of the embodiments of the present invention is made with reference to fig. 1 to 10; it should be noted that the specific embodiments described herein are only for illustrating and explaining the present invention and are not to be construed as limiting the present invention.
The first embodiment is as follows:
the application provides a microelectrode measuring device, which comprises a measuring body, wherein the measuring body comprises a culture dish 1, the lower part of the culture dish is connected with a substrate 2, a plurality of electrodes 3 are distributed on the periphery of the substrate 2, preferably, 64 microelectrodes and 4 groups of grounds are distributed in the center of the culture dish 1, the microelectrode array is designed according to the mode that each 16 electrodes correspond to one group, cells are placed in the culture dish 1, the voltage of the cells to be measured is extracellular voltage, and the voltage range is usually only between 5uV and 100 uV; the measuring body is connected with the pre-amplification module 4, the electrodes of the microelectrode array are output to the pre-amplification module 4, the pre-amplification module 4 is used for amplifying the output voltage of the electrodes, and the amplified voltage has certain driving capability; the preamplification module 4 is connected with the acquisition processing module 5, the acquisition processing module 5 is connected with the voltage stimulation module 6, and the voltage stimulation module 6 is connected with the measuring body, namely the voltage stimulation module 6 is connected with the microelectrode array; the acquisition processing module 5 is also connected with an upper computer 7, and preferably, the acquisition processing module 5 is connected with the upper computer 7 through a USB3.0 interface; the acquisition processing module 5 is used for sampling, sending data to the upper computer 7 for display, processing and storage, the upper computer 7 controls the acquisition processing module 5 to generate stimulation waveforms, the voltage stimulation circuit 6 stimulates the microelectrode of the measuring body, and the arrangement of the stimulation circuit can reduce the input impedance of the measuring circuit; when the stimulation waveform range output by the acquisition processing module 5 does not meet the requirement, the acquisition processing module 5 controls the pre-amplification module 4 to amplify.
The technical parameters of the application are referred to as follows:
(1) input impedance of the amplification module: 200G ohm 2 pf;
(2) magnification: 1 × 104-2 × 105 times;
(3) amplifying the voltage range: -1V to + 1V;
(4) frequency response range: 10Hz to 10 kHz;
(5) sampling rate: 25kfps, 50kfps or 100 kfps;
(6) stimulation output: -4 to +4V, limit: 200uA/0.1 ms.
In the embodiment, not only the weak voltage of each channel of the measuring body, namely the weak voltage of the microelectrode array, needs to be measured, but also the voltage stimulation needs to be applied to each channel, and the measurement result is displayed, processed and stored by the upper computer 7; the embodiment can complete the sampling of each path of microelectrode signal, can apply stimulation signals on each path of microelectrode, program a plurality of microelectrodes at the same time, control the sampling rate of equipment, control the amplification factor of the equipment, and transmit the sampled data to the upper computer 7 through a USB3.0 interface; the invention has simple structure and convenient use, controls each parameter through the simple structure and improves the accuracy of measurement.
Example two:
in this embodiment, in order to reduce the input impedance of the measurement circuit, a high-impedance solid-state switch 8 is arranged between the voltage stimulation module 6 and the measurement body, the high-impedance solid-state switch 8 preferably adopts a solid-state relay, the internal resistance of the solid-state relay is generally 100M ohm, and is one order of magnitude different from the G ohm of the electrode of the cell to be measured; the design of this embodiment enables the input impedance of the measuring circuit to be reduced and the provision of the high impedance solid state switch 8 enables control of whether stimulation can be performed on the measuring body.
Example three:
the embodiment can improve the working efficiency, and particularly, because the input paths are more, the sampling circuit adopts a multi-channel scanning type AD, the circuit scale of the rear end can be reduced, the sampling circuit is transmitted to the upper computer 7 through a USB3.0 interface after being simply processed by the FPGA, and the data format required by the existing mature processing software of the upper computer is consistent with the previous data processing format, so the workload of software development can be saved.
Specifically, the acquisition processing module 5 comprises an FPGA chip, the FPGA chip is respectively connected with an AD chip and a USB chip, the USB chip adopts a USB3.0 chip, and the USB3.0 chip is connected with the upper computer 7; the FPGA chip is connected with the amplifier group of the amplifying module 4; the AD chip comprises a sampling original chip, a multiplexing switch chip and an output chip.
More specifically, the expected effective signal frequency of the acquired data is only 10KHZ, the upper limit value of the sampling frequency is 100kfps for facilitating the display of the time domain, 64 paths of input are shared, the high sampling rate is selected, an AD product with a multi-path selection switch is repeatedly compared, AD7616-P is selected as a sampling original, namely the type of the sampling original of the AD chip is AD7616-P, the type of the multiplexing switch of the AD chip is ADG658, and the type of the output chip of the AD chip is AD 5753; 4 AD7616-P sampling chips are selected to meet the sampling requirement; AD7616-P has the following characteristics:
(1) 16-way independent input
(2) Two independent ADCs with sampling rate of 1Mfps and sampling precision of 16 bits;
(3) the parallel port output function is provided, so that FPGA programming can be simplified;
(4) positive and negative voltage sampling can be supported;
according to the above description, the functions that the FPGA chip, i.e., the main control chip of the acquisition and processing module needs to implement are:
(1) controlling 4 AD7616P chips, wherein the highest working clock on the chip is 1MHz, 27 pins are needed, and a certain margin is reserved for wiring, so that each chip needs 30 pins, and 4 chips need 120 pins;
(2) an AD5753 chip is controlled, the AD5753 chip is used for controlling the output of voltage, the highest working clock of the chip is 1Mhz, and 10 pins are needed;
(3) control 8 solid state switches ADG658, requiring 24 pins;
(4) 8 pins are needed for controlling a final amplifier LTC1564 in 64 preamplification modules;
(5) USB3.0 local BUS pins, 40 pins are required;
(6) other interfaces need to reserve 30 pins
According to the description above, 232 effective pins are needed in total, and the device is supposed to use a xilinx sbada 7 chip XC7S50 chip, namely the FPGA chip is XC7S50 chip in type; the chip is the latest low-cost high-performance FPGA chip of xilinx company, an MB processor is arranged in the chip, later-stage upgrading application and expansion functions are facilitated, and 250 pins can be used for an XC7S50 chip, so that the requirement of high equipment can be met.
Example four:
the present embodiment specifically defines the pre-amplification module 4, specifically, the pre-amplification module 4 adopts a pre-amplifier, and the circuit structure of the pre-amplifier is as shown in fig. 3; more specifically, the key of the design of the front-end circuit is high impedance and low noise, a J-fet operational amplifier with high input impedance is selected to realize high impedance, and an ultralow ripple DC-DC module is used for supplying power to the amplifier; the circuit uses a basic voltage series negative feedback circuit, as shown in fig. 4, to achieve maximum input impedance invariance; the amplification factor of the circuit is set to be 100 times, so that the output voltage can reach 500 uV-10 mV after passing through the preamplifier; and has a certain driving capability.
In order to prevent self-excitation, the amplification factor of each stage is not too large, the amplification factors of the first two sets are set to be 100 times, so that the voltage from 50mV to 1V can be obtained, the last stage of amplifier is provided with an adjustable gain and an adjustable bandwidth anti-aliasing filter, the maximum amplification factor is 16 times, so that the minimum voltage can be amplified to 0.8V, the maximum voltage can reach 16V, the amplification factor of the front stage fixed amplification factor amplifier can be further adjusted according to the later test condition, and the adjustment range can reach the optimal state.
Example five:
the present embodiment specifically defines the preamplifier, and specifically, the preamplifier includes a first-stage input amplifier, a second-stage amplifier, and a final-stage amplifier.
First-stage and first-stage input amplifier
As shown in FIG. 5, the input amplifier of the first stage is selected from a J-FET input operational amplifier, ADA4622-4, and has the following characteristics:
(1) input impedance: differential mode capacitance 0.4pf, input resistance 1013 ohm;
(2) the pass bandwidth is 8 MHz;
(3) 4KV electrostatic protection;
(4) the input pin withstand voltage of 36V can be directly applied with the stimulation voltage without disconnecting the subsequent circuit.
In order not to affect the input resistance, the forward input pin of ADA4622 is not connected to any back-end feedback circuit.
Because the input signal of the front-end circuit is extremely weak, the power supply of the front-end amplifier should be particularly noted, ADP5070 of ADI is selected to generate positive and negative voltages which are provided for the ultra-low noise LDO to be reduced in voltage, and the positive and negative voltages are provided for the J-FET amplifier at the front end after being reduced in voltage; processing is performed using the circuit shown in fig. 5; the advantages brought by the adoption of the circuit are as follows:
(1) in order to avoid extra noise and errors caused by circuit biasing, the whole amplifying circuit is completely powered by a positive power supply and a negative power supply;
(2) the ADP5070 can generate positive and negative voltages at one time, and is well balanced;
(3) AD7118 and ADP7182 are very low noise LDO devices;
(4) the first stage amplification is provided with the purest power supply through a one-to-two structure.
Second and secondary amplifier
The positive power supply and the negative power supply are used for continuously amplifying the voltage signals, the amplifier also adopts a fixed amplification factor of 100 times, and the secondary amplifier only needs to use a common operational amplifier with a bandwidth higher than that of the primary amplifier.
Three, last stage amplifier
The final amplifier adopts LTC1564, and a functional block diagram of the LTC1564 is shown in FIG. 6, so that 4-bit amplification factor programming and 4-bit anti-aliasing filter setting can be realized, and finally, a signal is input into an AD device.
(1) The magnification is 1-16 times;
(2) the frequency of the low-pass filter is 10 to 150 kHz;
LTC1564 controls gain through 4-wire parallel, and 4-wire parallel controls frequency, can directly realize gain control and anti-aliasing filter setting.
Example six:
the embodiment specifically limits the voltage stimulation module, adopts a voltage stimulation circuit, and more specifically adopts a chip AD5753, wherein the AD5753 has 1-path current output, and can directly generate a current of plus or minus 20mA, and limit the power supply voltage of the AD5753, so that the highest output voltage of the AD5753 does not exceed 4V.
(1) Selecting proper power supply voltage to control the highest voltage not to exceed plus or minus 4V;
(2) signals were coupled to any of the 64-way microelectrodes using 8 ADG658 chips.
Example seven:
the embodiment provides more specific structural limitation to the microelectrode measuring device of the invention, and specifically comprises a culture dish 1, wherein the culture dish is connected with a substrate 2, a microelectrode is arranged on the substrate 2, and a simulation board 9 is arranged on the upper part of the substrate; a digital plate 10 is arranged at the lower part of the substrate 2; in this embodiment, the device is mainly divided into two layers, the analog board is an upper layer, the digital board is a lower layer, and as shown in fig. 8, the upper layer is a microelectrode, and the microelectrode signal is fanned out, and the signal is amplified to the secondary amplifier for output on the first layer circuit.
The layout of the main devices of the analog board circuit is described as follows:
(1) the circuit closest to the microelectrode is a Jfet amplifying circuit;
(2) surrounding the JFET circuit is a multi-way switch of the stimulation circuit;
(3) the circuit surrounding the relay is a second signal amplifying circuit;
(4) power and other ancillary functions are handled in the blank.
The second layer circuit mainly comprises an acquisition control circuit, amplification and acquisition processing are carried out before AD is completed on the second layer circuit, an external interface is also positioned on the second layer, and the structure is shown in fig. 9 and mainly comprises:
(1) an FPGA circuit;
(2) AD acquisition and pre-stage amplification;
(3) DA control and buffer processing.
(4) USB interface implementation
(5) Blanks are used for processing power supplies and the like.
Example eight:
the embodiment provides a microelectrode measurement method, which comprises the following steps:
s1: the measuring body generates weak voltage signals with low driving force; particularly, a microelectrode array generates extremely weak voltage signals driving the polar region;
s2: the signal is transmitted to the preamplification module 4; in particular, AC coupled to a preamplifier with an input impedance of up to 1013Ohm 0.6 pf;
s3: the preamplification module 4 amplifies the signal, and the signal has certain driving capability while being amplified; the method specifically comprises the following steps: s31: directly amplifying the signal by 100 times, and enabling the signal to have certain driving capability while amplifying the signal; s32: amplifying for the second time, namely amplifying the signal by adopting a numerical control gain amplifier to adapt to the amplitude sampled by the acquisition processing module, more specifically amplifying the signal by adopting the amplitude acquired by the ADC;
s4: the acquisition processing module 5 samples signals; specifically, S41: 100Kfps sampling and 16-bit sampling precision are realized by using a multi-channel scanning ADC (analog to digital converter); s42: sampling at 50kfps and 25kfps is realized through FPGA extraction;
s5: the acquisition processing module 5 sends the sampling data to the upper computer 7;
s6: the acquisition processing module 5 generates a stimulation waveform according to the input of the upper computer 7; the stimulation process is opposite to the collection process;
s7: the voltage stimulation module 6 stimulates the microelectrode of the measuring body, in particular to connect the high internal resistance solid-state switch 8 to the microelectrode which needs stimulation.
As a preferable scheme, the method further comprises the step of S8: the acquisition circuit does not need to be disconnected in the process of generating the stimulation voltage.
As a preferable scheme, the method further comprises S6.1: S6.1 between S6 and S7, wherein when the output range of the acquisition processing module does not meet the requirement, the pre-amplification module is controlled to amplify; specifically, when the output range of the DAC does not meet the requirement, the amplifier is controlled to amplify.
In summary, due to the adoption of the technical scheme, the weak voltage of each channel of the measuring body is measured, voltage stimulation needs to be applied to each channel, and the measurement result is displayed, processed and stored by the upper computer; the microelectrode sampling device can sample signals of each path of microelectrode, can apply stimulation signals to each path of microelectrode, program a plurality of microelectrodes at the same time, control the sampling rate of equipment, control the amplification factor of the equipment, and transmit the sampled data through a USB3.0 interface; the invention has simple structure and convenient use, controls each parameter through the simple structure and improves the accuracy of measurement.
The devices and connection relationships that are not described in detail above all belong to the prior art, and the present invention is not described in detail herein.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are included in the scope of protection of the present invention.
It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present application will not be described separately.
In addition, any combination of the various embodiments of the present application can be made, and the present application should be considered as disclosed in the present application as long as the combination does not depart from the spirit of the present application.