CN114035767B

CN114035767B - Instruction design method for TEC-XP16 combinational logic controller

Info

Publication number: CN114035767B
Application number: CN202110995071.XA
Authority: CN
Inventors: 宗德才; 王康康
Original assignee: Changshu Institute of Technology
Current assignee: Changshu Institute of Technology
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2024-07-09
Anticipated expiration: 2041-08-27
Also published as: CN114035767A

Abstract

The application provides a method for designing an instruction of a TEC-XP16 combinational logic controller, which comprises the following steps: using the teaching machine assembly instruction design to realize a teaching machine assembly language source program corresponding to the instruction to be designed; automatically generating beat signals and control signals according to the teaching machine assembly language source program and beat conversion relations; leading beat signals, control signals and beat conversion relations into simulation software of a designed teaching machine combination logic controller for simulation; after the simulation is passed, automatically generating a source program file of the combinational logic controller capable of executing the designed instruction according to the beat signal, the control signal and the beat conversion relation; compiling a source program file of the combinational logic controller, and downloading the JED file generated after compiling into a MACH chip of the teaching machine; and writing the teaching machine assembly language source program containing the designed instructions for verification. The method provided by the application simplifies the beat conversion relation logic expression and the control signal logic expression.

Description

Instruction design method for TEC-XP16 combinational logic controller

Technical Field

The application relates to the technical field of combination logic controllers, in particular to a method for designing an instruction of a TEC-XP16 combination logic controller.

Background

According to the different compositions and different operating principles of the command step marking circuit and the control signal generating circuit, there are two controllers: a combinational logic controller and a micro-program controller. The combination logic controller adopts a combination logic circuit and directly generates control signals according to the instructions and the execution steps thereof. The micro-program controller uses a memory circuit to store the control signals and reads out the signal combinations to be used according to the steps of instruction execution.

The combinational logic controller consists of 4 parts of a program counter PC, an instruction register IR, a beat generator Timer and a control signal generation unit CU. The PC is used for providing the address of the command to be read in the main memory, the IR is used for saving the command content read from the main memory, the Timer is used for giving and maintaining the code (beat state code) of the command execution step, and the control signal generating part is used for generating control signals required by each part in the computer operation step by using a combinational logic circuit according to the command content (in the IR) and the operation step (beat state code) where the command execution is. The combined logic controller in the TEC-XP16 teaching machine is mainly realized by MACH devices.

In the TEC-XP16 teaching machine, the control signals of the control arithmetic unit in the 32-bit control signals sent by the combination logic controller are 23-bit I8I7I6, I5I4I3, I2I1I0, A3A2A1A0, B3B2B1B0, SST2SST1SST0, SSHSCI1SCI0, the control signals for controlling the memory or I/O interface are 3-bit MIO, REQ and_WE, the control signals for controlling the internal bus data sources are 3-bit DC1_2, DC1_1 and DC1_0, and the control signals received by the control special registers are 3-bit DC2_2, DC2_1 and DC2_0.

At present, the experimental teaching contents of the composition principle of a plurality of college computers in China are mainly developed based on a TEC-XP16 computer composition principle experimental system developed by a Qinghai university computer, and the experimental contents of the courses are remained in a verification experiment stage, so that students can better grasp the working principle of each component part of the computer, understand the execution flow of instructions, systematically establish the whole computer concept, cultivate the design and innovation capability of the students, cultivate the analysis, application, design and development capability of the students on the computer system, and need to develop some design experiments based on the TEC-XP16 teaching machine, such as designing some complex instructions, such as floating point operation instructions for a combined logic controller of the TEC-XP16 teaching machine.

At present, the specific process of designing instructions in a combined logic controller of a TEC-XP16 teaching machine is as follows:

(1) Determining the format and function of the instruction;

(2) Dividing the execution steps of the instruction, designing the execution function of each step, and designing the value of the beat state;

(3) Filling state of beats in the instruction execution flow chart, and state value of each control signal under each beat state;

(4) Adding a logic expression of a control signal of a designed expansion instruction into an ABEL language source file of the existing MACH device, compiling and adapting, and then downloading the logic expression into the MACH device;

(5) Programming a program containing the designed expansion instruction, and checking the correctness of the execution result by running the program to verify whether the designed expansion instruction is correct.

The process of designing instructions described above is purely manual and is suitable for designing simple instructions. However, when designing complex instructions, the execution stage of some complex instructions often needs hundreds of beats, for a TEC-XP16 teaching machine, each beat will generate 32-bit control signals, if the complex instructions requiring hundreds of beats are designed and executed by the pure manual mode, the complex instructions are very low in efficiency, only the (2) step and the (3) step are completed, and are very easy to make mistakes, errors are difficult to find after mistakes, the cost of correcting mistakes is very high, if the value of one control signal in a certain beat in the (3) step is artificially designed to make mistakes, the mistakes cannot be found until the (5) step runs a program containing the designed expansion instructions, and due to the lack of debugging tools for the instruction control signals and the beat signals, the mistakes and the beat signals are determined as if the sea fishing pins, the ABEL language source files of the MACH device are modified and recompiled after the mistakes and the mistakes are recompiled, and then the mistakes are downloaded to the MACH chip, and the efficiency is very low. Step (4) adds the logic expression of the control signal of the designed expansion instruction into the ABEL language source file of the existing MACH device, so that the efficiency is low, mistakes are easy to occur after carelessness, and the MACH device needs to be recompiled after mistakes are corrected and then downloaded into a MACH chip again.

Disclosure of Invention

The application provides a method for designing an instruction of a TEC-XP16 combinational logic controller, which comprises the following steps:

Using the teaching machine assembly instruction design to realize a teaching machine assembly language source program corresponding to the instruction to be designed;

generating beat signals and control signals according to the teaching machine assembly language source program and beat conversion relations;

importing the beat signal, the control signal and the beat conversion relation into designed TEC-XP16 teaching machine combinational logic controller simulation software to simulate;

After the simulation is passed, generating a source program file of a combination logic controller corresponding to the TEC-XP16 teaching machine according to the beat signal, the control signal and the beat conversion relation;

And compiling a source program file of the combinational logic controller, and downloading the JED file generated after compiling into a MACH chip of the teaching machine.

Optionally, generating the beat signal, the control signal and the beat conversion relation according to the teaching machine assembly language source program includes:

(1) Looking up Iname a FIRSTTIME field value of a record of the designed instruction name from a pre-established INSTFIRSTTIME table and assigning to the bean variable;

(2) Searching NewIname a maximum Number field value of all records of the designed instruction name from a pre-established AsblProgram table, marking maxN, and enabling i=1;

(3) Searching a record of which NewIname is the designed instruction name and the Number field is equal to i in AsblProgram tables, and recording the record AsbInsti;

(4) For record AsbInsti, if Iname of record AsbInsti is JR, JRZ, JRNZ, JRC, JRNC, JRS, JRNS, RET instruction, the control signal at the time of instruction PSHF, POPF, CLC execution is fixed, then the control signal generated in table ControlSignal is fixed; MVRR, OR, AND, ADD, SUB, XOR, TEST, ADC, CMP the instruction needs to set according to the register number in the instruction except the B port address and the A port address, and other control signals are fixed; the SHR, RCR, SHL, INC, DEC instruction has fixed control signals except that the address of the B port needs to be set according to the number of a register in the instruction; MVRD DATA instruction to generate a control signal according to a predetermined algorithm 1;

If Iname of record AsbInsti is any one of MVRR, OR, AND, ADD, SUB, XOR, TEST, ADC, CMP, SHR, RCR, SHL, INC, DEC, CLC, RET, a record is generated in timeConversion table, and NextTime field value is CurrentTime field value plus 1;

if Iname of record AsbInsti is MVRD, generating a beat signal at timeConversion according to the algorithm 1;

if Iname of record AsbInsti is JR, then a record is generated in timeConversion table, nextTime field value is generated according to algorithm 2;

if Iname of the record AsbInsti is any one of JRZ, JRNZ, JRC, JRNC, JRS, JRNS, two records are generated in the timeConversion table, wherein one record is the beat transition when the condition is met, the NextTime field value is generated according to the algorithm 3, the other record is the beat transition when the condition is not met, and the NextTime field value is the currentTime field value plus 1;

If Iname of the record AsbInsti is PSHF or POPF, two records are generated in the timeConversion table, wherein the NextTime field value of each record is the CurrentTime field value plus 1;

All records will generate one record in the ISEA table;

(5) I=i+1, repeating step (3) and step (4) until i > maxN ends.

Alternatively, algorithm 1 is as follows:

(1) Converting DATA into a 16-bit binary number D16;

(2) Calculating the number of 1 in D16, and recording as one (D16);

(3) Executing (4) if one (D16) >1, otherwise executing (12);

(4) Generating a control signal for a first beat, after the first beat is executed, (Ri) =1111111111111111;

(5) Calculating the beat number of D16 obtained by adopting a method of shifting Ri left and then shifting right, and recording the beat number as SLR (D16);

(6) Calculating the number of times of D16 obtained by taking Ri by a method of right shifting and left shifting, and marking the number of times as SRL (D16);

(7) If SLR (D16). Ltoreq.SRL (D16), executing (8), otherwise executing (10);

(8) Generating a control signal of 16-one (D16) beats, each beat shifted left by one bit Ri;

(9) Generating a control signal of SLR (D16) +one (D16) -16 beats, shifting each beat by one bit Ri to the right, and ending;

(10) Generating a control signal of 16-one (D16) beats, each beat shifted by one bit Ri to the right;

(11) Generating a control signal of SRL (D16) +one (D16) -16 beats, shifting one bit Ri to the left of each beat, and ending;

(12) Calculating the number of beats of D16 obtained from 0000000000000001, recorded as SL (D16), then obtaining D16 from DATA requires SL (D16) +2 beats;

(13) Calculating the number of beats of D16 obtained by 1111111111111, namely SLR (D16), and obtaining D16 from DATA requires SLR (D16) +1 beats;

(14) If SL (D16) +2 is less than or equal to SLR (D16) +1, executing (15), otherwise executing (18);

(15) Generating a control signal of a beat, wherein the beat is executed to obtain 0000000000000000;

(16) Generating a control signal of a beat, wherein the beat is obtained by 000000000001 after execution;

(17) Generating a control signal of SL (D16) beats, shifting one bit Ri to the left of each beat, and ending;

(18) Generating a control signal of a beat, wherein the beat is executed to obtain 1111111111111111;

(19) A control signal of SLR (D16) beats is generated, each beat is shifted one bit Ri to the left, and the process ends.

Alternatively, algorithm 2 is as follows:

(1) Searching NewIname records with the designed instruction name and Iname JR from a table of an assembly language source program AsblProgram of the teaching machine, and assuming that N records exist in the query result, enabling i to be 1;

(2) Setting the Number field value and DstAdr field value of the record i in the query result as Numberi and DstAdri respectively, if DstAdri is FINISH, updating NextTime of the record with Number field equal to Numberi in the timeConversion table to 00000000, otherwise, turning to (3);

(3) Searching a AsblProgram table for the Number field value of the record with the Label field equal to DstAdri, and marking the Number field value as DstNumber;

(4) Searching the start field value of the record with the Number field equal to DstNumber in the ISEA table, and recording the value as JRDtime;

(5) Updating NextTime field value of record whose Number field is equal to Numberi in timeConversion table to JRDtime;

(6) i=i+1, repeating steps (2) to (5) until i > N ends.

Optionally, algorithm 3 is as follows:

(1) Searching NewIname records with the designed instruction name and Iname JRZ from a table of an assembly language source program AsblProgram of the teaching machine, and assuming that the query result has M records, enabling i=1;

(2) Setting the Number field value and DstAdr field value of the record i in the query result to be Numberi and DstAdri respectively, if DstAdri is FINISH, updating NextTime of the record with Number field equal to Numberi and Condition field value of "Z= =1" in the timeConversion table to be 00000000, otherwise, turning to (3);

(5) NextTime to update records in timeConversion table with Number field equal to Numberi and Condition field value of "z= 1" is JRDtime;

(6) i=i+1, repeating steps (2) to (5) until i > M ends.

Optionally, importing the beat signal, the control signal and the beat conversion relation into the designed simulation software of the combined logic controller of the TEC-XP16 teaching machine for simulation, including:

designing simulation software of a combined logic controller of the TEC-XP 16 teaching machine as a simulation debugging tool;

The simulation software of the combined logic controller of the TEC-XP 16 teaching machine is used for importing beat signals and control signals designed for new instructions and beat conversion relations, and the combined logic controller operates in a single beat mode or continuously operates; and observing the contents of the general register, the flag bit, the IR, the AR and the 32-bit control signals after each beat runs.

And importing the beat signal, the control signal and the beat conversion relation into the simulation software of the combinational logic controller for simulation debugging.

Optionally, generating a source program of the TEC-XP 16 teaching machine combinational logic controller capable of executing the designed instructions includes:

(1) Opening a controller source program file m256.abl, and storing all lines of the read m256.abl file in a list1 list object;

(2) Connecting a new instruction database comlogicINST.db;

(3) Reading Iname a record of the designed instruction name from INSTFIRSTTIME table, and forming a character string OPstring by using Iname field value and Opcode field value;

Find the "" "Expand Instruction here" string in list1 list object, replace it with string OPstring;

(4) Reading Iname from timeConversion table the CurrentTime, nextTime, condition field value of all records of the designed instruction name, assuming n records, setting NextTime field value of record i as row [1], condition field value as row [2], currentTime field value as row [0]; i is more than or equal to 1 and n is more than or equal to n

Each beat signal is 8 bits, and is marked as T7, T6, T5, T4, T3, T2, T1 and T0; the method comprises the steps of storing current beat signals with T7 in a next beat in a beat conversion relation in a list01, storing current beat signals with T7 in the next beat in a beat conversion relation in a list01NZ, wherein the current beat signals with T7 in the next beat in the beat conversion relation in the list01NZ meet the condition Z as 0, the current beat signals with T7 in the next beat in the beat conversion relation in the list01Z meet the condition Z as 1, the current beat signals with T7 in the next beat in the beat conversion relation in the list01NC meet the condition C as 0, the current beat signals with T7 in the next beat in the beat conversion relation in the list01C meet the condition C as 1, the current beat signals with T7 in the next beat in the beat conversion relation in the list01NS meet the condition S as 0, the current beat signals with T7 in the next beat in the beat conversion relation in the list is 1, and the current beat signals with T7 in the next beat in the beat conversion relation in the list are 1;

if the row [1] [0] is 1 and the row [2] field value is null, adding the row [0] field value in the list01 list object;

If row [1] [0] is 1 and row [2] field value is 'Z= 0', then adding row [0] field value in list01NZ list object;

if row [1] [0] is 1 and row [2] field value is 'Z= 1', then adding row [0] field value in list01Z list object;

If row [1] [0] is 1 and row [2] field value is 'C= 0', then adding row [0] field value in list01NC list object;

If row [1] [0] is 1 and row [2] field value is 'C= 1', then adding row [0] field value in list01C list object;

if row [1] [0] is 1 and row [2] field value is 's= 0', then adding row [0] field value in list01NS list object;

if row [1] [0] is 1 and row [2] field value is 's= 1', then adding row [0] field value in list01S list object;

Comparing objects in the list01NZ list and the list01Z list, if the same beat signal exists, adding the beat signal to the list01, and deleting the beat signal from the list01NZ list and the list01Z list;

Comparing the objects in the list of list01NC and the list of list01C, if the same object exists, adding the object to the list of list01, and deleting the object from the list of list01NC and the list of list 01C;

comparing the objects in the list01NS list and the list01S list, if there are the same objects, adding the objects to the list01, and deleting them from the list01NS list and the list01S list;

According to the objects in the list01Z, list NZ, list01C, list01NC and list01S, list NS list, respectively, adding beat signals with conditions of 'z= =1', 'z= =0', 'c= =1', 'c= =0', 's= =1', 's= =0' to the T70 expression of the list1 list;

in order to simplify the beat conversion relation logic expression and the control signal logic expression, the design algorithm 6 is used for merging beat signals in the list, and the algorithm 7 generates a beat expression according to the merged beat signals;

obtaining a list01 after combination according to the algorithm 6; a beat expression is generated according to algorithm 7, the line where T70 is found in list1 and this beat expression is added in the T70 expression.

The method of adding beat signals in list1 list T60, T50, T40, T30, T20, T10, T00 expressions is the same as the method of adding beat signals in T70 expression;

(5) Reading Iname all records with designed instruction names from ControlSignal table, assuming t records, setting the CurrentTime field value of record I (1.ltoreq.i.ltoreq.t) as row [1], the I2-0 field value as row [3], the I5-3 field value as row [4], the I8-6 field value as row [5], the Bp field value as row [6], the Ap field value as row [7];

Taking the modification of the I2 expression in the list1 as an example, for all records in the ControlSignal table, if row [3] [0] is 1, then the row [1] field value is added in the listI2 list; obtaining a merged listI list according to algorithm 6; generating a beat expression according to algorithm 7, finding the line in which I2 is located in list1 and adding this beat expression to the I2 expression.

The method of modifying the other expressions of A3, A2, A1, A0, B3, B2, B1, B0, etc. in the list1 is the same as the method of modifying the expression of I2 in the list 1.

(6) The list1 list object is written to a new file m256c.abl, which is then closed.

Alternatively, algorithm 6 is as follows:

let n beat signals in the list, each beat signal being an 8 bit signal.

(1) Comparing the least significant bits and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the least significant bits are different and the other bits are the same, changing the least significant bits of the list [ i ] and list [ j ] into 'X', and only preserving one beat signal in the list;

(2) Comparing the penultimate bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the penultimate bit is different and the other bits are the same, changing the penultimate bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(3) Comparing the third last bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the third last bit is different and the other bits are the same, changing the third last bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(4) Comparing the fourth last bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the fourth last bit is different and the other bits are the same, changing the fourth last bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(5) Comparing the fourth bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the fourth bit is different and the other bits are the same, changing the fourth bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(6) Comparing the third bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the third bit is different and the other bits are the same, changing the third bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(7) Comparing the second bit and other bits of any two beat signals list [ i ] and list [ j ] in the list, if the second bit is different and the other bits are the same, changing the second bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list;

(8) Comparing the first bit and the other bits of any two beat signals list [ i ] and list [ j ] in the list, if the first bit is different and the other bits are the same, changing the first bit of the list [ i ] and list [ j ] into 'X', and keeping only one beat signal in the list.

Alternatively, algorithm 7 is as follows:

setting m items in the combined list, wherein for each item list [ i ] in the list, i is more than or equal to 0 and less than or equal to len (list) -1;

(1) If the list [ i ] [0] is not 'X', the (T7= list [ i ] [0 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(2) If the list [ i ] [1] is not 'X', the (T6= list [ i ] [1 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(3) If the list [ i ] [2] is not 'X', the (T5= list [ i ] [2 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(4) If the list [ i ] [3] is not 'X', the (T4= list [ i ] [3 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(5) If the list [ i ] [4] is not 'X', the (T3= list [ i ] [4 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(6) If the list [ i ] [5] is not 'X', the (T2= list [ i ] [5 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(7) If the list [ i ] [6] is not 'X', the (T1= list [ i ] [6 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression;

(8) If list [ i ] [7] is not 'X', then (T0= list [ i ] [7 ]) item is needed to be added in the beat expression, otherwise, the item is not needed to be added in the expression

In the method, in the implementation process of automatically generating the source program file module of the combined logic controller of the TEC-XP16 teaching machine according to the beat signals, the control signals and the beat conversion relation table, in order to simplify the beat conversion relation logic expression and the control signal logic expression, an algorithm is designed for merging the beat signals in all the expressions and generating the beat conversion relation expression and the control signal expression according to the merged beat signals. The method that simulation software passes and then is downloaded into the MACH chip of the TEC-XP16 teaching machine designs a new instruction for the TEC-XP16, and has the advantages of easy operation, convenient debugging, high instruction design realization efficiency and the like.

Drawings

FIG. 1 is a flow chart of a method for designing instructions of a TEC-XP16 combinational logic controller according to an embodiment of the application;

FIG. 2 is a diagram illustrating a MVRD R, 7F8 instruction according to one embodiment of the present application;

fig. 3 is a block diagram of beats corresponding to MVRD R, 7F8 instructions provided in an embodiment of the present application;

fig. 4 is a schematic diagram of a beat conversion relationship generated by MVRD R, 7F80 instruction according to an embodiment of the present application;

FIG. 5 is a schematic diagram of control signals generated by MVRD R, 7F80 commands according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a next beat of JRb _loop instruction according to one embodiment of the present application;

FIG. 7 is a schematic diagram of a next beat of Rbyte _loop instruction according to one embodiment of the present application;

FIG. 8 is a schematic diagram of a next beat of a JR adj_loop instruction according to an embodiment of the present application;

Fig. 9 is a schematic diagram of a next beat of JRZ FPMul _exit instruction according to an embodiment of the present application;

Fig. 10 is a schematic diagram of a next beat of JRZ result _zero instruction according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a next beat of JRZ FPMul _byte instruction according to one embodiment of the present application;

Fig. 12 is a schematic diagram of a next beat of JRZ FPMul _end instruction according to an embodiment of the present application;

Fig. 13 is a schematic diagram of a next beat of a next JRZ FPMul _end instruction according to an embodiment of the present application;

Fig. 14 is a schematic diagram of a next beat of JRZ byte _end instruction according to an embodiment of the present application;

FIG. 15 is a schematic diagram of a next beat of JRZ FLM _n_rnd instruction according to one embodiment of the present application;

FIG. 16 is a schematic diagram of a condition for generating T3 according to an embodiment of the present application;

FIG. 17 is a diagram of a method for generating-! A conditional schematic of I7;

FIG. 18 is a schematic diagram of a simulation software main interface of a combinational logic controller according to an embodiment of the present application;

FIG. 19 is a flowchart illustrating a WorkThread thread execution process according to one embodiment of the present application;

FIG. 20 is a schematic diagram of a WorkThread thread simulation serial port output flow provided by an embodiment of the present application;

FIG. 21 is a schematic diagram of a WorkThread thread simulation serial port input flow provided by an embodiment of the present application;

FIG. 22 is a schematic diagram illustrating implementation of keyboard input in an interrupt mode according to an embodiment of the present application;

FIG. 23 is a schematic diagram of a final simulation result of a floating-point multiply instruction FLM according to an embodiment of the present application;

FIG. 24 is a schematic diagram of a selection device type provided by an embodiment of the present application;

FIG. 25 is a schematic diagram of an add controller source file according to an embodiment of the present application;

FIG. 26 is a schematic diagram of a programming success provided by an embodiment of the present application;

FIG. 27 is a diagram of one embodiment of a teaching machine program including FLM instructions;

FIG. 28 is a second embodiment of a teaching machine program including FLM instructions;

FIG. 29 is a representation of intent in database ComLogicControls.db provided by an embodiment of the present application;

fig. 30 is a diagram of a representation of the intent in the database comlogicfpmul.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

The following first illustrates a flow diagram corresponding to a method for designing instructions of a TEC-XP16 combinational logic controller according to an embodiment of the present application in conjunction with fig. 1.

The method provided by the application comprises the following steps:

and step S101, designing and realizing a teaching machine assembly language source program corresponding to the instruction to be designed by using the teaching machine assembly instruction.

Step S102, generating beat signals and control signals according to the teaching machine assembly language source program and beat conversion relations.

And step S103, importing beat signals, control signals and beat conversion relations into simulation software of a designed TEC-XP16 teaching machine combinational logic controller to simulate.

And step S104, after the simulation passes, generating a source program file of the combination logic controller corresponding to the TEC-XP 16 teaching machine according to the beat signal, the control signal and the beat conversion relation.

Step S105, compiling the source program file of the combinational logic controller, and downloading the JED file generated after compiling into the MACH chip of the teaching machine

And step S106, writing a source program of the teaching machine assembly language containing the designed instruction for verification.

The assembler instructions of the TEC-XP16 teaching machine used in step S101 are the same for different instructions to be designed, as shown in table 2, but the source program of the teaching machine assembler language designed with the assembler instructions of the teaching machine is different according to the instruction functions to be designed.

Specifically, in step S101, description will be given taking as an example the design implementation of a floating-point number multiplication instruction in the format of 32-bit IEEE 754.

The format and function of the 32-bit floating point multiply instruction is shown in Table 1:

table 1 FLM instruction format and function

The teaching machine assembly language source program for realizing the floating point multiplication instruction FLM is designed by the teaching machine assembly instruction, and the designed teaching machine assembly language program is composed of 100 teaching machine assembly instructions in total. Since this section is not the subject of the present application, it will not be described in detail here.

As shown in table 2, the assembler instructions for the TEC-XP 16 teaching machine.

Table 2 TEC-XP 16 instruction for assembler

For different instructions to be designed, step S102 is identical, but the specifically generated beat signal and control signal and beat conversion relationship are different.

In step S102, the present application designs an assembly language program table AsblProgram, as shown in table 3, for storing an assembly language source program of the teaching machine for implementing the instruction function to be designed. Taking the design implementation of the floating-point number multiplication instruction in the 32-bit IEEE 754 format as an example, what is stored in the AsblProgram table is a teaching machine assembly language source program for implementing the 32-bit floating-point number multiplication instruction, and the NewIname field value of the floating-point number multiplication instruction in the 32-bit IEEE 754 format is FLM.

Table 3 AsblProgram teaching machine assembly language source program table

In order to save the first beat at execution, an instruction head beat table INSTFIRSTTIME is designed, as shown in table 4, FIRSTTIME is the first beat at execution of the designed instruction. Taking the design implementation of a 32-bit IEEE 754 format floating-point number multiply instruction as an example, its first beat is 00010000 beats and Iname field value is FLM.

Table 4 InstFirstTime instruction head beat table

In order to store and represent the conversion relationship between beats at the time of instruction execution, timeConversion beat conversion tables are designed as shown in table 5.

TABLE 5 timeConversion beat conversion table

Since the number of beats required at the time of execution of each assembler instruction is different, an assembler instruction beat table ISEA is designed, and as shown in table 6, start and end are used to represent the first beat and the last beat at the time of execution of each assembler instruction, respectively.

Table 6 ISEA Assemble instruction beat Table

The control signal sent by the TEC-XP16 teaching machine combinational logic controller under each beat comprises the following components:

control signals I8-6, I5-3, I2-0, A3-A0, B3-B0, SST 2-SST 0, SSH-SCI of the control arithmetic unit;

control signals MIO, REQ, WE for controlling the memory or I/O interface;

control signals DC12, DC11, DC10 controlling the internal bus;

Control signals DC22, DC21, DC20 received by the control dedicated register;

In order to represent the state of the 32-bit control signal sent by each beat of the combinational logic controller during instruction execution, a ControlSignal control signal table is designed, as shown in table 7, for storing the control signal that needs to be sent by each beat when the combinational logic controller executes the instruction. Taking the design implementation of a floating-point number multiplication instruction in the format of 32-bit IEEE 754 as an example, controlSignal tables store control signals required by each beat when the floating-point number multiplication instruction FLM is executed, and the Iname field value of the control signals is FLM.

TABLE 7 ControlSignal control signal Table

AsblProgram, instFirstTime, timeConversion, ISEA and ControlSignal tables are contained in the designed new instruction database comlogicINST.

The following describes a method of converting the teaching machine assembler instruction into a beat signal and a control signal.

Only one beat is needed when instructions such as MVRR, OR, AND, ADD, SUB, XOR, TEST, ADC, CMP, SHR, RCR, SHL, INC, DEC, JR, JRZ, JRNZ, JRC, JRNC, JRS, JRNS, CLC, RET are executed, two beats are needed when PSHF and POPF instructions are executed, and a plurality of beats are needed when MVRD instructions are executed.

Wherein the control signals for JR, JRZ, JRNZ, JRC, JRNC, JRS, JRNS, RET instructions, PSHF, POPF, CLC instructions are fixed when executed.

The MVRR, OR, AND, ADD, SUB, XOR, TEST, ADC, CMP instruction has fixed control signals except that the B port address and the A port address are required to be set according to the register numbers in the instruction.

The SHR, RCR, SHL, INC, DEC instruction is fixed except that the B port address needs to be set according to the register number in the instruction.

The number of beats and control signals required for the MVRD DATA instruction are different depending on the DATA value.

In the designed teaching machine assembly language source program for realizing the floating point operation instruction FLM, MVRD Ri and the DATA instruction, the DATA values have hexadecimal values of 7F80, 1FC0, 007F, 8000, 0010, 0001, 0008, 0040, 0080 and 0100. Based on the continuous nature of 1 in the DATA value, algorithm 1 was designed, with the design goal of algorithm 1 being to generate control signals for executing MVRD instructions with the least possible beats.

Algorithm 1 is used MVRD Ri, the DATA instruction generates a control signal for multiple beats.

The specific steps of algorithm 1 are as follows:

(1) Converting DATA into a 16-bit binary number D16;

(2) Calculating the number of 1 in D16, and recording as one (D16);

(3) Executing (4) if one (D16) >1, otherwise executing (12);

(7) If SLR (D16). Ltoreq.SRL (D16), executing (8), otherwise executing (10);

In the source program of the assembly language of the teaching machine for realizing the floating point operation instruction FLM, the 7 th assembly instruction is MVRD R, 7F80, and as shown in FIG. 2, an instruction diagram of MVRD R, 7F8 is provided in the embodiment of the application. For MVRD R, 7F80 instructions, according to algorithm 1, after the first beat is executed, (Ri) =1111111111111, d16=011111110000000, one (D16) =8, slr (D16) =9, srl (D16) =15, so that a control signal of 8 beats is generated first, each beat is shifted left by one bit Ri; then a control signal of 1 beat is generated, each beat being shifted right by one bit Ri.

According to algorithm 1, 10 beats are total, namely 00010110 ～ 00011111, generated by the command MVRD R, 7F80, and as shown in fig. 3, a schematic diagram of beats corresponding to MVRD R, 7F8 is provided in the embodiment of the present application.

Fig. 4 is a schematic diagram of a beat conversion relationship generated by MVRD R, 7F80 instructions according to an embodiment of the present application.

Fig. 5 is a schematic diagram of control signals generated by MVRD R, 7F80 instructions according to an embodiment of the present application.

The algorithm 2 provided by the implementation of the application generates the next beat for the JR instruction.

Taking the design implementation of a floating point number multiply instruction in 32-bit IEEE 754 format as an example, specifically, algorithm 2 includes:

(1) Searching NewIname records which are FLM and Iname records which are JR from a table of an assembly language source program AsblProgram of the teaching machine, and assuming that N records exist in a query result, enabling i to be 1;

(2) Setting the Number field value and DstAdr field value of record i in the query result to be Numberi and DstAdri respectively, if DstAdri is FINISH, updating NextTime of record whose Number field is Numberi in timeConversion table to 00000000, otherwise, turning (3)

(6) i=i+1, repeating steps (2) to (5) until i > N ends.

Algorithm 2 differs for different instructions to be designed in that in step (1) the instruction name NewIname value of the design looked up from the AsblProgram table differs according to the instruction name to be designed.

Three JR instructions in the assembly language source program of the teaching machine for realizing the 32-bit floating point multiplication instruction FLM are JR b_loop, JR byte_loop and JR adj_loop respectively. The next beat NextTime generated by algorithm 2 is shown in table 8. The timeConversion tables produced are shown in figures 6 to 8.

Table 8 shows the next beat generated for the JR instruction

Fig. 6 is a schematic diagram of a next beat of a JRb _loop instruction according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a next beat of a JRbyte _loop instruction according to an embodiment of the present application.

Fig. 8 is a schematic diagram of a next beat of a JR adj_loop instruction according to an embodiment of the present application.

Algorithm 3 provided by the implementation of the present application may generate the next beat for JRZADR instructions.

Taking the design implementation of a floating point number multiplication instruction in 32-bit IEEE 754 format as an example, specifically, the method comprises the following steps:

(1) Searching records NewIname which are FLM and Iname which are JRZ from a table of an assembly language source program AsblProgram of the teaching machine, and assuming that M records exist in a query result, enabling i=1;

(2) Setting the Number field value and DstAdr field value of record i in the query result to be Numberi and DstAdri respectively, if DstAdri is FINISH, updating NextTime of record whose Number field is Numberi and Condition field value is "Z= =1" in timeConversion table to be 00000000, otherwise, turning to (3)

(6) i=i+1, repeating steps (2) to (5) until i > M ends.

The algorithm 3 differs for different instructions to be designed in that in step (1), the instruction name NewIname value of the design is looked up from the AsblProgram table according to the instruction name to be designed.

Seven instructions are included in JRZ instructions in the source program of the teaching machine assembly language for realizing the 32-bit floating point multiplication instruction. The next beat NextTime generated by algorithm 3 is shown in table 9. The timeConversion tables produced are shown in figures 9 to 15.

Table 9 shows the next beat generated for JRZ instructions

Fig. 9 is a schematic diagram of a next beat of JRZ FPMul _exit instruction according to an embodiment of the present application.

Fig. 10 is a schematic diagram of a next beat of JRZ result _zero instruction according to an embodiment of the present application.

As shown in fig. 11, a schematic diagram of a next beat of JRZ FPMul _byte instruction is provided in an embodiment of the present application.

As shown in fig. 12, a schematic diagram of a next beat of JRZ FPMul _end instruction is provided in an embodiment of the present application.

As shown in fig. 13, a schematic diagram of a next cycle of a next JRZ FPMul _end instruction is provided in an embodiment of the present application.

As shown in fig. 14, a schematic diagram of a next beat of JRZ byte _end instruction is provided in an embodiment of the present application.

As shown in fig. 15, a schematic diagram of a next beat of JRZ FLM _n_rnd instruction is provided in an embodiment of the present application.

The algorithm for generating the next beat for the JRNZ, JRC, JRNC, JRS, JRNS etc. conditional branch instruction is similar to algorithm 3. The next beat is generated for JRNZ instructions by changing the Condition field value to "z= =0". Similarly, the Condition field values need only be changed to "c= 1", "c= 0", "s= 1" and "s= 0" for the JRC, JRNC, JRS, JRNS instruction to generate the next beat, respectively.

From the above analysis, embodiments of the present application provide algorithm 4, algorithm 4 being able to generate all beats and control signals of the FLM command.

Taking the design implementation of a floating point number multiply instruction in 32-bit IEEE 754 format as an example, specifically, algorithm 4 is as follows:

(1) Looking up Iname a FIRSTTIME field value of the record of the FLM from a pre-established INSTFIRSTTIME table and assigning to the bean variable;

(2) Searching NewIname from a pre-established AsblProgram table for the maximum Number field value of all records of the FLM, which is maxN, and enabling i=1;

(3) Searching a record of which NewIname is FLM and the Number field is equal to i in AsblProgram table, and recording the record AsbInsti;

All records will generate one record in the ISEA table;

(5) I=i+1, repeating step (3) and step (4) until i > maxN ends.

Algorithm 4 differs for different instructions to be designed in that, depending on the instruction name to be designed, the value of instruction name Iname to be designed is looked up from the table INSTFIRSTTIME in step (1), and the value of instruction name NewIname to be designed is looked up from the table AsblProgram in steps (2) and (3).

Taking the design implementation of the floating point number multiplication instruction in the 32-bit IEEE 754 format as an example, according to algorithm 4, the Python program is designed, and the beat conversion table timeConversion, the control signal table ControlSignal and the assembler instruction beat table ISEA can be automatically generated by the assembler language source program in the AsblProgram table in the database com logic inst.db and INSTFIRSTTIME beat tables.

The beat signal and the control signal and the beat conversion relation are designed for the new instruction, the new instruction can be designed manually, and the beat signal and the control signal which are designed for the new instruction manually are compared with all beats and control signals of the FLM instruction which are automatically generated by applying the Python program, so that the problems in the design process can be found timely. Step S103 is identical for different instructions to be designed.

Step S103 specifically comprises the steps of designing combinational logic controller simulation software as a debugging tool;

and importing the beat signal, the control signal and the beat conversion relation into the combinational logic controller simulation software for simulation.

After the conversion relation between the beat signals of the floating-point multiplication instruction and the control signal under each beat is designed, in order to debug the beat signals and the control signals designed for the new instruction, combinational logic controller simulation software is designed as a debugging tool, and the simulation software can import the beat signals and the control signals designed for the new instruction and the beat conversion relation, can operate in a single-beat mode and can also operate continuously. And can observe the values of the general registers, flag bits, IR, AR, 32-bit control signals after each beat run. The simulation software of the combinational logic controller can timely and intuitively discover which beat signal or which control signal has errors, correct the errors and greatly improve the design efficiency.

An assembly language file containing a floating point multiplication instruction FLM is imported into the simulation software of the combinational logic controller, cross-assembly is performed, a database comingINST.db is opened to import Times and ControlSignal, then a new instruction database comingFPMUL.db is opened, a new instruction beat signal and a new instruction control signal are imported, RESET is pressed, and then the assembly language program can be operated in a single step and continuously. The value of the 32-bit control signal per beat and the values of the general registers, flag bits, IR, AR after each beat run can be observed.

The database comlogiccontrols.db contains basicbeat tables and basicControlSignal tables.

Basicbeat tables (shown in table 10) store the beat transition tables of the teaching machine instructions in table 2. Wherein, the beat signal has 8 bits, the upper four bits are 0000, and the lower four bits are T3, T2, T1 and T0 in sequence from the upper position to the lower position; the condition for generating the beat signal bits consists of an instruction operation code required for generating each beat signal bit, the current beat and the like. The conditions for generating the beat signal bits have various formats as shown in table 11. For example, there are three formats of conditions for generating T3, and as shown in fig. 16, a condition diagram of conditions for generating T3 is provided in an embodiment of the present application.

Table 10 basicbeat beat conversion table

Table 11 conditional format for generating beat signal bits

BasicControlSignal (as shown in table 12) stores a table of control signals for teaching machine instructions in table 2. The condition for generating the control signal consists of an instruction operation code, a current beat, a flag bit and the like which are required by generating the control signal. The conditions for generating the control signal are in various formats as shown in table 13. For example, generate-! The conditions of I7 have three formats, as shown in FIG. 17, which is one of the generation of-! Schematic of the conditions of I7.

Table 12 basicControlSignal control signals

Table 13 conditional formats for generating control signals

The simulation software of the combination logic controller is developed by adopting the latest Python language, and a software interface is designed by using PyQt5 QT DESIGNER, as shown in FIG. 18, which is a schematic diagram of a main interface of the simulation software of the combination logic controller provided by the embodiment of the application. The simulation software of the combination logic controller adopts a multithreading technology, and a plurality of threads are used for respectively simulating the running process of the combination logic controller and the serial port input and output operation, and supporting the design comprehensive experiments such as multistage nested interrupt experiments and the like. And the students can do experiments anytime and anywhere by using the combination logic controller simulation software, and are not limited by experimental sites and experimental equipment.

The design adopts multiple threads, wherein WorkThread threads simulate the execution process of the combinational logic controller, as shown in fig. 19, and a WorkThread thread execution flow chart is provided for the embodiment of the application. The WorkThread thread simulates a serial port output process, as shown in fig. 20, and is a schematic diagram of a WorkThread serial port output process. Fig. 21 is a schematic diagram of a WorkThread thread simulation serial port input process according to an embodiment of the present application. Wherein the thread sleep time may be set.

The design process adopts a modularized design, and modules ProduceControlSignal, produceControlSignalI, produceBport, produceAport and the like are required to be called for generating the control signals in fig. 19.

ProduceControlSignal (inst, bean, LISTSIGNAL, qf) for generating each bit control signal (except I7 control signal, B-port address, a-port address), wherein LISTSIGNAL is a list type, LISTSIGNAL may be listM, listR, listW, listI2, listI1, listI0, listI5, listI4, listI, etc., qf being 1 indicates that the control signal generated is 0 when the current instruction inst, the current beat bean satisfies any of the conditions of LISTSIGNAL, otherwise being 1.

ListM, listR, listW, listI2, listI1, listI0, listI5, listI4, listI3, etc. are list objects, including all conditions for generating corresponding control signals, which can be generated from the ControlSignal table in comlogicfpmul.

ProduceControlSignalI7 (inst, bean, LISTSIGNAL, qf, flags) generates an I7 control signal block, wherein LISTSIGNAL can only be listI7, and the generation of the I7 control signal is related to the status flag bit in addition to the current instruction, the current beat.

ProduceBport module generates the B port address. ProduceAport module generates the a-port address.

Executeinst (controlSignals, bean, R, AR, IR, flag) execution module in fig. 19 is for executing one beat of an instruction, where controlSignals is a control signal generated by the generate control signal module, bean is a current beat signal, R is a general register set, AR is an address register, IR is an instruction register, and flag is a flag register.

ProduceTime (inst, bean, listT, listT6, listT, listT, listT3, listT2, listT1, listT0, INTTERUPT, flags) are used to generate a beat signal module to generate the next 8-bit beat signal.

Where inst is a current binary instruction, bet is a current beat, listT is a command operation code, a beat signal, and a condition that make the highest bit T7 of the beat signal 1, listT is a command operation code, a beat signal, and a condition that make the next highest bit T6 of the beat signal 1, listT5 is a command operation code, a beat signal, and a condition that make the lowest bit T5 of the beat signal 1, listT4 is a command operation code, a beat signal, and a condition that make the bit T4 of the beat signal 1, listT3 is a command operation code, a beat signal, and a condition that make the bit T3 of the beat signal 1, listT2 is a command operation code, a beat signal, and a condition that make the bit T2 of the beat signal 1, listT is a command operation code, a beat signal, and a condition that make the lowest bit T0 of the beat signal 1, listT is a command operation code, a beat signal, and a condition that make the lowest bit T0 of the beat signal 1, INTTERUPT is an interrupt request signal, and a low valid bit flags is a state vs.

If the current beat is the last beat of the current instruction inst execution cycle and INTTERUPT =0, then the next beat is '00001010' into the interrupt cycle.

The execution of the process interrupt module in fig. 19 is as follows:

if the current beat is '00000010', interrupt processing is performed:

If any one of the interrupt 1, interrupt 2, interrupt 3 buttons (multi-level nested interrupt experiment) is pressed, then

Int=0 issues an interrupt request signal if the interrupt request is allowed, the priority is higher than the current interrupt and the interrupt request is allowed;

otherwise, int=1 (no interrupt request is issued).

If the interrupt request is allowed and keyboardInterrupt is 1, then

Int=0 issues an interrupt request signal;

if the interrupt request is allowed and screenInterrupt is 1, then

LNT = 0 issues an interrupt request signal;

if the lowest bit of the status register is 1, then

The display displays the R0 register content;

Otherwise, there is no interrupt request.

The following describes the process of realizing keyboard input in an interrupt mode:

The main program is firstly interrupted by EI instruction, and then a section of loop program is executed. The interrupt service routine includes three instructions, the IN 80 instruction fetches the character '6' from the keyboard buffer, sends the ASCII code of the character '6' to the register R0, the EI instruction completes the interrupt, and the IRET instruction is used for interrupt return. The main program and the interrupt service routine assemble the instruction execution process as shown in the lower left of fig. 22.

First, the combinational logic emulation software is started, the main program and interrupt service routine are imported, the database comlogiccontrols. Db is opened to import Time and ControlSignal, and the combinational logic controller is run, if the number 6 on the keyboard is pressed down in the keyboard area in fig. 22, the WorkThread thread will be started, first, the thread dormancy is delayed for 30 seconds, then the status register is at position 2 reciprocal, 1, finally keyboardInterrupt =1, and the character '6' is added in the keyboard buffer keyboardInput.

In the workthread thread processing interrupt module, if the current beat is '00000010' and the interrupt request is allowed and keyboardInterrupt is 1 during execution, int=0 issues an interrupt request signal.

In the workthread thread ProduceTime module, if the current beat is the last beat of the current instruction inst execution cycle, and INTTERUPT =0 (i.e., int=0), then the next beat is '00001010' into the interrupt cycle. In the interrupt period, the operations of closing the interrupt, saving the program breakpoint, sending the interrupt vector to the PC and the like are completed by executing '00001010', '00001110', '00001100', '00001111', '00001101', '00001011'6 beats.

After the interrupt cycle is completed, the interrupt service routine is executed, the IN 80 instruction fetches the character '6' from the keyboard buffer, sends the ASCII code of the character '6' to the register R0, the EI instruction completes the interrupt, and the IRET instruction is used for interrupt return.

And returning to the main program to continue to execute after the interrupt service routine is finished.

Fig. 22 is a schematic diagram illustrating implementation of keyboard input in an interrupt manner according to an embodiment of the present application.

An assembly language file containing a floating-point multiplication instruction FLM is imported into the simulation software of the combinational logic controller, cross-assembly is conducted, a basicbeat table and a basicControlSignal table in a database ComLogicControl.db are imported, then a new instruction database comLogicFPMUL.db is opened, a new instruction FLM beat signal and a new instruction control signal are imported, RESET is pressed, and then the assembly language program containing the floating-point multiplication instruction FLM can be run in a single step and run continuously. The value of the 32-bit control signal of each beat of each assembly instruction and the values of the general register, the flag bit, the IR and the AR after each beat is operated can be observed in the operation process.

Fig. 23 is a schematic diagram of a final simulation result of a floating-point multiply instruction FLM according to an embodiment of the present application. Simulation results show that the control signal and beat signal of the floating-point multiplication instruction FLM designed by us are correct, and the final execution result is also correct.

Step S104 is identical for different instructions to be designed, but the generated combinational logic controller source program is different.

Step S104 specifically includes automatically generating a source program file of the combined logic controller of the TEC-XP 16 teaching machine capable of executing the designed instruction according to the beat signal, the control signal and the beat conversion relation after the simulation is passed.

After the beat signal and the control signal designed for the new instruction are simulated in the combinational logic controller simulation software, in order to execute the new instruction in the TEC-XP16 teaching machine, the source program file of the combinational logic controller of the TEC-XP16 teaching machine is also required to be modified according to the beat signal and the control signal designed for the new instruction, and the work of the part is very low in efficiency and easy to make mistakes. For this purpose, an algorithm 5 is designed to automatically modify the source program file of the TEC-XP16 teaching machine combinational logic controller according to the beat signal and control signal designed for the new instruction. Taking the design implementation of a floating-point multiply instruction in 32-bit IEEE 754 format as an example, in particular,

Algorithm 5 automatically generates an algorithm for a combinational logic controller source program that is capable of executing the designed instructions.

(2) Connecting a comingins db database;

(3) The record Iname is FLM is read from INSTFIRSTTIME table, and the Iname field value and the Opcode field value form a string OPstring: "flm= (ir= = [1,1,1,0,1,1,0,0 ]); "

(4) The CurrentTime, nextTime, condition field values of all records Iname are FLM are read from timeConversion table, assuming n records, nextTime field value of record i (1. Ltoreq.i.ltoreq.n) is row [1], condition field value is row [2], and CurrentTime field value is row [0].

Each beat signal is 8 bits, denoted T7, T6, T5, T4, T3, T2, T1, T0. The list01 list stores current beat signals with T7 in the next beat being 1 in the beat conversion relation, the list01NZ list stores current beat signals with T7 in the next beat being 0 in the beat conversion relation and T7 in the next beat being 1 in the beat conversion relation, the list01Z list stores current beat signals with T7 in the next beat being 1 in the beat conversion relation, the list01NC list stores current beat signals with T7 in the next beat being 0 in the beat conversion relation and T7 in the next beat being 1 in the beat conversion relation, the list01C list stores current beat signals with T7 in the next beat being 1 in the beat conversion relation, the list01NS list stores current beat signals with T7 in the next beat being 1 in the beat conversion relation and T7 in the next beat being 1 in the beat conversion relation, and the list stores current beat signals with T7 in the next beat being 1 in the beat conversion relation and T7 in the list.

in order to simplify the beat conversion relation logic expression and the control signal logic expression, an algorithm 6 is designed for merging beat signals in the list and an algorithm 7 generates a beat expression from the merged beat signals.

The method of adding beat signals in list1 list T60, T50, T40, T30, T20, T10, T00 expressions is the same as the method of adding beat signals in T70 expression.

(5) All records Iname are FLM are read from ControlSignal table, assuming t records are present, let the CurrentTime field value of record I (1.ltoreq.i.ltoreq.t) be row [1], the I2-0 field value be row [3], the I5-3 field value be row [4], the I8-6 field value be row [5], the Bp field value be row [6], the Ap field value be row [7].

Algorithm 5 differs from the instruction to be designed in that the instruction name Iname value of the design is looked up from the INSTFIRSTTIME table in step (3), and the Iname value read from the timeConversion table in step (4) and the Iname value read from the ControlSignal table in step (5).

Algorithm 6 merges the beat signals in the list. Let n beat signals in the list, each beat signal being an 8 bit signal.

The algorithm 7 generates a beat expression from the combined beat signal. Let m items in the combined list, for each item list [ i ] in the list, 0.ltoreq.i.ltoreq.len (list) -1.

(8) If list [ i ] [7] is not 'X', then (T0= list [ i ] [7 ]) item is added to the beat expression, otherwise, the item is not added to the expression.

Taking the design implementation of a 32-bit IEEE 754 format floating-point number multiplication instruction as an example, the number of terms added in the T70, T60, T50, T40, T30, T20, T10, T00 expressions are compared before and after algorithm 6 and algorithm 7, as shown in Table 14.

Table 14 uses the comparison of the term numbers in the beat expressions before and after the algorithms 6 and 7

Taking the design implementation of a 32-bit IEEE 754 format floating-point number multiplication instruction as an example, the number of terms added in the I2, I1, I0, I8, I7, I6, I5, I4, I3 expressions are compared before and after algorithm 6 and algorithm 7, as shown in Table 15.

Table 15 uses the comparison of the term numbers in the I8-I0 expressions before and after the algorithm 6 and 7

Taking the design implementation of the 32-bit IEEE 754 format floating-point number multiplication instruction as an example, the number of terms added in the expressions B3-B0 and A3-A0 are compared before and after adopting the algorithm 6 and the algorithm 7, as shown in the table 16.

Table 16 uses the comparison of the numbers of terms in the expressions B3-B0, A3-A0 before and after the algorithm 6, 7

Step S105 is identical for different instructions to be designed.

In step S105, the generated source program file m256c.abl of the combinational logic controller is compiled and downloaded to the teaching machine MACH chip.

The specific process is as follows:

(1) The ISPLEVER CLASSIC Project Navigator software in LATTICE ISPLEVER CLASSIC 2.0.0 was started and an item was created under the name lc4256.

(2) The device type is selected.

Fig. 24 is a schematic diagram of a selection device type according to an embodiment of the present application.

(3) By clicking the "Add Source" button, the Add controller Source file m256c.abl is added, as shown in FIG. 25, which is a schematic diagram of adding a controller Source file according to an embodiment of the present application. Then, click the "done" button.

(4) Clicking on the m256c.abl file in the left source file window, double clicking Compile Logic the task item, i.e., compiling the source file m256 c.abl.

(5) Clicking on the device icon in the left side source File window, double clicking on the JEDEC File task item in the right side window generates the lc4256. Jet File. Marked with a green "/" after completion.

(6) ISPVM SYSTEM software in LATTICE ISPLEVER CLASSIC 2.0.0 is launched and the main interface is popped up.

(7) Five black control switches at the left lower part of the teaching machine are turned to 10100 (1 means to dial upwards, and 0 means to dial downwards).

(8) The power supply of the teaching computer is turned on by connecting the PC with the MACH chip on the teaching computer through the Lattice USB download cable HW-USB-2A.

(9) The operations, cable and I/O Port Setup … command is executed, setting Cable as the USB interface, since we use USB ispDOWNLOAD Cables.

(10) The on-line programming device is found through the SCAN button of ISPVM SYSTEM software main interface.

(11) Right clicking on the found programming Device LC4256V, selecting "EDIT DEVICE", selecting Device LC4256V (B) in the "Device Information" window, selecting the compiled JED file (LC 4256.jed) by the Browse button, clicking the OK button.

(12) Returning to ISPVM SYSTEM software main interface again, clicking GO command to download programming. FIG. 26 is a schematic diagram showing the programming success according to the embodiment of the present application.

(13) And closing the power supply of the teaching computer, and pulling out the downloading programming cable.

Step S106 is the same for different instructions to be designed, but the written tutorial assembly source program is different.

In step S106, the teaching machine assembly language source program containing the designed instruction is written to verify whether the function of the designed instruction is correct.

The specific process is as follows:

(1) The five black control switches at the left lower part of the teaching machine are turned to 00110 (1 is turned upwards, 0 is turned downwards), winPcec software is started, then the power supply of the teaching machine is turned on, a RESET key is pressed firstly, then a START key is pressed, and a monitoring program of the teaching machine is started.

(2) A teaching machine program for realizing 2 32-bit floating point number multiplications is written in WinPcec software, an expansion instruction is specified in the teaching machine to be written into a memory of the teaching machine by an E command, the binary code of an FLM instruction is EC00 (hexadecimal form), and EC is the operation code of the FLM instruction.

Fig. 27 shows one of teaching machine programs including FLM instructions according to an embodiment of the present application. Fig. 28 shows a second teaching machine program including FLM instructions according to an embodiment of the present application.

As shown in fig. 27, the multiplicand and multiplier are 01000000000000000000000000000000, i.e., 1.0×2 ¹, and the product is 01000000100000000000000000000000, i.e., 1.0×2 ², and the program running result verifies that the function of the 32-bit floating point multiply instruction designed and implemented is correct.

As shown in fig. 28, the multiplicand and multiplier are 01000000000100000000000000000000, i.e., 1.001×2× 2 ¹, and the product is 01000000101000100000000000000000, i.e., 1.010001×2× 2 ², and the program running result verifies that the function of the 32-bit floating-point multiply instruction designed and implemented is correct.

It will be apparent to those skilled in the art that the techniques of embodiments of the present application may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present application may be embodied in essence or what contributes to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present application.

The same or similar parts between the various embodiments in this specification are referred to each other. In particular, for the service building apparatus and the service loading apparatus embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description in the method embodiments for the matters.

The embodiments of the present application described above do not limit the scope of the present application.

Claims

1. A method for designing a TEC-XP16 combinational logic controller instruction, the method comprising:

After the simulation is passed, generating a source program file of a combination logic controller corresponding to the TEC-XP 16 teaching machine according to the beat signal, the control signal and the beat conversion relation;

compiling a source program file of the combinational logic controller, and downloading a JED file generated after compiling into a MACH chip of the teaching machine;

Generating beat signals, control signals and beat conversion relations according to the teaching machine assembly language source program comprises the following steps:

(3) Searching NewIname in the AsblProgram table as a record AsbInsti, wherein the record is the designed instruction name and the Number field is equal to i;

All records will generate one record in the ISEA table;

(5) I=i+1, repeating step (3) and step (4) until i > maxN ends.

2. The method of claim 1, wherein algorithm 1 is as follows:

(1) Converting DATA into a 16-bit binary number D16;

(2) Calculating the number of 1 in D16, and recording as one (D16);

(3) Executing (4) if one (D16) >1, otherwise executing (12);

(7) If SLR (D16). Ltoreq.SRL (D16), executing (8), otherwise executing (10);

3. The method of claim 1, wherein algorithm 2 is as follows:

(6) i=i+1, repeating steps (2) to (5) until i > N ends.

4. The method according to claim 1, characterized in that algorithm 3 is as follows:

(6) i=i+1, repeating steps (2) to (5) until i > M ends.

5. The method of claim 1, wherein importing the beat signal, the control signal, and the beat conversion relationship into the designed TEC-XP16 teaching machine combinational logic controller simulation software for simulation comprises:

The simulation software of the combined logic controller of the TEC-XP 16 teaching machine is used for importing beat signals and control signals designed for new instructions and beat conversion relations, and the combined logic controller operates in a single beat mode or continuously operates; observing the content of the general register, the flag bit, the IR, the AR and the 32-bit control signals after each beat runs;

6. The method of claim 1, wherein generating a source program for a TEC-XP 16 teaching machine combinational logic controller from the beat signal, the control signal, and the beat transition relation after the simulation passes comprises:

(2) The new instruction database comlogicINST.db of the connection design;

(4) Reading Iname from timeConversion table the CurrentTime, nextTime, condition field value of all records of the designed instruction name, assuming n records, setting NextTime field value of record i as row [1], condition field value as row [2], currentTime field value as row [0]; i is more than or equal to 1 and less than or equal to n;

Obtaining a list01 after combination according to the algorithm 6; generating a beat expression according to the algorithm 7, finding the line where T70 is located in the list1 and adding the beat expression in the T70 expression;

taking the modification of the I2 expression in the list1 as an example, for all records in the ControlSignal table, if row [3] [0] is 1, then the row [1] field value is added in the listI2 list; obtaining a merged listI list according to algorithm 6; generating a beat expression according to the algorithm 7, finding the row where I2 is located in the list1 and adding the beat expression in the I2 expression;

the method of modifying other expressions including A3, A2, A1, A0, B3, B2, B1, B0 in the list1 is the same as the method of modifying the I2 expression in the list 1;

(6) The list1 list object is written to a new file m256c.abl, and then the file is closed.

7. The method of claim 6, wherein algorithm 6 is as follows:

setting n beat signals in the list, wherein each beat signal is an 8-bit signal;

8. The method of claim 6, wherein algorithm 7 is as follows: