CN113535499A - Multi-type concurrent memory access flow verification method supporting multi-core shared access - Google Patents
Multi-type concurrent memory access flow verification method supporting multi-core shared access Download PDFInfo
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Abstract
The invention discloses a multi-type concurrent access flow verification method supporting multi-core shared access, which comprises the steps of obtaining system information of a storage system corresponding to an access component to be tested, and constructing a verification system corresponding to the access component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models; when a multi-source core request instruction is detected, determining each test excitation for sending the multi-source core request instruction; and respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result. The invention realizes the functions of request sending, analysis, response processing and the like of each virtual model in a short time, finally judges the correctness of processing, analysis and forwarding of the memory access component to be tested by comparing real and virtual responses, and is easier to find errors and error positioning by the verification method and the verification system, thereby ensuring the correctness of the memory access component to be tested and ensuring no errors of the stream chip.
Description
Technical Field
The application relates to the technical field of verification of the correctness of pre-silicon functions of a central processing unit chip, in particular to a multi-type concurrent access flow verification method supporting multi-core shared access.
Background
The MEMORY access management unit (MBOX) is one of the core units of the high-performance microprocessor, has a decisive influence on the performance and the efficiency of a computer MEMORY system, is positioned in the core, and mainly has the functions of resolving and forwarding various MEMORY access operations initiated by a plurality of request sources, submitting a plurality of MEMORY access objects for MEMORY access, receiving and managing read response data and returning the read response data to each request source, and managing the completion of the MEMORY access, wherein the access request sources mainly comprise requests of an execution unit (EBOX), MEMORY requests sent by other cores through a local transmission unit (TBOX), and MEMORY requests initiated by a maintenance access (IOBOX), and the MEMORY access objects mainly comprise a chip main MEMORY (MEMORY), a local MEMORY (LDM) of the core and a local MEMORY (remote GLDM) of other cores. The response mainly comprises a memory access response returned by the GLDM through the TBOX and a main memory response returned by a core management unit (SBOX), and the main structure block diagram of the response is shown in figure 1.
As the design is increasingly complex, the application of multi-core parallel processing and distributed shared storage technology and the characteristics of multiple request sources, multiple cores and multiple access types of MBOX as an important component of a computer storage system make the functional correctness verification face a plurality of challenges. How to efficiently verify the correctness of the image in an effective time and ensure the comprehensiveness and the sufficiency of the verification become important. Although the traditional software simulation verification method has the advantages of low cost and easy error, the requirements on the quantity and quality of test vectors are increased along with the increase of the design scale and complexity. And the traditional software simulation method has the defects of low running speed, low control force for simulating specific functions, difficult control of time sequence and the like, and the system can be verified only after being completely built by a software simulation verification mode, so that the high efficiency and the comprehensiveness of verification are ensured.
Disclosure of Invention
In order to solve the above problem, an embodiment of the present application provides a multi-type concurrent access flow verification method supporting multi-core shared access.
In a first aspect, an embodiment of the present application provides a method for verifying a multi-type concurrent access stream that supports multi-core shared access, where the method includes:
the method comprises the steps of obtaining system information of a storage system corresponding to an access storage component to be tested, and constructing a verification system corresponding to the access storage component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
Preferably, the system information of the storage system corresponding to the memory access component to be tested is acquired, and a verification system corresponding to the memory access component to be tested is constructed based on the system information, where the verification system includes a plurality of virtual models, including:
acquiring system information of a storage system corresponding to a memory access component to be tested, wherein the system information comprises a memory access request source component, a memory access object and a response object corresponding to the memory access component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can correspond to each other one by one and realize the functions of the access request source components, the access objects and the response objects;
and constructing a verification system corresponding to the memory access component to be tested based on each virtual model.
Preferably, after determining to send each test stimulus of the multi-source core request instruction when the multi-source core request instruction is detected, where the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
generating analog address bits to characterize a core of a call;
and performing cross-core memory access sharing based on the analog address bits.
Preferably, after determining to send each test stimulus of the multi-source core request instruction when the multi-source core request instruction is detected, where the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
and dividing different local memory addresses based on the test excitations, and generating control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test excitations.
Preferably, the determining each of the virtual models corresponding to each of the test stimuli and processing the multi-source core request instruction in parallel based on each of the virtual models to obtain each of the virtual response results includes:
respectively determining each virtual model corresponding to each test excitation;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to generate each storage visit based on the multi-source core request instruction simulation, and sending each storage visit to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
Preferably, the method further comprises:
when a test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training and generating a new virtual model based on the similar sample excitation set, and adding the new virtual model into the verification system.
In a second aspect, an embodiment of the present application provides a multi-type concurrent access flow verification apparatus for supporting multi-core shared access, where the apparatus includes:
the system comprises an acquisition module, a verification module and a storage module, wherein the acquisition module is used for acquiring system information of a storage system corresponding to an access component to be tested and establishing a verification system corresponding to the access component to be tested based on the system information, and the verification system comprises a plurality of virtual models;
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining each test stimulus for sending a multi-source core request instruction when the multi-source core request instruction is detected, and the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and the processing module is used for respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor executes the computer program to implement the steps of the method as provided in the first aspect or any one of the possible implementation manners of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method as provided in the first aspect or any one of the possible implementations of the first aspect.
The invention has the beneficial effects that: when a multi-source core request instruction is detected, functions of request sending, analysis, response processing and the like of each virtual model are realized in a short time by generating complete and efficient test excitation, and finally the correctness of processing, analysis and forwarding of the memory access component to be tested is judged by comparing real and virtual responses.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic block diagram illustrating an example of the main structure of an existing MBOX provided in an embodiment of the present application;
fig. 2 is a schematic flowchart of a multi-type concurrent access flow verification method supporting multi-core shared access according to an embodiment of the present application;
fig. 3 is a schematic block diagram illustrating a main structure of an authentication system according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a multi-type concurrent access flow verification apparatus supporting multi-core shared access according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the following description, the terms "first" and "second" are used for descriptive purposes only and are not intended to indicate or imply relative importance. The following description provides embodiments of the present application, where different embodiments may be substituted or combined, and thus the present application is intended to include all possible combinations of the same and/or different embodiments described. Thus, if one embodiment includes feature A, B, C and another embodiment includes feature B, D, then this application should also be considered to include an embodiment that includes one or more of all other possible combinations of A, B, C, D, even though this embodiment may not be explicitly recited in text below.
The following description provides examples, and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the described methods may be performed in an order different than the order described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
Referring to fig. 2, fig. 2 is a schematic flowchart of a method for verifying a multi-type concurrent access flow supporting multi-core shared access according to an embodiment of the present application. In an embodiment of the present application, the method includes:
s101, obtaining system information of a storage system corresponding to a memory access component to be tested, and constructing a verification system corresponding to the memory access component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models.
The execution subject of the present application may be a controller.
The memory access component to be tested can be understood as a core internal access memory component of a high-performance microprocessor needing to be tested in the embodiment of the application.
In the embodiment of the application, because the memory access component to be tested is only one part of the storage system expected to be used, and other components in the storage system need to be matched if the memory access component needs to be functionally verified, in the prior art, after the whole system or the memory access component is completely designed, a gradual function running verification process is performed on the whole system or the component in a software running simulation mode, the time consumption of the mode is very long in practical situations, for some complex systems, the verification time can be as long as several years, and the mode can start verification only when the whole system is completely designed, and the verification cannot be performed in the system design process. The method includes the steps that system information in a storage system used correspondingly by the memory access component to be tested is obtained, so that the current or expected use operation environment of the storage system and the connection mode of the memory system and other components are determined according to the system information, a corresponding verification system is independently constructed based on the system information, other components in the verification system are replaced by virtual models, and due to the fact that other components are virtual models, the corresponding environment can be directly simulated and directly verified based on the virtual models directly aiming at part of designed functions in the design process of the memory access component to be tested, and the efficiency is higher. For example, the generated verification system may be as shown in fig. 3, where VTX is a virtual model corresponding to TBOX, VIO is a virtual model corresponding to IOBOX, VEX is a virtual model corresponding to EBOX, VSX is a virtual model corresponding to SBOX, VLX is a virtual model corresponding to LDM, VGLX is a virtual model corresponding to GLDM, and VMEM is a virtual model corresponding to MEMORY.
In one possible embodiment, step S101 includes:
acquiring system information of a storage system corresponding to a memory access component to be tested, wherein the system information comprises a memory access request source component, a memory access object and a response object corresponding to the memory access component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can correspond to each other one by one and realize the functions of the access request source components, the access objects and the response objects;
and constructing a verification system corresponding to the memory access component to be tested based on each virtual model.
In the embodiment of the application, after system information of a corresponding storage system is acquired, information related to a memory access request source component, a memory access object, a response object and the like corresponding to a memory access component to be tested can be determined, training data can be generated in a targeted manner according to the information, each virtual model corresponding to each component object one to one is finally obtained, and a verification system can be constructed through each virtual model.
S102, when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs.
The multi-source core request instruction can be understood as corresponding instruction information generated when a multi-source core access request occurs in the embodiment of the application.
In the embodiment of the application, after a multi-source core request instruction is detected, in order to perform concurrent response processing on each source in the instruction, each corresponding test stimulus in the instruction needs to be determined based on the instruction.
In one embodiment, after determining, when a multi-source core request instruction is detected, each test stimulus for issuing the multi-source core request instruction, where the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
generating analog address bits to characterize a core of a call;
and performing cross-core memory access sharing based on the analog address bits.
In the embodiment of the present application, in order to implement cross-core access, it is first necessary to be able to identify each core, and the present application generates an analog address bit to characterize a called core. Specifically, the cores are identified in a binary manner, for example, 0001 denotes the core 1,0010 denotes the core 2,0011 denotes the core 3, and the like. After the analog address bit is determined, the analog address bit can be used as a cross-core memory access shared address, so that the memory access flow verification process of multi-core shared access is realized.
In one embodiment, after determining, when a multi-source core request instruction is detected, each test stimulus for issuing the multi-source core request instruction, where the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs, the method further includes:
and dividing different local memory addresses based on the test excitations, and generating control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test excitations.
In the embodiment of the application, different local memory addresses can be divided for each request source to store, so that the condition of multi-source memory access request concurrency is realized. And through setting and generating corresponding control environment parameters, the interval of request/response sending/receiving is realized, error checking and problem finding are facilitated, and the function of the access flow of a real access component can be simulated to the greatest extent.
S103, respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request command in parallel based on each virtual model to obtain each virtual response result.
In the embodiment of the application, after each test stimulus is determined, each virtual model suitable for each test stimulus operation can be found and confirmed according to each test stimulus, that is, the virtual model corresponding to each test stimulus is found, and after all the virtual models are completely corresponded, the multi-source core request instruction can be processed in parallel based on each virtual model, so that each virtual response result is obtained.
In one possible embodiment, step S103 includes:
respectively determining each virtual model corresponding to each test excitation;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to generate each storage visit based on the multi-source core request instruction simulation, and sending each storage visit to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
In the embodiment of the application, after multi-source core request instructions are processed in parallel based on each virtual model, a virtual response result directly output by the virtual model can be obtained. And the virtual model can also simulate and generate storage access based on the multi-source core request instruction, and then send the storage access to the memory access component to be tested for direct access processing to obtain a real response result. By comparing the virtual response result with the real response result, the correctness of the memory access component to be tested can be judged.
In one embodiment, the method further comprises:
when a test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training and generating a new virtual model based on the similar sample excitation set, and adding the new virtual model into the verification system.
In the embodiment of the application, because each virtual model in the verification system is constructed based on the current state of the memory access component to be tested, and the memory access component to be tested is not necessarily completely designed with all functions at present, when a new function is designed subsequently and needs to be verified, the generated virtual model may not meet the verification requirement of the function. Therefore, when a test stimulus which cannot correspond to any virtual model exists, a similar sample stimulus set is generated according to the data type of the test stimulus, so that a new virtual model is generated through training and added to the verification system, and the verification of functions is added newly.
The multi-type concurrent memory access flow verification system supporting multi-core shared access provided by the embodiment of the present application will be described in detail below with reference to fig. 4. It should be noted that, the multi-type concurrent access flow verification system supporting multi-core shared access shown in fig. 4 is used for executing the method of the embodiment shown in fig. 2 of the present application, for convenience of description, only the part related to the embodiment of the present application is shown, and details of the specific technology are not disclosed, please refer to the embodiment shown in fig. 2 of the present application.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a multi-type concurrent access flow verification apparatus supporting multi-core shared access according to an embodiment of the present application. As shown in fig. 4, the apparatus includes:
an obtaining module 201, configured to obtain system information of a storage system corresponding to an access component to be tested, and construct a verification system corresponding to the access component to be tested based on the system information, where the verification system includes a plurality of virtual models;
the system comprises a determining module 202, a storing module and a judging module, wherein the determining module 202 is used for determining each test stimulus for sending a multi-source core request instruction when the multi-source core request instruction is detected, and the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
the processing module 203 is configured to determine each virtual model corresponding to each test stimulus, and process the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
In one implementation, the obtaining module 201 includes:
the system comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring system information of a storage system corresponding to a memory access component to be tested, and the system information comprises a memory access request source component, a memory access object and a response object corresponding to the memory access component to be tested;
a corresponding function realization unit, configured to generate a plurality of virtual models based on the system information, so that each virtual model can correspond to one another and realize the functions of each access request source component, access object, and response object;
and the verification system construction unit is used for constructing a verification system corresponding to the memory access component to be tested based on each virtual model.
In one possible embodiment, the apparatus comprises:
the simulation address bit generation module is used for generating simulation address bits, and the simulation address bits are used for representing called cores;
and the sharing module is used for carrying out cross-core memory access sharing based on the analog address bit.
In one possible embodiment, the apparatus comprises:
and the control environment parameter generating unit is used for dividing different local memory addresses based on the test excitations and generating control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test excitations.
In one possible implementation, the processing module 203 includes:
an excitation determining unit configured to determine each of the virtual models corresponding to each of the test excitations, respectively;
the parallel processing unit is used for processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
the simulation generation unit is used for controlling each virtual model to generate each storage visit based on the multi-source core request instruction in a simulation mode, and sending each storage visit to the memory access component to be tested to obtain each real response result;
and the comparison unit is used for comparing the virtual response result with the real response result and judging the correctness of the memory access component to be tested.
In one possible embodiment, the apparatus comprises:
the judging module is used for generating a similar sample excitation set based on the test excitation when the test excitation which cannot correspond to any virtual model exists;
and the adding module is used for training and generating a new virtual model based on the similar sample excitation set and adding the new virtual model into the verification system.
It is clear to a person skilled in the art that the solution according to the embodiments of the present application can be implemented by means of software and/or hardware. The "unit" and "module" in this specification refer to software and/or hardware that can perform a specific function independently or in cooperation with other components, where the hardware may be, for example, a Field-Programmable Gate Array (FPGA), an Integrated Circuit (IC), or the like.
Each processing unit and/or module in the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.
Referring to fig. 5, a schematic structural diagram of an electronic device according to an embodiment of the present application is shown, where the electronic device may be used to implement the method in the embodiment shown in fig. 2. As shown in fig. 5, the electronic device 300 may include: at least one central processor 301, at least one network interface 304, a user interface 303, a memory 305, at least one communication bus 302.
Wherein a communication bus 302 is used to enable the connection communication between these components.
The user interface 303 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 303 may further include a standard wired interface and a wireless interface.
The network interface 304 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
The central processor 301 may include one or more processing cores. The central processor 301 connects various parts within the entire electronic device 300 using various interfaces and lines, and performs various functions of the terminal 300 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 305 and calling data stored in the memory 305. Alternatively, the central Processing unit 301 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The CPU 301 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the cpu 301, but may be implemented by a single chip.
The Memory 305 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 305 includes a non-transitory computer-readable medium. The memory 305 may be used to store instructions, programs, code sets, or instruction sets. The memory 305 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 305 may alternatively be at least one storage device located remotely from the central processor 301. As shown in fig. 3, memory 305, which is a type of computer storage medium, may include an operating system, a network communication module, a user interface module, and program instructions.
In the electronic device 300 shown in fig. 3, the user interface 303 is mainly used for providing an input interface for a user to obtain data input by the user; the central processing unit 301 may be configured to invoke a multi-type concurrent access flow verification application program supporting multi-core shared access stored in the memory 305, and specifically perform the following operations:
the method comprises the steps of obtaining system information of a storage system corresponding to an access storage component to be tested, and constructing a verification system corresponding to the access storage component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some service interfaces, devices or units, and may be an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, and the memory may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The above description is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure should not be limited thereby. That is, all equivalent changes and modifications made in accordance with the teachings of the present disclosure are intended to be included within the scope of the present disclosure. Embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (9)
1. A multi-type concurrent access flow verification method supporting multi-core shared access is characterized by comprising the following steps:
the method comprises the steps of obtaining system information of a storage system corresponding to an access storage component to be tested, and constructing a verification system corresponding to the access storage component to be tested based on the system information, wherein the verification system comprises a plurality of virtual models;
when a multi-source core request instruction is detected, determining each test stimulus for sending the multi-source core request instruction, wherein the multi-source core request instruction is corresponding instruction information generated when a multi-source core access request occurs;
and respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
2. The method as claimed in claim 1, wherein the obtaining of system information of a storage system corresponding to a memory access component to be tested, and the constructing of a verification system corresponding to the memory access component to be tested based on the system information are performed, and the verification system includes a plurality of virtual models, including:
acquiring system information of a storage system corresponding to a memory access component to be tested, wherein the system information comprises a memory access request source component, a memory access object and a response object corresponding to the memory access component to be tested;
generating a plurality of virtual models based on the system information, so that the virtual models can correspond to each other one by one and realize the functions of the access request source components, the access objects and the response objects;
and constructing a verification system corresponding to the memory access component to be tested based on each virtual model.
3. The method of claim 1, wherein after determining that each test stimulus for a multi-source core request instruction is issued when the multi-source core request instruction is detected, further comprising:
generating analog address bits to characterize a core of a call;
and performing cross-core memory access sharing based on the analog address bits.
4. The method of claim 1, wherein after determining that each test stimulus for a multi-source core request instruction is issued when the multi-source core request instruction is detected, further comprising:
and dividing different local memory addresses based on the test excitations, and generating control environment parameters corresponding to the local memory addresses, wherein the control environment parameters are used for controlling the processing time interval of the test excitations.
5. The method of claim 1, wherein the separately determining each of the virtual models corresponding to each of the test stimuli and processing the multi-source core request instructions in parallel based on each of the virtual models to obtain each of the virtual response results comprises:
respectively determining each virtual model corresponding to each test excitation;
processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result;
controlling each virtual model to generate each storage visit based on the multi-source core request instruction simulation, and sending each storage visit to the memory access component to be tested to obtain each real response result;
and comparing the virtual response result with the real response result, and judging the correctness of the memory access component to be tested.
6. The method of claim 1, further comprising:
when a test excitation which cannot correspond to any virtual model exists, generating a similar sample excitation set based on the test excitation;
training and generating a new virtual model based on the similar sample excitation set, and adding the new virtual model into the verification system.
7. A multi-type concurrent memory access flow verification apparatus supporting multi-core shared access, the apparatus comprising:
the system comprises an acquisition module, a verification module and a storage module, wherein the acquisition module is used for acquiring system information of a storage system corresponding to an access component to be tested and establishing a verification system corresponding to the access component to be tested based on the system information, and the verification system comprises a plurality of virtual models;
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining each test stimulus for sending a multi-source core request instruction when the multi-source core request instruction is detected;
and the processing module is used for respectively determining each virtual model corresponding to each test excitation, and processing the multi-source core request instruction in parallel based on each virtual model to obtain each virtual response result.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 1-6 are implemented when the computer program is executed by the processor.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 6.
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