CN113517197B - Vertical JFET device and method of making the same - Google Patents
Vertical JFET device and method of making the same Download PDFInfo
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- CN113517197B CN113517197B CN202111071595.6A CN202111071595A CN113517197B CN 113517197 B CN113517197 B CN 113517197B CN 202111071595 A CN202111071595 A CN 202111071595A CN 113517197 B CN113517197 B CN 113517197B
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/83—FETs having PN junction gate electrodes
- H10D30/831—Vertical FETs having PN junction gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/051—Manufacture or treatment of FETs having PN junction gates
- H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
- H10D30/0515—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates of vertical FETs having PN homojunction gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates
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Abstract
本发明提供一种垂直型JFET器件及其制备方法，形成了贯穿第一导电类型体区、第二导电类型体区，且与第一导电类型外延层相接触的第一导电类型沟道区，从而通过第一导电类型沟道区，可精确的优化垂直型JFET器件的沟道区宽度，以在缩小垂直型JFET器件面积的同时，可以调整垂直型JFET器件的夹断电压，以进一步提高器件的集成度和设计的灵活性。
The present invention provides a vertical type JFET device and a preparation method thereof. A first conductive type channel region is formed through the first conductive type body region and the second conductive type body region and in contact with the first conductive type epitaxial layer, Therefore, through the channel region of the first conductivity type, the width of the channel region of the vertical JFET device can be precisely optimized, so that the pinch-off voltage of the vertical JFET device can be adjusted while reducing the area of the vertical JFET device, so as to further improve the device. integration and design flexibility.
Description
Technical Field
The invention belongs to the field of semiconductors, and relates to a vertical JFET device and a preparation method thereof.
Background
A Junction Field Effect Transistor (JFET) is a three-terminal active device with an amplifying function, and its operating principle is to control an output current by changing the conductivity of a channel through a voltage. Unlike the surface type MOSFET, the JFET has a channel inside the semiconductor, and carriers in the channel are not affected by the surface effect of the semiconductor, so the mobility is high and the noise is low.
JFETs are divided into Vertical JFETs (VJFETs) and horizontal JFETs (LJFETs) according to their conduction paths, wherein the conduction paths of the LJFETs are lateral, i.e. the sources and drains are all distributed on the front side, and the conduction paths of the VJFETs are longitudinal, i.e. the drains are often arranged on the back side of the substrate. Because the pinch-off of the LJFET is difficult, the pinch-off voltage is usually higher, the adjustment is difficult, and the device area is larger, so that the VJFET has a larger advantage in the device integration level.
Currently, a conventional VJFET device is generally shown in fig. 1, and includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type body region (P-body) 3, a P-type active region 4, an N-type active region 6, a contact hole 7, a dielectric layer 8, and a source metal 9. Since the VJFET device is a normally-on device, when the VJFET device needs to be pinched off, a reverse bias voltage needs to be applied between the P-type body regions 3 and the N-type epitaxial layer 2, so that depletion layers are generated in the channel regions 5 between the adjacent P-type body regions 3, and when the depletion layers are gradually widened along with the increase of the reverse bias voltage, the effective on-channel of the channel regions 5 becomes narrower and narrower, when the channel regions 5 are completely depleted, the on-channel of the VJFET device is turned off, the VJFET device assumes an off high-resistance state, and the corresponding reverse bias voltage is called as the pinch-off voltage of the JFET device. However, the doping concentration of the channel region 5 of the VJFET device cannot be adjusted, and the width of the channel region 5 is a fixed value, and there is no optimized space, so the area of the vertical JFET device still cannot meet the ideal requirement.
Therefore, it is necessary to provide a vertical JFET device and a method for fabricating the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a vertical JFET device and a method for manufacturing the same, which are used to solve the problem that the doping concentration and width of the channel region of the vertical JFET device are difficult to adjust in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a vertical JFET device, comprising the steps of:
providing a first conductive type substrate;
forming a first conductive type epitaxial layer on the first conductive type substrate;
forming a second conductive type body region in the first conductive type epitaxial layer;
forming a first conductive type body region in the second conductive type body region;
forming a groove, wherein the groove penetrates through the first conductive type body region and the second conductive type body region and exposes the first conductive type epitaxial layer;
forming a first conductive type channel region in the trench;
forming a second conductivity type body contact region in the second conductivity type body region and a first conductivity type body contact region in the first conductivity type channel region;
forming a dielectric layer on the first conductive type epitaxial layer;
patterning the dielectric layer to form contact holes, wherein the contact holes comprise a first contact hole exposing the first conductive type body contact area and a second contact hole exposing the second conductive type body contact area;
and forming a source electrode metal structure, wherein the source electrode metal structure comprises a first source electrode metal structure filling the first contact hole and a second source electrode metal structure filling the second contact hole.
Optionally, a doping concentration of the first conductive type body contact region is greater than a doping concentration of the first conductive type channel region, and the doping concentration of the first conductive type channel region is greater than the doping concentration of the first conductive type body region.
Optionally, between the steps of forming the first conductivity type epitaxial layer and forming the second conductivity type body region, a step of forming a sacrificial layer is further included; a step of forming a barrier layer is further included prior to forming the first conductivity type body region, the first conductivity type channel region, the first conductivity type body contact region and the second conductivity type body contact region.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; or the first conduction type is P type, and the second conduction type is N type.
Optionally, a drain metal layer is further disposed below the first conductive type substrate.
Optionally, the source metal structure includes an ohmic contact metal pillar filling the contact hole and a source metal layer located on the dielectric layer and contacting the ohmic contact metal pillar.
The present embodiment also provides a vertical type JFET device, including:
a first conductive type substrate;
the first conductive type epitaxial layer is positioned on the first conductive type substrate;
a second conductivity type body region located in the first conductivity type epitaxial layer;
a first conductivity-type body region located in the second conductivity-type body region;
the groove penetrates through the first conductive type body region and the second conductive type body region and exposes the first conductive type epitaxial layer;
a first conductive-type channel region filling the trench;
a second conductivity type body contact region in the second conductivity type body region, and a first conductivity type body contact region in the first conductivity type channel region;
the dielectric layer is positioned on the first conduction type epitaxial layer;
contact holes including a first contact hole exposing the first conductive type body contact region and a second contact hole exposing the second conductive type body contact region;
and the source electrode metal structure comprises a first source electrode metal structure for filling the first contact hole and a second source electrode metal structure for filling the second contact hole.
Optionally, a doping concentration of the first conductive type body contact region is greater than a doping concentration of the first conductive type channel region, and the doping concentration of the first conductive type channel region is greater than the doping concentration of the first conductive type body region.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; or the first conduction type is P type, and the second conduction type is N type.
Optionally, a drain metal layer is further disposed below the first conductive type substrate.
As described above, according to the vertical JFET device and the method for manufacturing the same of the present invention, the first conductivity type channel region penetrating through the first conductivity type body region and the second conductivity type body region and contacting with the first conductivity type epitaxial layer is formed, so that the width of the channel region of the vertical JFET device can be precisely optimized through the first conductivity type channel region, so that the pinch-off voltage of the vertical JFET device can be adjusted while the area of the vertical JFET device is reduced, thereby further improving the integration level of the device and the flexibility of design.
Drawings
Fig. 1 shows a schematic structure of a vertical JFET device in the prior art.
Fig. 2 is a schematic structural diagram illustrating a first conductive type epitaxial layer and a sacrificial layer formed in the embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating the structure after the sacrificial layer is removed according to the embodiment of the invention.
Fig. 4 is a schematic structural view illustrating the second conductive type body region and the first barrier layer formed in the embodiment of the invention.
Fig. 5 is a schematic structural view after a first conductive type body region is formed according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram illustrating a second barrier layer and a trench formed in the embodiment of the invention.
Fig. 7 is a schematic structural view illustrating a first conductive channel region and a third barrier layer formed in accordance with an embodiment of the present invention.
Fig. 8 is a schematic structural view illustrating a first conductive type contact region and a second conductive type contact region formed in accordance with an embodiment of the present invention.
FIG. 9 is a schematic structural diagram illustrating a dielectric layer and a contact hole formed in an embodiment of the invention.
Fig. 10 is a schematic structural diagram illustrating an ohmic contact metal pillar formed according to an embodiment of the invention.
Fig. 11 is a schematic structural diagram illustrating a source metal layer formed in an embodiment of the invention.
Description of the element reference numerals
A 1-N type substrate; 2-N type epitaxial layer; a 3-P type body region; a 4-P active region; 5-a channel region; a 6-N active region; 7-a contact hole; 8-a dielectric layer; 9-source metal; a 100-N type substrate; a 200-N type epitaxial layer; a 300-P type body region; a 400-N type body region; 501-a groove; a 500-N type channel region; a 600-P type body contact region; a 700-N type body contact region; 800-a dielectric layer; 801-contact holes; 901-ohmic contact metal posts; 902-source metal layer; 110-a sacrificial layer; 210-a first barrier layer; 220-a second barrier layer; 230-third barrier layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
The embodiment provides a preparation method of a vertical JFET device, which comprises the following steps:
s1: providing a first conductive type substrate;
s2: forming a first conductive type epitaxial layer on the first conductive type substrate;
s3: forming a second conductive type body region in the first conductive type epitaxial layer;
s4: forming a first conductive type body region in the second conductive type body region;
s5: forming a groove, wherein the groove penetrates through the first conductive type body region and the second conductive type body region and exposes the first conductive type epitaxial layer;
s6: forming a first conductive type channel region in the trench;
s7: forming a second conductivity type body contact region in the second conductivity type body region and a first conductivity type body contact region in the first conductivity type channel region;
s8: forming a dielectric layer on the first conductive type epitaxial layer;
s9: patterning the dielectric layer to form contact holes, wherein the contact holes comprise a first contact hole exposing the first conductive type body contact area and a second contact hole exposing the second conductive type body contact area;
s10: and forming a source electrode metal structure, wherein the source electrode metal structure comprises a first source electrode metal structure filling the first contact hole and a second source electrode metal structure filling the second contact hole.
The preparation of the vertical JFET device is not limited thereto, and the specific preparation steps can be adjusted adaptively according to needs, and the preparation of the vertical JFET device in this embodiment is further described below with reference to fig. 2 to 11.
First, step S1 is performed to provide a first conductivity type substrate.
Specifically, the first conductivity type may be an N-type, and the corresponding second conductivity type is a P-type; or if the first conductive type is a P type, the corresponding second conductive type is an N type. Referring to fig. 2, in the embodiment, the first conductive type is selected as an N-type substrate 100, and the N-type substrate 100 may be a doped silicon substrate, a doped sapphire substrate, or even a doped silicon substrate, which is not limited herein.
Next, step S2 is performed to form a first conductive type epitaxial layer on the first conductive type substrate.
Specifically, referring to fig. 2, in the present embodiment, an N-type epitaxial layer 200 is formed on the N-type substrate 100. Preferably, after the first conductivity type epitaxial layer is formed, a step of forming a sacrificial layer is further included. That is, after forming the N-type epitaxial layer 200, a layer of sacrificial layer 110 may be formed on the surface of the N-type epitaxial layer 200, wherein the sacrificial layer 110 may be selected from silicon oxide having a thickness of 500 a formed at 950 ℃ using a dry thermal oxygen process, and after forming the sacrificial layer 110, the sacrificial layer 110 may be removed by wet etching, so that a silicon surface having better quality may be obtained, as shown in fig. 3.
Next, step S3 is performed to form a second conductivity type body region in the first conductivity type epitaxial layer.
Specifically, referring to fig. 4, P-type body regions 300 may be formed in the N-type epitaxial layer 200 by implanting trivalent boron B into the N-type epitaxial layer 200, wherein the implantation energy of the B element may be 120KEV and the dose may be E13, but the implantation energy, energy and dose are not limited thereto, and for example, indium or gallium may be used for P-type doping.
Next, step S4 is performed to form a first conductive body region in the second conductive body region.
Specifically, referring to fig. 4 and 5, in the present embodiment, before forming the N-type body region 400, a step of forming the first blocking layer 210 is preferably further included, and then a patterned photoresist (not shown) is formed on the surface of the first blocking layer 210 to form a process window for preparing the N-type body region 400, so that through the photoresist and the shielding of the first blocking layer 210, a pentavalent element can be implanted through the process window to perform N-type doping, such as doping of phosphorus and arsenic, to form the N-type body region 400, and meanwhile, through the shielding of the first blocking layer 210, damage to other regions of the device can be avoided. In this embodiment, the N-type body region 400 is formed by implanting phosphorus P element, wherein the implantation energy is 80KEV and the dose is E13, to form the shallow-well N-type body region 400, but the elements, energies, and doses of the N-type doping can be selected according to the requirement, and are not limited herein, and the first barrier layer 210 can be made of silicon oxide, but is not limited thereto.
Next, step S5 is performed to form a trench, where the trench penetrates through the first conductivity-type body region and the second conductivity-type body region, and the trench exposes the first conductivity-type epitaxial layer.
Specifically, as shown in fig. 6, in this embodiment, it is preferable that a step of forming the second barrier layer 220 is further included before forming the trench 501, and then a patterned photoresist (not shown) is formed on a surface of the second barrier layer 220 to form a process window for preparing the trench 501, and the second barrier layer 220 blocks the process window, so that damage to other regions of the device can be avoided. The second blocking layer 220 may be made of silicon oxide, but is not limited thereto. In this embodiment, a silicon oxide layer having a thickness of 3000 a is deposited on the surface of the P-type body region 300 as a blocking layer, but the material and thickness of the second barrier layer 220 are not limited thereto. After etching, the bottom of the formed trench 501 exposes the N-type epitaxial layer 200, and the sidewall of the trench 501 exposes the P-type body region 300 and the N-type body region 400.
Next, step S6 is performed to form a first conductive channel region in the trench.
Specifically, referring to fig. 7, in the present embodiment, an N-type channel region 500 filling the trench 501 is formed in the trench 501 by using an epitaxial technique, so that the N-type channel region 500 in contact with the N-type epitaxial layer 200, the P-type body region 300, and the N-type body region 400 can be formed, and by using the N-type channel region 500, the width of the channel region of the vertical JFET device can be precisely optimized, so that the pinch-off voltage of the vertical JFET device can be adjusted while the area of the vertical JFET device is reduced, and the integration level and the design flexibility of the device can be further improved.
Next, step S7 is performed to form a second conductive type contact region in the second conductive type body region and a first conductive type contact region in the first conductive type channel region.
Specifically, as shown in fig. 8, in this embodiment, it is preferable that before forming the P-type body contact region 600 and the N-type body contact region 700, a step of forming a third barrier layer 230 is further included, and then a patterned photoresist (not shown) is formed on a surface of the third barrier layer 230 to form a process window for preparing the P-type body contact region 600 and the N-type body contact region 700, and the third barrier layer 230 shields the process window, so that damage to other regions of the device can be avoided. The third barrier layer 230 may be made of silicon oxide, but is not limited thereto. In this embodiment, a silicon oxide layer having a thickness of 500 a is deposited as a blocking layer on the surface of the P-type body region 300, but the material and thickness of the third barrier layer 230 are not limited thereto. The P-type body contact region 600 is then formed by ion implantation at the top of the P-type body region 300 and the N-type body contact region 700 is formed by ion implantation at the top of the N-type channel region 500.
As an example, a doping concentration of the first conductive type body contact region is greater than a doping concentration of the first conductive type channel region, and the doping concentration of the first conductive type channel region is greater than the doping concentration of the first conductive type body region.
Specifically, as shown in fig. 8, in order to provide the conductivity of the N-type channel region 500, the doping concentration is preferably selected such that the N-type body contact region 700 > the N-type channel region 500 > the N-type body region 400. The specific doping concentrations for the N-type body contact region 700, the N-type channel region 500, and the N-type body region 400 can be set as desired and are not overly limited herein.
Then, step S8 is performed to form a dielectric layer on the first conductive type epitaxial layer, and step S9 is performed to pattern the dielectric layer to form contact holes, wherein the contact holes include a first contact hole exposing the first conductive type body contact region and a second contact hole exposing the second conductive type body contact region.
Specifically, as shown in fig. 9, a dielectric layer 800 is formed on the surface of the P-type body region 300, and the dielectric layer 800 is patterned to form a contact hole 801 penetrating through the dielectric layer 800 in the dielectric layer 800, wherein the contact hole 801 includes a first contact hole exposing the N-type body contact region 700 and a second contact hole exposing the P-type body contact region 600. The dielectric layer 800 may be made of silicon oxide, silicon nitride, etc., and the specific material and thickness thereof are not limited herein.
Next, step S10 is performed to form a source metal structure, where the source metal structure includes a first source metal structure filling the first contact hole and a second source metal structure filling the second contact hole.
Specifically, as shown in fig. 10 and 11, in this embodiment, the source metal structure includes an ohmic contact metal pillar 901 filling the contact hole 801 and a source metal layer 902 located on the dielectric layer 800 and contacting the ohmic contact metal pillar 901, and the source metal structures are insulated and isolated by the dielectric layer 800.
Referring to fig. 10, the ohmic contact metal pillar 901 may be prepared using a CVD process, for example, a TI having a thickness of 400 a and a TIN of 500 a may be sequentially deposited in the contact hole 801 to form a metal transition layer, and then metal tungsten may be filled to form the ohmic contact metal pillar 901. Then, referring to fig. 11, a metal layer is deposited on the surface of the dielectric layer 800, and is selectively etched to form a patterned source metal layer 902 in contact with the ohmic contact metal pillar 901, where the material, distribution, structure, and preparation method of the ohmic contact metal pillar 901 and the source metal layer 902 are not limited herein.
As an example, a step of forming a drain metal layer under the first conductive type substrate may be further included, that is, a drain metal layer (not shown) may be formed on the bottom surface of the N-type substrate 100, and the material and the thickness of the drain metal layer are not limited herein.
The embodiment also provides a vertical type JFET device which can be formed by the preparation method, but is not limited to the preparation method.
Specifically, the vertical type JFET device comprises a first conduction type substrate, a first conduction type epitaxial layer, a second conduction type body region, a first conduction type body region, a groove, a first conduction type channel region, a second conduction type body contact region, a first conduction type body contact region, a dielectric layer, a contact hole and a source electrode metal structure. Wherein the first conductivity type epitaxial layer is located on the first conductivity type substrate, the second conductivity type body region is located in the first conductivity type epitaxial layer, the first conductivity type body region is located in the second conductivity type body region, the trench penetrates through the first conductivity type body region and the second conductivity type body region, and the trench exposes the first conductivity type epitaxial layer, the first conductivity type channel region fills the trench, the second conductivity type body contact region is located in the second conductivity type body region, the first conductivity type body contact region is located in the first conductivity type channel region, the dielectric layer is located on the first conductivity type epitaxial layer, the contact holes include a first contact hole exposing the first conductivity type body contact region, and a second contact hole exposing the second conductivity type body contact region, the source electrode metal structure comprises a first source electrode metal structure filling the first contact hole and a second source electrode metal structure filling the second contact hole.
Referring to fig. 2 to 11, in the present embodiment, the first conductive type is an N-type, and the second conductive type is a P-type, but not limited thereto, in another embodiment, the first conductive type may also be a P-type, and the second conductive type is an N-type.
Specifically, in this embodiment, the vertical JFET device includes an N-type substrate 100, an N-type epitaxial layer 200, a P-type body region 300, an N-type body region 400, a trench 501, an N-type channel region 500, a P-type body contact region 600, an N-type body contact region 700, a dielectric layer 800, a contact hole 801, and a source metal structure.
Wherein the N-type epitaxial layer 200 is located on the N-type substrate 100, the P-type body region 300 is located in the N-type epitaxial layer 200, the N-type body region 400 is located in the P-type body region 300, the trench 501 penetrates the N-type body region 400 and the P-type body region 300, the trench 501 exposes the N-type epitaxial layer 200, the N-type channel region 500 fills the trench 501, the P-type body contact region 600 is located in the P-type body region 300, the N-type body contact region 700 is located in the N-type channel region 500, the dielectric layer 800 is located on the N-type epitaxial layer 200, the contact hole 801 includes a first contact hole exposing the N-type body contact region 700 and a second contact hole exposing the P-type body contact region 600, the source metal structure includes an ohmic contact metal pillar 901 filling the first contact hole and filling the second contact hole and a source gold located on a surface of the dielectric layer 800 and in contact with the ohmic contact metal pillar 901 An auxiliary layer 902.
As an example, a doping concentration of the first conductive type body contact region is greater than a doping concentration of the first conductive type channel region, and the doping concentration of the first conductive type channel region is greater than the doping concentration of the first conductive type body region. I.e., the magnitude relationship of the doping concentration is preferably such that the N-type body contact region 700 > the N-type channel region 500 > the N-type body region 400 to provide the conductivity of the N-type channel region 500.
As an example, a drain metal layer (not shown) may be further disposed under the first conductive type substrate.
In summary, according to the vertical JFET device and the method for manufacturing the same of the present invention, the first conductivity type channel region penetrating through the first conductivity type body region and the second conductivity type body region and contacting with the first conductivity type epitaxial layer is formed, so that the width of the channel region of the vertical JFET device can be precisely optimized through the first conductivity type channel region, so as to reduce the area of the vertical JFET device and adjust the pinch-off voltage of the vertical JFET device, thereby further improving the integration level of the device and the flexibility of the design.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040232450A1 (en) * | 2002-12-20 | 2004-11-25 | Hamza Yilmaz | Self-aligned trench MOS junction field-effect transistor for high-frequency applications |
| US20080230812A1 (en) * | 2002-08-14 | 2008-09-25 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
| CN103811353A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Junction field-effect transistor and preparation method thereof |
| US20150340476A1 (en) * | 2012-05-07 | 2015-11-26 | Avogy, Inc. | Method and system for planar regrowth in gan electronic devices |
| CN111200025A (en) * | 2018-11-20 | 2020-05-26 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080230812A1 (en) * | 2002-08-14 | 2008-09-25 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
| US20040232450A1 (en) * | 2002-12-20 | 2004-11-25 | Hamza Yilmaz | Self-aligned trench MOS junction field-effect transistor for high-frequency applications |
| US20150340476A1 (en) * | 2012-05-07 | 2015-11-26 | Avogy, Inc. | Method and system for planar regrowth in gan electronic devices |
| CN103811353A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Junction field-effect transistor and preparation method thereof |
| CN111200025A (en) * | 2018-11-20 | 2020-05-26 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
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