CN113363240A - Chip metal wire, manufacturing method thereof and wafer - Google Patents
Chip metal wire, manufacturing method thereof and wafer Download PDFInfo
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- CN113363240A CN113363240A CN202110458966.XA CN202110458966A CN113363240A CN 113363240 A CN113363240 A CN 113363240A CN 202110458966 A CN202110458966 A CN 202110458966A CN 113363240 A CN113363240 A CN 113363240A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 179
- 239000002184 metal Substances 0.000 title claims abstract description 179
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000012360 testing method Methods 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 239000000377 silicon dioxide Substances 0.000 claims description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000011161 development Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000005286 illumination Methods 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 abstract description 15
- 239000000463 material Substances 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002224 dissection Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
Abstract
本发明提供一种芯片金属线及其制作方法、晶圆，属于芯片领域。所述芯片金属线包括第一金属线，所述第一金属线垂直横跨相邻两块芯片之间的划片槽，且所述第一金属线的两个连接端位于同一块芯片内，所述连接端用于连接芯片内的测试电路模块。本申请提供的芯片金属线垂直横跨相邻两块芯片之间的划片槽，保持划片槽内材质组成均匀，使得锯片两面在划片槽内所受的压力一致，不会出现锯片切割歪斜，影响切割质量，同时保证第一金属线被锯片切割开。
The invention provides a chip metal wire, a manufacturing method thereof, and a wafer, which belong to the field of chips. The chip metal wire includes a first metal wire, the first metal wire vertically spans the dicing groove between two adjacent chips, and the two connection ends of the first metal wire are located in the same chip, The connecting end is used for connecting the test circuit module in the chip. The chip metal wire provided by the application vertically spans the dicing groove between two adjacent chips, and the material composition in the dicing groove is kept uniform, so that the pressure on both sides of the saw blade in the dicing groove is consistent, and no sawing occurs. The blade cutting is skewed, which affects the cutting quality, and at the same time ensures that the first metal wire is cut by the saw blade.
Description
Technical Field
The invention relates to the field of chips, in particular to a chip metal wire, a manufacturing method of the chip metal wire and a wafer.
Background
Wafer dicing (i.e., dicing) is an essential process in the semiconductor chip manufacturing process, and belongs to a subsequent process in wafer manufacturing. The whole wafer with the chips is divided into single chips (crystal grains) according to the size of the chips, and the single chips are called wafer scribing.
In the industry, saw blade cutting and laser cutting are currently used for die sawing. The diamond saw blade (grinding wheel) cutting belongs to the traditional scribing method, has lower cost and occupies a larger share of the global chip cutting market. The laser cutting belongs to a novel scribing method, can be used for non-contact processing, does not generate mechanical stress on a wafer, has small damage and higher cost.
In chip design, fuse (also called metal wire, fuse wire) exists for CP (chip combining) test, and after CP test is finished, the fuse is required to be cut off, and the chip can normally work. For ease of operation, some chip designs keep the fuse in a scribeline (scribe line). When die sawing is carried out, the wafer can be cut off, and the fuse is cut off at the same time, so that the design scheme for breaking the fuse is ingenious.
In the prior art, as shown in fig. 1, a fuse structure is similar to a gate, two end points extend out from the chip, and the gate is horizontally located in a scribing slot. When the saw blade is used for cutting a wafer, because fuse exists in the scriber line, the material composition in the scriber line is uneven (fuse is a copper wire and the scriber is SiO2), the pressure on two sides of the saw blade in the scriber line is inconsistent, so that the saw blade is cut and inclined, on one hand, the cutting quality is influenced, on the other hand, part of fuse cannot be cut and disconnected, and in the subsequent chip application, the chip function is invalid.
Disclosure of Invention
The invention aims to provide a chip metal wire and a manufacturing method thereof.
In order to achieve the above object, a first aspect of the present invention provides a chip metal line, where the chip metal line includes a first metal line, the first metal line vertically crosses a scribe line between two adjacent chips, and two connection ends of the first metal line are located in a same chip, and the connection ends are used to connect test circuit modules in the chips.
Optionally, the first metal wire has a rectangular wave structure with wave troughs and wave crests, the wave troughs of the first metal wire are all located in one chip, and the wave crests are all located in another adjacent chip.
Optionally, the first metal wire is a zigzag metal wire. The arched metal wire vertically crosses the scribing groove for many times, and when scribing is carried out, the whole metal wire can be completely disconnected as long as a section of metal wire crossing the scribing groove is cut by the saw blade.
Optionally, the two connection ends of the first metal wire are respectively a first connection end and a second connection end; the metal line further includes a first metal segment connected with the first connection end and/or the second connection end of the first metal line to form two connection ends of the metal line and to connect the two connection ends of the metal line to a test circuit module within a chip. The first metal section is arranged to connect two connecting ends of the metal wire to the test circuit module so as to ensure that the test can be carried out.
The invention provides a chip metal wire manufacturing method in a second aspect, which comprises the following steps:
s1: coating photoresist on the substrate board completely;
s2: performing illumination development, and removing the photoresist at the corresponding position of the section of the metal wire on the substrate plate;
s3: etching the substrate plate to form a groove which is used for arranging the metal wire and is matched with the section of the metal wire;
s4: removing all the photoresist on the substrate plate;
s5: depositing metal on the substrate plate to fill the trench;
s6: removing redundant metal;
s7: depositing a substrate layer;
s8: repeating the above steps S1-S7 until the metal line is formed. The metal wire manufactured by the method has a plurality of metal sections vertically crossing the scribing groove, and the material composition in the scribing groove is kept uniform, so that the pressure on two sides of the saw blade in the scribing groove is consistent, and the saw blade cannot be cut obliquely to influence the cutting quality. And the process manufacturing slow link is not increased, and the process cost is not increased.
Further, the substrate is a silica substrate.
The third aspect of the present invention provides a wafer, where the wafer includes a plurality of chips, and the chip metal lines are disposed between two adjacent chips in the plurality of chips. Have chip metal wire in this application can guarantee the dissection metal wire at cutting process, guarantee and the in-process saw bit disappearance is crooked, promote the yields of chip after the cutting.
Through above-mentioned technical scheme, the chip metal wire that this application provided spanes perpendicularly the scribing groove between two adjacent chips, keeps the scribing inslot material to constitute evenly for the saw bit both sides are unanimous at the pressure that the scribing inslot received, and saw bit cutting skew can not appear, influences the cutting quality, guarantees simultaneously that first metal wire is cut by the saw bit and is opened.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art metal line structure;
fig. 2 is a schematic front view of a metal line structure according to a first embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a metal line structure A-A according to a first embodiment of the present invention;
FIG. 4 is a flow chart of a metal line fabrication process provided in a first embodiment of the present invention;
FIG. 5 is a schematic top view of a metal line structure according to a second embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a metal line structure A-B according to a second embodiment of the present invention;
fig. 7A to 7G are flow charts of manufacturing a metal line according to a second embodiment of the present invention.
Description of the reference numerals
1-first chip, 2-second chip, 3-scribing groove, 4-metal line, 41-wave crest, 42-wave trough, 43-first metal section.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
In the embodiments of the present application, unless otherwise stated, the use of directional terms such as "upper, lower, left, and right" generally refers to the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the embodiment is usually placed when in use. The terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The terms "parallel", "perpendicular", etc. do not require that the components be absolutely parallel or perpendicular, but may be slightly inclined. For example, "parallel" merely means that the directions are more parallel relative to "perpendicular," and does not mean that the structures are necessarily perfectly parallel, but may be slightly tilted.
The invention provides a chip metal wire, which comprises a first metal wire, wherein the first metal wire vertically crosses a scribing groove between two adjacent chips, two connecting ends of the first metal wire are positioned in the same chip, and the connecting ends are used for connecting test circuit modules in the chips.
Optionally, the first metal wire has a rectangular wave structure with wave troughs and wave crests, the wave troughs of the first metal wire are all located in one chip, and the wave crests are all located in another adjacent chip.
Optionally, the first metal wire is a zigzag metal wire. The arched metal wire vertically crosses the scribing groove for many times, and when scribing is carried out, the whole metal wire can be completely disconnected as long as a section of metal wire crossing the scribing groove is cut by the saw blade.
Two optional connecting ends of the first metal wire are respectively a first connecting end and a second connecting end; the metal line further includes a first metal segment connected with the first connection end and/or the second connection end of the first metal line to form two connection ends of the metal line and to connect the two connection ends of the metal line to a test circuit module within a chip. The first metal section is arranged to connect two connecting ends of the metal wire to the test circuit module so as to ensure that the test can be carried out.
Optionally, the metal wire is a copper wire or an aluminum wire, and is preferably a copper wire.
Example one
Fig. 2 and fig. 3 are schematic diagrams of a metal line structure according to a first embodiment of the present invention, and as shown in fig. 3, the metal line 4 includes a first metal line that vertically crosses a scribe line 3 between a first chip 1 and a second chip 2, and both connection ends of the first metal line are located in the first chip 1, and the connection ends are used for connecting a test circuit module in the chip.
In the present embodiment, the first metal wire is a zigzag metal wire, the first metal wire has a rectangular wave structure having one valley 42 and two peaks 41, the valley 42 of the first metal wire is located in the first chip 1, and the two peaks 41 are located in the second chip 2.
In this embodiment, the metal wire is a copper wire.
In this embodiment, the metal wire 4 is disposed between the first chip 1 and the second chip 2 in a horizontal zigzag shape, in this embodiment, two connection ends of the test circuit module in the chip are located in the same plane in the horizontal direction, and two connection ends of the first metal wire are also located in the same plane in the same way.
In other embodiments, the two connection terminals of the test circuit module in the chip may be located at different positions in the vertical direction, and in these embodiments, the metal wire 4 further includes a first metal segment 43, and the first metal segment 43 is connected to the first connection terminal and/or the second connection terminal of the first metal wire to form the two connection terminals of the metal wire 4, and the two connection terminals of the metal wire 4 are connected to the two connection terminals of the test circuit module.
Fig. 4 is a schematic view of a manufacturing process of the metal line in this embodiment, and the manufacturing process includes the following steps:
s1: coating photoresist on the silicon dioxide substrate plate in a full-surface mode, wherein the photoresist coating mode is spin coating;
s2: performing light irradiation development to remove the photoresist on the substrate plate at the position corresponding to the cross section of the metal wire, wherein the cross section of the metal wire is in a bow shape in the embodiment, so that the shape of the removed photoresist is also in a bow shape from the top view;
s3: etching the substrate plate to form a groove which is used for arranging the metal wire and is matched with the section of the metal wire, wherein the shape of the formed groove is also in a bow shape in the embodiment;
s4: removing all the photoresist on the substrate plate;
s5: depositing metal on the substrate plate to fill the trench, wherein the metal is copper in the embodiment;
s6: the excess metal is removed by chemical mechanical polishing in this embodiment, so that the metal line is completed. And continuously depositing a substrate layer on the upper layer to manufacture other structures of the chip.
In the embodiment, all parts of the metal wire are positioned on the same plane and have certain thickness only in the vertical direction, so that the metal wire can be manufactured only through the steps, and the manufacturing process is simple.
Example two
Fig. 5 and 6 are schematic structural diagrams of a metal line 4 according to a second embodiment of the present invention, and as shown in fig. 6, the metal line 4 includes a first metal line, the first metal line vertically crosses a scribe line 3 between a first chip 1 and a second chip 2, and two connection terminals of the first metal line are both located in the first chip 1, and the connection terminals are used for connecting test circuit modules in the chip.
In the present embodiment, the first metal wire is a zigzag metal wire, the first metal wire has a rectangular wave structure with one valley 42 and two peaks 41, the valleys 42 of the first metal wire are located in the first chip 1, and the two peaks 41 are located in the second chip 2.
In the present embodiment, the metal wire 4 is disposed between the first chip 1 and the second chip 2 in a vertical bow shape.
In this embodiment, the two connection terminals of the test circuit module in the chip are located in the same plane in the horizontal direction, so the two connection terminals of the metal wire also need to be located in the same plane, the two connection terminals of the first metal wire are defined as a first connection terminal and a second connection terminal, the metal wire 4 further includes a first metal section 43, and the first metal section 43 is connected to the second connection terminal of the first metal wire and extends upward, so that the two connection terminals of the metal wire 4 are connected to the two connection terminals of the test circuit module.
In other embodiments, the first metal segment 43 may be extended arbitrarily according to design requirements, so as to achieve the purpose of connecting the two connection ends of the metal wire 4 to the two connection ends of the test circuit module.
In this embodiment, the metal wire is a copper wire.
Fig. 7A to 7G are schematic diagrams illustrating a manufacturing process of the metal line in this embodiment, and the manufacturing process includes the following steps:
s1: coating photoresist on the silicon dioxide substrate plate in a full-surface mode, wherein the photoresist coating mode is spin coating;
s2: illuminating and developing, and removing the photoresist at the position of the substrate plate corresponding to the cross section of the metal wire, wherein in the step, the cross section of the metal wire is the cross section of the bottommost part of the bow-shaped structure, and the cross section at the moment is the cross section of the first metal section crossing the scribing groove;
s3: etching the substrate plate to form a groove which is used for arranging the metal wire and matched with the section of the metal wire, wherein in the step, the shape of the formed groove is the shape of the first metal section crossing the scribing groove;
s4: removing all the photoresist on the substrate plate;
s5: depositing metal on the substrate plate to fill the trench, wherein the metal is copper in the embodiment;
s6: removing the excess metal, in this embodiment, chemical mechanical polishing is used to remove the excess metal;
s7: depositing a silicon dioxide substrate layer;
s8: coating photoresist on the substrate layer;
s9: performing illumination development, removing the photoresist on the silicon dioxide substrate layer corresponding to the section of the metal wire, manufacturing a deeper groove during production, and then manufacturing a shallower groove, wherein in the step, the photoresist on the corresponding part of the first metal section cross section and the wave crest cross section is removed after development;
s10: etching the silicon dioxide substrate layer to form a groove for arranging the first metal section and the wave crest;
s11: removing all the photoresist on the silicon dioxide substrate layer;
s12: coating photoresist on the silicon dioxide substrate layer;
s13: performing illumination development, and removing the photoresist on the silicon dioxide substrate layer at the position corresponding to the second metal section crossing the scribing groove;
s14: etching the silicon dioxide substrate layer to form a groove which is used for arranging a second metal section crossing the scribing groove and is matched with the section of the second metal section crossing the scribing groove;
s15: removing all the photoresist on the silicon dioxide substrate layer;
s16: depositing metal on the silicon dioxide substrate layer to fill the groove, wherein the grooves formed in S10 and S14 are filled with the metal;
s17: removing redundant metal;
s18: depositing a silicon dioxide substrate layer;
s19: coating photoresist on the silicon dioxide substrate layer;
s20: performing illumination development, and removing the photoresist at the position corresponding to the cross sections of the first metal section and the wave trough;
s21: etching the silicon dioxide substrate layer to form a groove for arranging the first metal section and the wave trough;
s22: removing all the photoresist on the silicon dioxide substrate layer;
s23: coating photoresist on the silicon dioxide substrate layer;
s24: performing illumination development, and removing the photoresist at the position corresponding to the third metal segment crossing the scribing groove;
s25: etching the silicon dioxide substrate layer to form a groove for arranging a third metal section crossing the scribing groove;
s26: removing all the photoresist on the silicon dioxide substrate layer;
s27: depositing metal on the silicon dioxide substrate layer to fill the groove, wherein the grooves formed in S21 and S25 are filled with the metal;
s28: removing redundant metal;
s29: depositing a silicon dioxide substrate layer;
s30: coating photoresist on the silicon dioxide substrate layer;
s31: performing illumination development, and removing the photoresist at the position corresponding to the cross sections of the first metal section and the second wave crest;
s32: etching the silicon dioxide substrate layer to form a groove for arranging the first metal section and the second wave crest;
s33: removing all the photoresist on the silicon dioxide substrate layer;
s34: coating photoresist on the silicon dioxide substrate layer;
s35: performing illumination development, and removing the photoresist corresponding to the cross section of the fourth metal segment crossing the scribing groove;
s36: etching the silicon dioxide substrate layer to form a groove for arranging a fourth metal section crossing the scribing groove;
s37: removing all the photoresist on the silicon dioxide substrate layer;
s38: depositing metal on the silicon dioxide substrate layer to fill the groove, wherein the grooves formed in S32 and S36 are filled with the metal;
s39: and removing redundant metal to finish the metal wire manufacturing.
The metal wire manufactured by the method has a plurality of metal sections vertically crossing the scribing groove, and the material composition in the scribing groove is kept uniform, so that the pressure on two sides of the saw blade in the scribing groove is consistent, and the saw blade cannot be cut obliquely to influence the cutting quality. And the process manufacturing slow link is not increased, and the process cost is not increased.
The third aspect of the present invention provides a wafer, where the wafer includes a plurality of chips, and the chip metal lines are disposed between two adjacent chips in the plurality of chips. Can guarantee the dissection metal wire among the cutting process, guarantee and cross the in-process saw bit and do not appear crooked, promote the yields of chip after the cutting.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.
Claims (7)
1. The chip metal wire is characterized by comprising a first metal wire, wherein the first metal wire vertically crosses a scribing groove between two adjacent chips, two connecting ends of the first metal wire are positioned in the same chip, and the connecting ends are used for connecting test circuit modules in the chips.
2. The chip wire of claim 1, wherein the first wire has a rectangular wave-like structure with troughs and crests, the troughs of the first wire being located in one chip and the crests being located in another chip.
3. The chip wire of claim 1, wherein said first wire is a zig-zag wire.
4. The chip wire of claim 1, wherein the two connection ends of the first wire are a first connection end and a second connection end, respectively; the metal line further includes a first metal segment connected with the first connection end and/or the second connection end of the first metal line to form two connection ends of the metal line and to connect the two connection ends of the metal line to a test circuit module within a chip.
5. A method of making a chip wire, the method comprising:
s1: coating photoresist on the substrate board completely;
s2: performing illumination development, and removing the photoresist at the corresponding position of the section of the metal wire on the substrate plate;
s3: etching the substrate plate to form a groove which is used for arranging the metal wire and is matched with the section of the metal wire;
s4: removing all the photoresist on the substrate plate;
s5: depositing metal on the substrate plate to fill the trench;
s6: removing redundant metal;
s7: depositing a substrate layer;
s8: repeating the above steps S1-S7 until the metal line is formed.
6. The method of claim 5, wherein the substrate is a silicon dioxide substrate.
7. A wafer, comprising a plurality of chips, wherein the chip metal lines of any one of claims 1-4 are disposed between two adjacent chips in the plurality of chips.
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| CN202110458966.XA CN113363240A (en) | 2021-04-27 | 2021-04-27 | Chip metal wire, manufacturing method thereof and wafer |
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