CN113257842A

CN113257842A - Semiconductor device and method for integrating passive device

Info

Publication number: CN113257842A
Application number: CN202110511063.3A
Authority: CN
Inventors: 陈立均; 代文亮; 李苏萍
Original assignee: Shanghai Sinbo Electronic Technology Co ltd
Current assignee: Shanghai Sinbo Electronic Technology Co ltd
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2021-08-13

Abstract

The invention discloses a semiconductor device of an integrated passive device, which comprises: a substrate; at least one integrated passive device comprising one or more of a resistor, a capacitor, or an inductor formed on a surface of a substrate; a rewiring layer disposed on a surface of the substrate on which the at least one integrated passive device is disposed; the rewiring layer comprises at least one metal layer to form a layer-wound inductor. The invention combines the existing semiconductor integrated passive device process with the packaging RDL (RDL (redistribution layer) process, breaks through the limit of the mature process of the integrated circuit on the limit of a thick metal layer and the limit of the metal thickness, adds 1-3 layers of routable metal layers in combination with the RDL process, and can make the metal thickness thicker, thereby forming a richer laminated structure, thereby realizing the functions of layer winding inductance and connecting wiring, improving the design flexibility of the passive integrated device, and improving the performance and the integration level of the integrated passive device.

Description

Semiconductor device and method for integrating passive device

Technical Field

The invention relates to the technical field of integrated passive device processes, in particular to a semiconductor device and a method for integrating passive devices.

Background

As shown in fig. 5, the conventional integrated passive device process is a process for manufacturing a resistor, a capacitor, and an inductor by using a Back-End-Of-Line (Back-End-Of-Line) process, so as to implement passive devices such as a filter, a power divider, and a coupler. However, the process has a small number of thick metal layers, generally 1-2 layers, which causes that the area of a winding plane two-dimensional inductor is too large, or the number of turns of a winding longitudinal spiral inductor is too small, thereby causing that a high-performance inductor cannot be manufactured; meanwhile, based on the electroplating technology of the existing mature integrated circuit process, the thickness of electroplated metal is limited, so that the cross section of the metal is small, the unit resistance is large, the line loss is large, and the performance of the wound inductor is poor, so that the performance of the whole passive device is influenced.

Therefore, it is necessary to provide a further solution to the above problems.

Disclosure of Invention

The invention aims to provide a semiconductor device integrated with a passive device and a method thereof, so as to overcome the defects in the prior art.

In order to solve the technical problems, one technical scheme of the invention is as follows:

a semiconductor device incorporating passive components, comprising:

a substrate;

at least one integrated passive device comprising one or more of a resistor, a capacitor, or an inductor formed on the surface of the substrate;

a rewiring layer disposed on a surface of the substrate on which the at least one integrated passive device is disposed;

the redistribution layer comprises at least one metal layer to form a layer-wound inductor.

In a preferred embodiment of the present invention, the substrate is high-resistance silicon or glass.

In a preferred embodiment of the present invention, the redistribution layer uses a wire bonding, ball mounting or BUMP process to extract signals.

In a preferred embodiment of the present invention, the integrated passive device includes an inductor, and the metal layer of the redistribution layer is located directly above the inductor, and the deviation is not more than 10% of the minimum line width of the metal layer wound inductor.

In a preferred embodiment of the present invention, the thickness of the dielectric layer of the integrated passive device closest to the redistribution layer is 3-5 μm.

The other technical scheme of the invention is as follows:

an integrated passive device process for enhancing performance with a redistribution layer, comprising:

s100, forming at least one integrated passive device on a substrate;

s200, forming a rewiring layer on the surface of the integrated passive device formed on the substrate;

In a preferred embodiment of the present invention, the S100 forming at least one integrated passive device on a substrate includes:

s101, forming a resistance layer on a substrate through metal sputtering, photoetching and ion etching processes, and depositing a first dielectric layer on the resistance layer;

s102, etching a first through hole on the first dielectric layer through photoetching and etching processes, wherein the first through hole exposes a part of the substrate and a part of the resistance layer;

s103, depositing a first metal layer on the first dielectric layer, wherein the first metal layer is connected with the substrate and the resistance layer through a first through hole, etching a first metal layer pattern as a lower bottom plate of the capacitor through photoetching and etching processes, and depositing a second dielectric layer on the surface of the first metal layer as a dielectric layer of the capacitor;

s104, depositing a second metal layer on the second dielectric layer, etching a second metal layer pattern as an upper bottom plate of the capacitor by photoetching and etching processes, and depositing a third dielectric layer on the second metal layer pattern;

s105, etching a second through hole on the third dielectric layer through photoetching and etching processes, wherein the second through hole exposes a part of the second metal layer, and continuously etching a third metal layer pattern on the second through hole through photoetching and etching processes;

s106, sputtering a second through hole and a third metal layer seed layer through a metal sputtering process, completing the second through hole and the third metal layer through an electroplating process, finally completing the surface flattening of the wafer through chemical mechanical polishing, and depositing a fourth dielectric layer on the wafer;

s107, repeating S105-S106 to complete the manufacture of the third through hole and the fourth metal layer, depositing a fifth dielectric layer on the surface of the fourth metal layer, and etching the fourth through hole on the fifth dielectric layer through photoetching and etching processes.

In a preferred embodiment of the present invention, the S200 forming a redistribution layer on a surface of a substrate on which an integrated passive device is formed, includes:

s201, forming a seventh dielectric layer on the fifth dielectric layer through spin coating, and etching a fifth through hole at a position corresponding to the fourth through hole through photoetching;

s202, metal electroplating is carried out on the seventh dielectric layer to form a thicker metal layer, the sixth metal layer is manufactured through the processes of illumination, development and etching, and the sixth metal layer is connected with the fourth metal layer through the fifth through hole and the fourth through hole;

s203, spin-coating the surface of the sixth metal layer to form an eighth dielectric layer, and etching a sixth through hole at the corresponding position of the fourth through hole by photoetching;

s204, repeating S202 to form a seventh metal layer, turning to S205 in the bonding process, and turning to S206 in the ball mounting process;

s205, forming a ninth dielectric layer on the surface of the seventh metal layer in a spin coating mode, etching a seventh through hole, exposing a part of the seventh metal layer through the seventh through hole, and manufacturing an eighth metal layer serving as a bonding pad in the seventh through hole through metal plating and etching processes;

s206 the BUMP process takes the seventh metal layer as UBM, and copper columns, BUMP or implanted balls are electroplated on the seventh metal layer through an electroplating process.

In a preferred embodiment of the present invention, the method further includes step S207 of thinning the back surface of the substrate.

In a preferred embodiment of the present invention, the seventh dielectric layer, the eighth dielectric layer and the ninth dielectric layer are made of PI or BCB.

In a preferred embodiment of the present invention, the substrate is made of high-resistance silicon or glass.

In a preferred embodiment of the present invention, the sixth metal layer is located directly above the fourth metal layer, and the deviation does not exceed 10% of the minimum line width of the winding inductance of the sixth metal layer.

In a preferred embodiment of the present invention, the thickness of the fifth dielectric layer is 3-5 μm.

In a preferred embodiment of the present invention, the thickness of the seventh dielectric layer and the eighth dielectric layer is 5-10 μm.

Compared with the prior art, the invention has the beneficial effects that:

the invention combines the existing semiconductor integrated passive device process with the packaging RDL (RDL (redistribution layer) process, breaks through the limit of few layers of thick metal and limited metal thickness in the mature process of an integrated circuit, adds 1-3 layers of routable metal layers in combination with the RDL process, and can make the metal thickness thicker, thereby forming a richer laminated structure, thereby realizing the functions of layer-wound inductance and connection wiring, improving the design flexibility of the passive integrated device, and improving the performance and the integration level of the integrated passive device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a semiconductor device integrated with a passive device according to an embodiment of the present invention;

fig. 2 is a schematic view of a semiconductor device integrated with a passive device according to another embodiment of the present invention;

FIG. 3 is a process flow diagram of the S100 process of the present invention for an integrated passive device process utilizing a redistribution layer to enhance performance;

FIG. 4 is a process flow diagram of the S200 process of the present invention for an integrated passive device process utilizing a redistribution layer to enhance performance;

FIG. 5 is a schematic diagram of a conventional integrated passive device;

FIG. 6 is a schematic diagram of an integrated passive device fabricated using the integrated passive device process of the present invention utilizing a redistribution layer to enhance performance;

FIG. 7 is a graph of insertion loss in comparison with a solid line using the process of the present invention and a dashed line using an IPD process;

fig. 8 is a graph of band rejection comparison, where the solid line is the process using the present invention and the dashed line is the process using IPD.

Specifically, 100, a substrate;

200. an integrated passive device;

300. a rewiring layer;

211. a resistive layer;

221. a first dielectric layer; 222. a second dielectric layer; 223. a third dielectric layer; 224. a fourth dielectric layer; 225. a fifth dielectric layer; 327. a seventh dielectric layer; 328. an eighth dielectric layer; 329. a ninth dielectric layer;

231. a first through hole; 232. a second through hole; 233. a third through hole; 234. a fourth via hole; 335. a fifth through hole; 336. a sixth through hole; 337. a seventh via hole;

241. a first metal layer; 242. a second metal layer; 243. a third metal layer; 244. a fourth metal layer; 346. a sixth metal layer; 347. a seventh metal layer; 348. an eighth metal layer;

361、BUMP。

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit indication of the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

Example 1: as shown in fig. 1, a semiconductor apparatus of an integrated passive device includes:

substrate 100, substrate 100 may be high resistance silicon or glass, but is not limited thereto.

At least one integrated passive device 200 comprising one or more of a resistor, a capacitor, or an inductor formed on a surface of the substrate 100.

A redistribution layer 300 disposed on a surface of the substrate 100 on which the at least one integrated passive device 200 is disposed, wherein the redistribution layer 300 includes at least one metal layer to form a layer wound inductor, it being understood that to form the layer wound inductor, the metal layer is in a horizontal winding spiral shape, such as in fig. 7.

As shown in fig. 1 and 2, the redistribution layer 300 may use wire bonding, ball mounting, or BUMP processes to extract signals.

Preferably, the integrated passive device 200 includes an inductor, the metal layer of the redistribution layer 300 is located directly above the inductor, the integrated passive device 200 and the redistribution layer 300 need to be aligned at upper and lower positions, and a process alignment error does not exceed 10% of a minimum line width of the inductor wound by the sixth metal layer 346 of the redistribution layer 300, so as to reduce an influence on device performance uniformity. Further, the thickness of the dielectric layer closest to the redistribution layer 300 of the integrated passive device 200 is 3-5 μm.

As shown in fig. 1 and fig. 2, specifically, the device sequentially includes, from bottom to top, a substrate 100, a resistive layer 211, a first dielectric layer 221, a first metal layer 241, a second dielectric layer 222, a second metal layer 242, a third dielectric layer 223, a third metal layer 243, a fourth dielectric layer 224, a fourth metal layer 244, a fifth dielectric layer 225, a seventh dielectric layer 327, a sixth metal layer 346, an eighth dielectric layer 328, a seventh metal layer 347, and a BUMP361 or a ninth dielectric layer 329, an eighth metal layer 348 disposed on the seventh metal layer 347.

The first metal layer 241 is connected to the substrate 100 and the resistor through a first via 231 disposed on the first dielectric layer 221, the third metal layer 243 is connected to the second metal layer 242 through a second via 232 disposed on the third dielectric layer 223, the fourth metal layer 244 is connected to the third metal layer 243 through a third via 233 disposed on the fourth dielectric layer 224, the sixth metal layer 346 is connected to the fourth metal layer 244 through a fifth via 335 and a fourth via 234 disposed on the seventh dielectric layer 327, the seventh metal layer 347 is connected to the sixth metal layer 346 through a sixth via 336 disposed on the eighth dielectric layer 328, the eighth metal layer 348 is connected to the seventh metal layer 347 through a seventh via 337 disposed on the ninth dielectric layer 329, and the eighth metal layer 348 is disposed in the seventh via 337.

Example 2:

first, a brief description will be given of a part of the processes used.

And (3) photoetching process: the photoetching is a process technology which transfers a circuit pattern to the surface of a dielectric layer by utilizing an optical-chemical reaction principle and chemical and physical etching methods to form an effective pattern window or a functional pattern.

The sputtering process is one kind of physical vapor deposition. Ar ions are accelerated to fly to a cathode target under the action of an electric field and bombard the surface of the target at high energy, so that atoms or molecules near the surface of the solid obtain enough energy and finally escape from the surface of the solid, and the target is sputtered. In the sputtered particles, neutral target atoms or molecules are deposited on the substrate to form a thin film.

The electroplating process comprises the following steps: copper electroplating is the process of plating a layer of copper on some solid surfaces using the principle of electrolysis. The anode and the cathode of the metal lead power supply are interconnected with the anode and the cathode of the plating bath to form an electric field between the two electrodes. Under the action of the electric field, cations flow to the cathode, anions flow to the anode, and the cations are deposited on the surface of the cathode to form a coating. Generally, before electroplating, a seed layer is sputtered on the surface of the substrate 100 to facilitate current loading of the electroplating electrode. Firstly, sputtering a seed layer Ti/Cu on the surface of a wafer, carrying out thick resist photoetching to serve as an electroplating mold, electroplating copper to form a copper wire, removing the photoresist, and corroding the seed layer to obtain the copper wiring.

An integrated passive device process for enhancing performance using a redistribution layer 300, comprising:

s100 forms at least one integrated passive device 200 on a substrate 100.

In the process, a substrate 100 wafer of high-resistance silicon, glass or the like is subjected to surface treatment. The integrated passive device 200 includes one or more of a resistor, a capacitor, or an inductor formed on the surface of the substrate 100.

S200 forms a redistribution layer 300 on the surface of the substrate 100 on which the integrated passive device 200 is formed.

The redistribution layer 300 includes at least one metal layer to form a layer-wound inductor. It will be appreciated that to form a layer wound inductor, the metal layer is in the form of a horizontal winding spiral, such as in fig. 5 and 6.

The redistribution layer 300 may use wire bonding, ball mounting, or BUMP processes to extract signals.

The integrated passive device 200 includes an inductor, the metal layer of the redistribution layer 300 is located directly above the inductor, and the deviation does not exceed 10% of the minimum line width of the sixth metal layer 346 of the redistribution layer 300 wound around the inductor.

As shown in fig. 3, preferably, S100 forms at least one integrated passive device 200 on the substrate 100, including:

s101 forms a resistive layer 211 on the substrate 100 by metal sputtering, photolithography, and ion etching processes, and deposits a first dielectric layer 221 thereon.

Specifically, the resistive target material is bombarded with ions by a metal sputtering process, so that the resistive material uniformly drops and is densely deposited on the surface of the substrate 100. The pattern of the resistive layer 211 is transferred to the surface of the wafer by a photolithography process, the resistive layer 211 is etched by an ion etching method, and an oxide dielectric layer is deposited thereon to form a first dielectric layer 221.

S102, a first through hole 231 is etched on the first dielectric layer 221 by photolithography and etching processes, wherein the first through hole 231 exposes a portion of the substrate 100 and a portion of the resistive layer 211, i.e., the first through hole 231 of the resistor and the first metal layer 241 is etched.

S103, depositing a first metal layer 241 on the first dielectric layer 221, connecting the first metal layer 241 with the substrate 100 and the resistor layer 211 through the first through hole 231, etching the first metal layer 241 pattern as a capacitor bottom plate through the photoetching and etching process, and depositing a second dielectric layer 222 on the surface of the first metal layer 241 as a capacitor dielectric layer.

Specifically, thin metal is deposited on the surface of the wafer, a metal layer pattern is etched through a photolithography process and an etching process to be used as a bottom plate of the capacitor, i.e., the first metal layer 241, and a dense dielectric layer is deposited on the surface of the metal to be used as a dielectric layer of the capacitor, i.e., the second dielectric layer 222.

S104, depositing a second metal layer 242 on the second dielectric layer 222, etching the second metal layer 242 pattern as the upper bottom plate of the capacitor by photoetching and etching processes, and depositing a third dielectric layer 223 thereon.

Specifically, a thin metal layer is deposited on the wafer surface, a metal layer pattern is etched through a photolithography process and an etching process to serve as an upper bottom plate of the capacitor, i.e., a second metal layer 242 is formed, and a thicker dielectric layer is deposited thereon to form the third dielectric layer 223.

S105, etching a second via 232 on the third dielectric layer 223 by photolithography and etching processes, wherein the second via 232 exposes a portion of the second metal layer 242, and continuously etching a third metal layer 243 pattern thereon by photolithography and etching processes.

Specifically, the second via hole 232 of the second metal layer 242-the third metal layer 243 is etched on the third dielectric layer 223 through the photolithography process and the etching process, and the third metal layer 243 pattern is continuously etched thereon through the photolithography process and the etching process.

S106, a second through hole 232 and a third metal layer 243 seed layer are sputtered through a metal sputtering process, the second through hole 232 and the third metal layer 243 are completed through an electroplating process, finally, the surface of the wafer is flattened through chemical mechanical polishing, and a fourth dielectric layer 224 is deposited on the wafer.

Specifically, the second via hole 232 and the third metal layer 243 are sputtered by a metal sputtering process, the second via hole 232 and the third metal layer 243 are completed together by an electroplating process, finally, the wafer surface is planarized by CMP (chemical mechanical polishing), and a thicker dielectric layer is deposited thereon as the fourth dielectric layer 224.

S107, repeating S105-S106, completing the manufacture of the third through hole 233 and the fourth metal layer 244, depositing a fifth dielectric layer 225 on the surface of the fourth metal layer 244, and etching a fourth through hole 234 thereon.

Specifically, S105-S106 are repeated to complete the fabrication of the third via 233 and the fourth metal layer 244 of the third metal layer 243-the fourth metal layer 244, a dense dielectric layer is deposited on the surface of the fourth metal layer 244 to serve as the fifth dielectric layer 225, and the fourth via 234 is etched on the dense dielectric layer.

Through the above steps, a passive integrated circuit device (IPD) including high precision resistors, capacitors, and inductors can be manufactured.

As shown in fig. 4, preferably, S200 forms a redistribution layer 300 on the surface of the substrate 100 where the integrated passive device 200 is formed, including the following steps. For clarity, the substrate 100 is used to replace a product before the previous step S107, and it should be noted that the fifth dielectric layer 225 in the IPD step S107 needs to be correspondingly improved, specifically, the thickness of the fifth dielectric layer 225 is increased from less than 1 μm to 3 μm to 5 μm, and an error is strictly controlled, where the error is less than 10% of the thickness of the fifth dielectric layer, so as to reduce the influence on the performance uniformity. It is understood that the present process continues to manufacture after the thickness of the fifth dielectric layer 225 on the chip surface is improved based on the previous process S107. The thickness of the fifth dielectric layer 225 on the surface of the chip is improved to be beneficial to: a thicker surface dielectric layer may protect the surface of the early completed integrated passive device S100 wafer. The method has the advantages that when the integrated circuit process IPD and the packaging rewiring RDL process are switched, a circuit manufactured in the S100 process on the surface of the wafer is prevented from being damaged; second, the thickness of the fifth dielectric layer 225 is increased, and the thickness of the dielectric between the fourth metal layer 244 and the sixth metal layer 346 is increased by matching with the seventh dielectric layer 327, so as to control the parasitic coupling between metals.

S201, a seventh dielectric layer 327 is formed on the fifth dielectric layer 225 by spin coating, and a fifth via 335 is etched at a position corresponding to the fourth via 234 by photolithography.

S202, metal plating is performed on the seventh dielectric layer 327 to form a thicker metal layer, and the sixth metal layer 346 is fabricated by the processes of illumination, development, and etching, and the sixth metal layer 346 is connected to the fourth metal layer 244 through the fifth via 335 and the fourth via 234.

S203 spin-coating the surface of the sixth metal layer 346 to form an eighth dielectric layer 328, and etching a sixth via 336 at a position corresponding to the fourth via 234 by photolithography.

S204 repeats S202, and a seventh metal layer 347 is formed, the bonding process goes to S205, and the ball mounting process goes to S206.

S205 spin-coating a ninth dielectric layer 329 on the surface of the seventh metal layer 347 to form a seventh via 337, wherein the seventh via 337 exposes a portion of the seventh metal layer 347, and fabricating an eighth metal layer 348 as a pad in the seventh via 337 through metal plating and etching processes.

S206BUMP361 processes the seventh metal layer 347 as a UBM (Under BUMP361metal layer), and a copper pillar, a BUMP361 or an implanted ball is plated on the seventh metal layer 347 through a plating process.

Preferably, S207 is further included to thin the back side of the substrate 100. Thinning the substrate 100 after all the processes is completed can reduce the size of the finished device while preventing the wafer from being broken due to excessive thinning during processing.

Further preferably, the seventh dielectric layer 327, the eighth dielectric layer 328, and the ninth dielectric layer 329 are made of PI (polyimide) or BCB (benzocyclobutene).

It is further preferred that the sixth metal layer 346 be aligned with the fourth metal layer 244 with no deviation in alignment accuracy exceeding 10% of the line width of the sixth metal layer 346. The alignment error will affect the inductance accuracy of the inductor wound with the combined RDL sixth metal layer 346, IPD third metal layer 243, and IPD fourth metal layer 244.

The thickness of the sixth metal layer 346 is preferably greater than 3 μm.

In the conventional RDL process, PAD locations are usually re-arranged and then ball-mounted in the WLCSP package, which mainly plays a role in newly allocating PAD locations. In the conventional RDL process, the seventh dielectric layer 327 and the eighth dielectric layer 328 play roles in isolating metal and buffering stress, and the thickness control precision grade can be obtained for several times. The process needs to accurately control the thicknesses of the seventh dielectric layer 327 and the eighth dielectric layer 328, the thicknesses of the seventh dielectric layer 327 and the eighth dielectric layer 328 are 5-10 μm, the error is controlled to be less than 10% of the thickness of the dielectric, and the performance consistency is affected by overlarge error. The thicknesses of the seventh dielectric layer 327 and the eighth dielectric layer 328 are parameters adjusted during device design, and may have an influence on device performance. The process utilizes the RDL process to increase the number of thick metal layers in the traditional integrated circuit process, can wind inductors with more turns, has smaller inductor area with the same inductance value, reduces the area and improves the integration level of devices. Meanwhile, the process utilizes the fact that a metal layer in the RDL process can be thicker, the photoetching and metal deposition accuracy is poor compared with the chip process, good metal connection loss can be obtained at low cost, and the performance of an integrated passive device is improved.

Compared with the conventional integrated passive device process (IPD), the process for preparing a low-pass filter has the advantages that fig. 5 is a schematic diagram of the conventional integrated passive device prepared by the IPD process, and fig. 6 is a schematic diagram of the integrated passive device prepared by the process. As shown in fig. 7 and 8, the insertion loss performance of the pass filter is improved by > 10% and the suppression performance is improved by > 10% by the process.

In conclusion, the invention combines the existing semiconductor integrated passive device process with the packaging RDL (RDL) process, breaks through the limitation of few thick metal layers (1-2 layers) and metal thickness in the mature process of the integrated circuit, adds 1-3 layers of routable metal layers in combination with the RDL process, and forms richer laminated structures, thereby realizing the functions of winding low-loss and high inductance per unit area and connecting and routing, improving the design flexibility of the passive integrated device, and improving the performance and the integration level of the integrated passive device.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A semiconductor device integrating passive devices, comprising:

substrate;

at least one integrated passive device comprising one or more of a resistor, capacitor or inductor formed on the surface of the substrate;

a redistribution layer disposed on the surface of the substrate on which the at least one integrated passive device is disposed;

Wherein, the redistribution layer includes at least one metal layer to form a layer wound inductor.

2 . The semiconductor device integrating passive devices according to claim 1 , wherein the substrate is high-resistance silicon or glass. 3 .

3 . The semiconductor device integrating passive devices according to claim 1 , wherein the redistribution layer adopts wire bonding, ball mounting or BUMP process to lead out signals. 4 .

4 . The semiconductor device integrating passive devices according to claim 1 , wherein the integrated passive device comprises an inductor, and the metal layer of the redistribution layer is located directly above the inductor, and the offset is 4 . No more than 10% of the minimum line width of the metal layer winding inductance.

5. an integrated passive device technology utilizing rewiring layer enhancement performance, is characterized in that, comprises:

S100 forming at least one integrated passive device on the substrate;

S200 forms a redistribution layer on the surface of the substrate to form the integrated passive device;

6 . The integrated passive device process using a redistribution layer to enhance performance according to claim 5 , wherein the substrate is made of high-resistance silicon or glass. 7 .

7. The integrated passive device process utilizing a redistribution layer to enhance performance according to claim 5, wherein the S100 forms at least one integrated passive device on the substrate, comprising:

S101 forms a resistance layer on the substrate through metal sputtering, photolithography, and ion etching processes, and deposits a first dielectric layer thereon;

S102, a first through hole is etched on the first dielectric layer through a photolithography and etching process, wherein the first through hole exposes part of the substrate and part of the resistance layer;

S103 Deposit a first metal layer on the first dielectric layer, and the first metal layer is connected to the substrate and the resistance layer through a first through hole, and a pattern of the first metal layer is etched as a capacitor through a photolithography and etching process lower bottom plate, and deposit a second dielectric layer on the surface of the first metal layer as the dielectric layer of the capacitor;

S104 depositing a second metal layer on the second dielectric layer, etching the second metal layer pattern as a capacitor upper bottom plate by photolithography and an etching process, and depositing a third dielectric layer thereon;

S105, a second through hole is etched on the third dielectric layer through photolithography and etching process, wherein the second through hole exposes part of the second metal layer, and continues to be etched on it through photolithography and etching process Etch out the third metal layer pattern;

S106 sputter the second through hole and the third metal layer seed layer through a metal sputtering process, complete the second through hole and the third metal layer together through an electroplating process, and finally complete the surface of the wafer through chemical mechanical polishing depositing a fourth dielectric layer;

S107 Repeat S105-S106 to complete the fabrication of the third through hole and the fourth metal layer, deposit a fifth dielectric layer on the surface of the fourth metal layer, and etch the fourth through hole on the fifth dielectric layer through photolithography and etching processes hole.

8. The integrated passive device process utilizing a redistribution layer to enhance performance according to claim 7, wherein the S200 forms a redistribution layer on the surface of the substrate on which the integrated passive device is formed, comprising:

S201, a seventh dielectric layer is formed on the fifth dielectric layer by spin coating, and a fifth through hole is etched at the corresponding position of the fourth through hole by photolithography;

S202, metal plating is performed on the seventh dielectric layer to form a thicker metal layer, and the sixth metal layer is fabricated through the processes of illumination, development and etching, and the sixth metal layer passes through the fifth through hole, the fourth through hole and the fourth through hole. metal layer connection;

S203 spin-coating the surface of the sixth metal layer to form the eighth dielectric layer, and etching the sixth through hole at the corresponding position of the fourth through hole by photolithography;

S204 repeats S202 to form the seventh metal layer, the bonding process goes to S205, and the ball-mounting process goes to S206;

S205 Spin coating the surface of the seventh metal layer to form a ninth dielectric layer, and etch a seventh through hole, wherein the seventh through hole exposes part of the seventh metal layer, and the metal plating and etching process is performed in the seventh through hole Make the eighth metal layer as the pad;

The seventh metal layer of the S206BUMP process is used as a UBM, and copper pillars, BUMPs or implanted balls are electroplated on the seventh metal layer through an electroplating process.

9 . The integrated passive device process using a redistribution layer to enhance performance according to claim 8 , wherein the material of the seventh dielectric layer, the eighth dielectric layer and the ninth dielectric layer is PI or BCB. 10 .

10 . The integrated passive device process using a redistribution layer to enhance performance according to claim 8 , wherein the sixth metal layer is located directly above the fourth metal layer, and the deviation does not exceed the sixth metal layer. 11 . The metal layer is wound with 10% of the minimum line width of the inductor.