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CN112768438B - A crimping type power module and preparation method thereof - Google Patents

A crimping type power module and preparation method thereof Download PDF

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CN112768438B
CN112768438B CN201911068924.4A CN201911068924A CN112768438B CN 112768438 B CN112768438 B CN 112768438B CN 201911068924 A CN201911068924 A CN 201911068924A CN 112768438 B CN112768438 B CN 112768438B
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power module
signal transmission
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layer
chip
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CN112768438A (en
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敖日格力
刘洋
叶怀宇
张国旗
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Nayu Semiconductor Materials Ningbo Co ltd
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Shenzhen Third Generation Semiconductor Research Institute
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Priority to PCT/CN2019/123833 priority patent/WO2021088186A1/en
Priority to PCT/CN2020/103123 priority patent/WO2021088414A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/071Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

A compression-bonded power module comprising: the power module layer comprises a first power module layer and a second power module layer which are arranged from top to bottom; the second power module layer comprises a substrate and n x m bosses arranged on the substrate, and each boss is provided with a subunit chip; the second power module layer further comprises n signal transmission strips for connecting the grid electrodes of the sub-unit chips in each row, the signal transmission strips comprise m layers of stacked and integrated signal transmission sub-strips, and each signal transmission sub-strip is used for transmitting a signal of one sub-unit chip; n >1, m > 1. The invention solves the technical problem that the sub-unit chip in the traditional crimping type power module is difficult to independently remove the fault, and can realize independent control and detection of the sub-unit chip in the power module.

Description

一种压接式功率模块及其制备方法A crimping type power module and preparation method thereof

技术领域technical field

半导体领域,具体涉及电力电子器件的制备The field of semiconductors, specifically the preparation of power electronic devices

背景技术Background technique

本发明设计一种基于多层PCB板便于检测的压接式器件,这种器件可以方便的测试出压接式器件的失效子单元芯片的位置。The invention designs a pressure-bonding device based on a multi-layer PCB board that is convenient for detection, and the device can conveniently test the position of a failed subunit chip of the pressure-bonding device.

在传统的焊接式IGBT内部,线路的杂散参数较大,关断的过程中会产生很大的电压尖峰并伴随着一定的电磁干扰。当电力系统对功率等级提出更高的要求,需要更多的芯片并联时,将进一步增大芯片栅极、发射极、集电极的寄生参数及其差异性,加剧了电压过冲、增大了开关损耗,并导致电流极大的不均衡,从而降低了器件的可靠性。相比于焊接式IGBT,压接式具有高电压、大电流、杂散电感低、开关速度快、可双面散热等优势,因此压接式IGBT已经成为高压直流输电中半导体器件的主流选择。In the traditional welded IGBT, the stray parameters of the line are large, and a large voltage spike will be generated during the turn-off process, accompanied by certain electromagnetic interference. When the power system puts forward higher requirements on the power level and requires more chips to be connected in parallel, the parasitic parameters and their differences of the gate, emitter and collector of the chip will be further increased, which will aggravate the voltage overshoot and increase the switching losses and lead to a large current imbalance, which reduces the reliability of the device. Compared with welded IGBTs, crimped IGBTs have the advantages of high voltage, high current, low stray inductance, fast switching speed, and double-sided heat dissipation. Therefore, crimped IGBTs have become the mainstream choice for semiconductor devices in HVDC transmission.

而压接式IGBT由于是通过压力将各个子单元芯片并联压接在一起,在使用过程中多发生短路失效,然而传统由于器件是所有芯片一起并联,一旦内部有芯片短路就会导致整个器件的失效。而传统的压接型器件在排除失效芯片时非常困难,需要将各个芯片单独取出进行晶圆级测试,整个测试过程非常繁琐。The crimp-type IGBT, because the sub-unit chips are crimped together in parallel by pressure, is often short-circuited during use. However, traditionally, because all the chips are connected in parallel, once there is a short circuit inside the chip, the entire device will be short-circuited. invalid. However, it is very difficult for traditional press-bonded devices to eliminate failed chips, and each chip needs to be taken out for wafer-level testing. The entire testing process is very cumbersome.

发明内容SUMMARY OF THE INVENTION

为克服现有技术的不足,解决压接式功率模块内部子单元芯片难以单独排除故障的技术问题,本发明可实现功率模块内部可单独控制和检测的压接式功率模块结构及其制备方法。In order to overcome the deficiencies of the prior art and solve the technical problem that the subunit chips inside the crimped power module are difficult to troubleshoot individually, the present invention can realize the crimped power module structure and its preparation method which can be independently controlled and detected inside the power module.

一种压接式功率模块,包括:堆叠设置的至少一层功率模块层,所述功率模块层包括由上至下设置的第一功率模块层,及第二功率模块层;A crimping type power module, comprising: at least one power module layer arranged in a stack, the power module layer comprising a first power module layer and a second power module layer arranged from top to bottom;

所述第二功率模块层包括基板,及设置在基板上n*m个凸台,每个所述凸台上设置一个子单元芯片;所述第二功率模块层还包括n个用于连接每行子单元芯片栅极的信号传输条,所述信号传输条包括m层堆叠集成的信号传输子条,每个信号传输子条用于传输一个子单元芯片的信号;n>1,m>1。The second power module layer includes a substrate, and n*m bosses arranged on the substrate, each of the bosses is provided with a sub-unit chip; the second power module layer also includes n for connecting each A signal transmission bar for the gate of a row sub-unit chip, the signal transmission bar includes m-layer stacked and integrated signal transmission sub-strips, each signal transmission sub-strip is used to transmit the signal of one sub-unit chip; n>1, m>1 .

优选的,所述m层堆叠集成的信号传输子条宽度相等,每层集成的信号传输子条的长度根据子单元芯片位置由上至下依次递减。Preferably, the signal transmission sub-strips integrated in the m-layer stack have equal widths, and the lengths of the signal transmission sub-strips integrated in each layer decrease sequentially from top to bottom according to the position of the sub-unit chips.

优选的,所述m层堆叠集成的信号传输子条包括顶针,所述顶针与子单元芯片连接;所述m层堆叠集成的信号传输子条之间采用绝缘材料连接。Preferably, the m-layer stacked and integrated signal transmission sub-strip includes a thimble, and the thimble is connected to the subunit chip; the m-layer stacked and integrated signal transmission sub-strip is connected by an insulating material.

优选的,所述第一功率模块层包括金属端盖上层及金属端盖下层,所述金属端盖下层包括绝缘外框及及与子单元芯片对应设置的n*m个金属块。Preferably, the first power module layer includes an upper layer of metal end caps and a lower layer of metal end caps, and the lower layer of metal end caps includes an insulating outer frame and n*m metal blocks corresponding to the subunit chips.

优选的,所述子单元芯片包括功率芯片及FRD芯片,所述功率芯片包括MOSFET芯片或IGBT芯片;所述绝缘材料为有机硅胶,酚醛树脂胶,脲醛树脂胶,耐温环氧胶,聚酰亚胺胶中的一种或多种组合。Preferably, the sub-unit chips include power chips and FRD chips, and the power chips include MOSFET chips or IGBT chips; the insulating materials are organic silica gel, phenolic resin glue, urea-formaldehyde resin glue, temperature-resistant epoxy glue, polyamide One or more combinations of imide gums.

一种压接式功率模块的制备方法,包括:A preparation method of a crimped power module, comprising:

S1:制备m层堆叠集成的信号传输子条,第一功率模块层;m>1;S1: prepare an m-layer stack-integrated signal transmission sub-strip, the first power module layer; m>1;

S2:采用n个所述m层堆叠集成的信号传输子条制备第二功率模块层;所述第二功率模块层包括基板,及设置在基板上n*m个凸台,每个所述凸台上设置一个子单元芯片;所述信号传输条包括m层堆叠集成的信号传输子条,每个信号传输子条用于传输一个子单元芯片的信号;n>1;S2: prepare a second power module layer by using n of the m-layer stacked and integrated signal transmission sub-strips; the second power module layer includes a substrate, and n*m bosses disposed on the substrate, each of the projections A sub-unit chip is arranged on the stage; the signal transmission strip includes m-layer stacked and integrated signal transmission sub-strips, and each signal transmission sub-strip is used to transmit the signal of one sub-unit chip; n>1;

S3:将第一功率模块层放置于第二功率模块层顶部,压接制备功率模块层;S3: placing the first power module layer on top of the second power module layer, and crimping to prepare the power module layer;

S4:垂直放置将至少一个所述功率模块层,压接形成功率模块。S4: Place at least one of the power module layers vertically and crimp to form a power module.

优选的,所述S1制备m层堆叠集成的信号传输子条包括:Preferably, the S1 preparation of the m-layer stacked integrated signal transmission sub-strip includes:

S1.1:在印制电路板上裁剪获得n个长度为xi的信号传输子条,1<i<m;S1.1: Cut out n signal transmission sub-strips of length xi on the printed circuit board, 1<i<m;

S1.2:选择长度为xi的m个信号传输子条,根据长度由短到长的顺序叠置并采用绝缘材料粘接,1<i<m,形成m层堆叠集成的信号传输子条。S1.2: Select m signal transmission sub-strips with a length of xi, stack them according to the order of length from short to long, and use insulating materials to bond, 1<i<m, to form m-layer stacked and integrated signal transmission sub-strips.

优选的,所述粘接时,预先在信号传输子条上留出与顶针接触位置不进行粘接,所述顶针接触位置根据子单元芯片栅极信号连接处确定。Preferably, during the bonding, a contact position with the ejector pin is reserved on the signal transmission sub-strip beforehand for bonding, and the ejector pin contact position is determined according to the gate signal connection position of the subunit chip.

优选的,所述第一功率模块层包括金属端盖上层及金属端盖下层,所述金属端盖下层包括绝缘外框及及与子单元芯片对应设置的n*m个金属块。Preferably, the first power module layer includes an upper layer of metal end caps and a lower layer of metal end caps, and the lower layer of metal end caps includes an insulating outer frame and n*m metal blocks corresponding to the subunit chips.

优选的,所述子单元芯片包括功率芯片及FRD芯片,所述功率芯片包括MOSFET芯片或IGBT芯片;所述绝缘材料为有机硅胶,酚醛树脂胶,脲醛树脂胶,耐温环氧胶,聚酰亚胺胶中的一种或多种组合。Preferably, the sub-unit chips include power chips and FRD chips, and the power chips include MOSFET chips or IGBT chips; the insulating material is organic silica gel, phenolic resin glue, urea-formaldehyde resin glue, temperature-resistant epoxy glue, polyamide One or more combinations of imide gums.

本发明提出改变传统安装方法,将上端盖分离成两层,底下一层用单独的铜块嵌入FR4板中与各个芯片的栅极相连,上层依旧用铜端盖盖住。栅极引出使用多层信号传输条,在外接测试端各层板的覆铜面依次漏出,这种特殊的信号传输条可以实现器件内指定芯片的驱动。在器件发生故障时,将上端盖的上层铜板去除,单独驱动单一器件的栅极,并且联通该芯片的CE端,可以达到检测单个芯片的效果。The invention proposes to change the traditional installation method, separate the upper end cap into two layers, the lower layer is embedded with a separate copper block in the FR4 board and connected to the gates of each chip, and the upper layer is still covered with copper end caps. Multi-layer signal transmission strips are used for gate lead-out, and the copper-clad surfaces of each layer of the external test end leak out in sequence. This special signal transmission strip can realize the driving of designated chips in the device. When the device fails, the upper copper plate of the upper end cap is removed, the gate of a single device is driven independently, and the CE terminal of the chip is connected to achieve the effect of detecting a single chip.

附图说明Description of drawings

图1为实施例一提供的堆叠型压接式功率模块的示意图FIG. 1 is a schematic diagram of a stacked crimp power module provided in Embodiment 1

图2为实施例一提供的堆叠型压接式功率模块的俯视图FIG. 2 is a top view of the stacked crimp power module provided in the first embodiment

图3为实施例一提供的拆掉端盖的堆叠型压接式功率模块俯视图FIG. 3 is a top view of the stacked crimping type power module with the end cover removed according to the first embodiment

图4为实施例一提供的多层信号传输条的示意图FIG. 4 is a schematic diagram of a multi-layer signal transmission strip provided in Embodiment 1

图5为实施例一提供的制备多层信号传输条的一层示意图FIG. 5 is a schematic diagram of one layer of preparing a multi-layer signal transmission strip provided in Embodiment 1

图6为实施例一提供的制备多层信号传输条的二层示意图FIG. 6 is a schematic diagram of a second layer for preparing a multi-layer signal transmission strip provided in Embodiment 1

图7为实施例一提供的制备多层信号传输条的三层示意图FIG. 7 is a three-layer schematic diagram of preparing a multi-layer signal transmission strip according to Embodiment 1

图8为实施例一提供的制备多层信号传输条的五层示意图FIG. 8 is a five-layer schematic diagram of preparing a multi-layer signal transmission strip provided in Embodiment 1

具体实施方式Detailed ways

下面详细说明本发明的具体实施,有必要在此指出的是,以下实施只是用于本发明的进一步说明,不能理解为对本发明保护范围的限制,该领域技术熟练人员根据上述本发明内容对本发明做出的一些非本质的改进和调整,仍然属于本发明的保护范围。The specific implementation of the present invention will be described in detail below. It is necessary to point out that the following implementation is only used for further description of the present invention, and should not be construed as a limitation on the protection scope of the present invention. Some non-essential improvements and adjustments made still belong to the protection scope of the present invention.

实施例一Example 1

本实施例提供一种堆叠型压接式功率模块及其制造方法,如图1-8所示。This embodiment provides a stacked crimp power module and a manufacturing method thereof, as shown in FIGS. 1-8 .

如图1-2所示,本实施例提供的一种堆叠型压接式功率模块,其包括自上而下依次设置的芯片、FR4板、铜块、铜板,将上端盖分离成两层;底下一层用单独的铜块嵌入FR4板中与各个芯片的C级相连,且端盖上套有绝缘外框,铜板作为端盖置于顶层;栅极的引出使用多层PCB板,在外接测试端各层PCB板的覆铜面依次漏出,这种特殊的PCB板可以实现器件内指定芯片的驱动。As shown in Figure 1-2, a stacked crimping power module provided by this embodiment includes a chip, an FR4 board, a copper block, and a copper plate arranged in sequence from top to bottom, and the upper end cover is separated into two layers; The bottom layer is embedded with a separate copper block into the FR4 board and connected to the C-level of each chip, and the end cover is covered with an insulating outer frame, and the copper plate is placed on the top layer as the end cover; the gate is drawn out using a multi-layer PCB board. The copper clad surface of each layer of the PCB board at the test end leaks out in turn. This special PCB board can realize the driving of the designated chip in the device.

如图3所示,是本实施例提供的多层信号传输条,将单个PCB按需求裁剪,把多个PCB错开粘接,粘接时把与芯片栅极信号相连处和最外侧引出部分漏出不粘接,便于顶针接触也避免后续的打磨工序。胶水可使用有机硅类胶、酚醛树脂胶、脲醛树脂胶、耐温环氧胶、聚酰亚胺胶等,所需层数,可按照压接式功率芯片的列或行的子单元芯片数量确定。As shown in Figure 3, it is the multi-layer signal transmission strip provided in this embodiment. A single PCB is cut according to the requirements, and multiple PCBs are staggered and bonded. When bonding, the part connected to the gate signal of the chip and the outermost lead-out part are leaked out. It is not bonded, which is convenient for thimble contact and avoids the subsequent grinding process. The glue can use silicone glue, phenolic resin glue, urea-formaldehyde resin glue, temperature-resistant epoxy glue, polyimide glue, etc. The required number of layers can be based on the number of sub-unit chips in the column or row of the crimp power chip. Sure.

在器件发生故障时,需要单独控制各个子单元芯片,进行维护测试等时,将上端盖的上层铜板去除,如图3所示,单独驱动单一器件的栅极,并且联通该芯片的CE端,可以达到检测单个芯片的效果。When the device fails, it is necessary to individually control each sub-unit chip, and when performing maintenance tests, etc., remove the upper copper plate of the upper end cap, as shown in Figure 3, drive the gate of a single device separately, and connect the CE end of the chip, The effect of detecting a single chip can be achieved.

一种压接式功率模块制造方法,如图5-8所示,包括:A method for manufacturing a crimped power module, as shown in Figure 5-8, includes:

第一步,制作多层信号传输条;根据每行五个子单元芯片到功率模块外边沿的距离,在PCB上裁剪五个与距离一一对应的长度的单条。若每行子单元芯片数量为其他数量,或每一个信号传输条用于传输每列的子单元芯片的信号,则PCB单条的数量根据压接式功率芯片的每列或行的子单元芯片数量确定。如图5所示为制备的单层的PCB。通过胶水将PCB错开粘接,粘接时把与芯片栅极信号相连处和最外侧引出部分漏出,便于顶针接触。如图6所示为粘接的两层不同长度PCB单条的信号传输条,如图7所示为粘接的三层不同长度PCB单条的信号传输条,如图8所示为粘接的五层不同长度PCB单条的信号传输条。The first step is to make a multi-layer signal transmission strip; according to the distance from the five subunit chips in each row to the outer edge of the power module, cut five single strips with a length corresponding to the distance one-to-one on the PCB. If the number of sub-unit chips in each row is another number, or each signal transmission bar is used to transmit the signals of sub-unit chips in each column, the number of single PCB bars is based on the number of sub-unit chips in each column or row of the press-fit power chip. Sure. Figure 5 shows the prepared single-layer PCB. The PCB is staggered and bonded by glue, and the part connected to the gate signal of the chip and the outermost lead-out part are leaked out during bonding, so as to facilitate the contact of the thimble. As shown in Figure 6, the signal transmission strips of two layers of different lengths of PCB are bonded, as shown in Figure 7, the signal transmission strips of three layers of PCBs of different lengths are glued, as shown in Figure 8, the five glued signal transmission strips Signal transmission strips for single PCB strips of different lengths.

第二步,按结构特征制作两层端盖,底下一层用单独的铜块嵌入FR4板中与各个芯片的C级相连,铜板作为端盖置于顶层;所述端盖套有绝缘体外壳;端盖的上层铜板可拆卸,在器件发生故障时,将端盖的上层铜板去除,单独驱动单一器件的栅极,并且联通该芯片的CE端,可以达到检测单个芯片的效果。In the second step, two layers of end caps are made according to the structural characteristics, and the bottom layer is embedded with a separate copper block in the FR4 board and connected to the C-level of each chip, and the copper plate is placed on the top layer as an end cap; the end cap is covered with an insulator shell; The upper copper plate of the end cap is detachable. When the device fails, the upper copper plate of the end cap is removed, the gate of a single device is driven independently, and the CE end of the chip is connected to achieve the effect of detecting a single chip.

第三步,完成所有子单元芯片的并联后压接形成功率模块并封装。可选的,可制备多个所述功率模块,垂直压接形成堆叠式压接功率模块。In the third step, after completing the parallel connection of all the subunit chips, a power module is formed and packaged by crimping. Optionally, a plurality of the power modules may be prepared and vertically crimped to form stacked crimped power modules.

本方法制备简单,仅在常规的压接式功率模块的制备方法的基础上增设采用PCB基板切割获得的多层信号传输条步骤,即可实现采用上述压接式功率模块制造方法可制造易于单独检测短路失效的模块,可驱动压接式IGBT器件中的指定子单元芯片,当器件失效时,可便捷地检测失效子单元芯片。The method is simple to prepare, and only adding the step of adopting a multi-layer signal transmission strip obtained by cutting a PCB substrate to the conventional method for preparing a crimping type power module can realize that the above-mentioned manufacturing method of a crimping type power module can be easily manufactured separately. The module for detecting short-circuit failure can drive the specified sub-unit chip in the press-fit IGBT device, and when the device fails, the failed sub-unit chip can be easily detected.

尽管为了说明的目的,已描述了本发明的示例性实施方式,但是本领域的技术人员将理解,不脱离所附权利要求中公开的发明的范围和精神的情况下,可以在形式和细节上进行各种修改、添加和替换等的改变,而所有这些改变都应属于本发明所附权利要求的保护范围,并且本发明要求保护的产品各个部门和方法中的各个步骤,可以以任意组合的形式组合在一起。因此,对本发明中所公开的实施方式的描述并非为了限制本发明的范围,而是用于描述本发明。相应地,本发明的范围不受以上实施方式的限制,而是由权利要求或其等同物进行限定。Although exemplary embodiments of the present invention have been described for purposes of illustration, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Carry out various modifications, additions and substitutions, etc., and all these changes should belong to the protection scope of the appended claims of the present invention, and the various steps in the various departments and methods of the products claimed in the present invention can be combined arbitrarily. form together. Accordingly, the description of the embodiments disclosed in the present invention is not intended to limit the scope of the present invention, but to describe the present invention. Accordingly, the scope of the present invention is not limited by the above embodiments, but is defined by the claims or their equivalents.

Claims (10)

1. A crimp-style power module, comprising: the power module layer comprises a first power module layer and a second power module layer which are arranged from top to bottom;
the second power module layer comprises a substrate and n × m bosses arranged on the substrate, and each boss is provided with a subunit chip; the second power module layer further comprises n signal transmission strips for connecting the grid electrodes of the sub-unit chips in each row, the signal transmission strips comprise m layers of stacked and integrated signal transmission sub-strips, and each signal transmission sub-strip is used for transmitting a signal of one sub-unit chip; n >1, m > 1.
2. The crimped power module of claim 1, wherein the m layers of stacked integrated signal transmission sub-strips have the same width, and the length of each layer of integrated signal transmission sub-strip decreases from top to bottom in sequence according to the position of the sub-unit chip.
3. The compression-type power module of claim 2, wherein the m-layer stack integrated signal transmission sub-strip comprises ejector pins, the ejector pins being connected with sub-unit chips; and the m layers of stacked and integrated signal transmission sub-strips are connected by adopting an insulating material.
4. The press-fit power module according to claim 1, wherein the first power module layer comprises an upper metal end cover layer and a lower metal end cover layer, and the lower metal end cover layer comprises an insulating outer frame and n x m metal blocks arranged corresponding to the sub-unit chips.
5. The crimp-type power module of claim 3, wherein the subunit chips comprise power chips and FRD chips, and the power chips comprise MOSFET chips or IGBT chips; the insulating material is one or a combination of more of organic silica gel, phenolic resin glue, urea-formaldehyde resin glue, temperature-resistant epoxy glue and polyimide glue.
6. A method for manufacturing a compression joint type power module is characterized by comprising the following steps:
s1: preparing m layers of stacked and integrated signal transmission sub-strips and a first power module layer; m is greater than 1;
s2: preparing a second power module layer by adopting n signal transmission sub-strips stacked and integrated by the m layers; the second power module layer comprises a substrate and n x m bosses arranged on the substrate, and each boss is provided with a subunit chip; the second power module layer further comprises n signal transmission strips for connecting the grid electrodes of the sub-unit chips in each row, the signal transmission strips comprise m layers of stacked and integrated signal transmission sub-strips, and each signal transmission sub-strip is used for transmitting a signal of one sub-unit chip; n is greater than 1;
s3: placing the first power module layer on the top of the second power module layer, and preparing the power module layer by crimping;
s4: and vertically placing at least one power module layer, and crimping to form a power module.
7. The method for preparing a crimped power module according to claim 6, wherein the S1 is used for preparing an m-layer stacked integrated signal transmission sub-strip and comprises the following steps:
s1.1: cutting on printed circuit board to obtain n pieces of x lengthiSignal transmission sub-strip of (1)<i<m;
S1.2: and m signal transmission sub-strips with the length of xi are selected, are stacked according to the sequence from short to long in length and are bonded by adopting insulating materials, and 1< i < m, so that m layers of stacked and integrated signal transmission sub-strips are formed.
8. The method for manufacturing a press-fit power module according to claim 7, wherein during the bonding, a contact position with a thimble is reserved on the signal transmission sub-strip in advance and is not bonded, and the contact position of the thimble is determined according to a gate signal connection position of the sub-unit chip.
9. The method for manufacturing a compression-type power module according to claim 6, wherein the first power module layer comprises an upper metal end cover layer and a lower metal end cover layer, and the lower metal end cover layer comprises an insulating outer frame and n × m metal blocks arranged corresponding to the subunit chips.
10. The method for manufacturing a compression joint type power module according to claim 7, wherein the subunit chip comprises a power chip and an FRD chip, the power chip comprises a MOSFET chip or an IGBT chip; the insulating material is one or a combination of more of organic silica gel, phenolic resin glue, urea-formaldehyde resin glue, temperature-resistant epoxy glue and polyimide glue.
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