CN111900207A - A SiC floating junction UMOSFET device integrated with a new etching process JBS and its preparation method - Google Patents

Abstract

The invention relates to a SiC floating junction UMOSFET device integrated with a novel etching process JBS and a preparation method thereof. The MOSFET device comprises: an N+ substrate layer, a first N- epitaxial layer, a P+ ion implantation region, a second N- epitaxial layer, first P+ implant, second P+ implant, gate electrode, first P-well, second P-well, first N+ implant, second N+ implant, first metal, second metal, and leakage pole, the second N-epitaxial layer between the first P+ implanted region and the second P+ implanted region forms a spacer, the contact interface of the first metal with the first P+ implanted region, the second P+ implanted region and the second N+ implanted region An ohmic contact is formed, and the second metal forms a Schottky contact with the upper surface of the spacer. Through the Schottky contact, the freewheeling capability of the device is improved and the fabrication cost of the device is reduced. At the same time, in the case of reverse blocking, the withstand voltage capability is improved, the reverse leakage is reduced, the avalanche resistance of the device is improved, and the reliability problem caused by the strong electric field at the corner of the trench gate can be effectively prevented.

Description

A SiC floating junction UMOSFET device integrated with a new etching process JBS and its preparation method

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a SiC floating junction UMOSFET device integrated with a novel etching process JBS and a preparation method thereof.

Background technique

In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system. Silicon (Si)-based power electronic devices have been unable to meet the requirements of system applications due to the limitations of the material itself. Silicon carbide (SiC) materials, as the representative of the third-generation semiconductor materials, are far better than silicon materials in many characteristics. Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) devices, as commercialized devices in recent years, have alternatives in terms of on-resistance, switching time, switching loss and heat dissipation performance. The huge potential of the existing IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor).

At present, the problem caused by the large forbidden band width of the silicon carbide material can be solved by the silicon carbide MOSFET device integrating the junction barrier Schottky diode. Due to the large forbidden band width of SiC material, the turn-on voltage of the parasitic PiN diode integrated in the SiC MOSFET device is mostly around 3V, which cannot provide the freewheeling effect for the SiC MOSFET device itself. Therefore, in power electronic system applications such as full bridges, a Schottky diode is often used in anti-parallel as a freewheeling diode, which increases the area of the Schottky contact area; in blocking mode, the gate oxide at the corner of the trench gate will cause Strong venue.

However, due to the large forbidden band width of SiC materials, there are still problems in SiC MOSFET devices integrating conventional junction-barrier Schottky diodes. The freewheeling capability of the SiC MOSFET device itself is weak. In the application of power electronic systems such as full bridges, the larger Schottky contact area makes the SiC MOSFET device have a larger leakage current during normal operation, which increases chip manufacturing. Cost; in blocking mode, the voltage stress of the gate will be too large, reducing the avalanche resistance of the device, and the strong field of gate oxide at the corner of the trench gate will cause a series of reliability problems.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a SiC floating junction UMOSFET device integrated with a novel etching process JBS and a preparation method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides a SiC floating junction UMOSFET device integrated with a novel etching process JBS, including:

N+ substrate layer;

a first N- epitaxial layer, disposed on the upper surface of the N+ substrate layer;

The P+ ion implantation region is located inside the first N- epitaxial layer;

A second N- epitaxial layer provided with a first trench and a second trench is disposed on the upper surface of the first N- epitaxial layer, and the first trench and the second trench are arranged adjacent to each other and spaced apart ;

a first P+ implantation region, arranged around the side surface and the ground of the first trench;

a second P+ implantation region, arranged around the side surface and the ground of the second trench;

a gate electrode, located in the third trench of the second N- epitaxial layer;

a gate dielectric layer, arranged around the side and bottom surface of the gate electrode, and spaced from the first P+ injection region and the second P+ injection region, and the gate dielectric layer and the second P+ injection region are respectively arranged on both sides of the first P+ implantation region;

a first P-well region, located inside the second N- epitaxial layer, and disposed on a side of the gate dielectric layer away from the first P+ implantation region;

a second P-well region, located inside the second N- epitaxial layer, and disposed between the gate dielectric layer and the first P+ implantation region;

a first N+ implantation region located inside the second N- epitaxial layer and above the first P-well region;

a second N+ implantation region located inside the second N- epitaxial layer and above the second P- well region;

a first metal covering the upper surface of the first P+ implantation region and the first trench surface, the upper surface of the second P+ implantation region and the second trench surface and the second N+ implantation Part of the upper surface of the region, the contact interface between the first metal and the first P+ implantation region, the second P+ implantation region and the second N+ implantation region is an ohmic contact;

a second metal, covering the surface of the second N- epitaxial layer between the first P+ implantation region and the second P+ implantation region, the second metal and the second N- epitaxial layer The contact interface is Schottky contact;

The drain electrode is arranged on the lower surface of the N+ substrate layer.

In an embodiment of the present invention, the P+ ion implantation region includes a first floating junction, a second floating junction and a third floating junction, wherein,

The first floating junction is located under the first P-well region, the second floating junction is located under the second P-well region and part of the first P+ implantation region, and the third floating junction under a portion of the second P+ implanted region.

In an embodiment of the present invention, the depth of the first P+ implantation region is greater than the depth of the gate dielectric layer.

In an embodiment of the present invention, the depth of the second P+ implantation region is greater than the depth of the gate dielectric layer.

In an embodiment of the present invention, the material of the gate electrode is polysilicon.

In an embodiment of the present invention, the material of the first metal is aluminum.

In an embodiment of the present invention, the material of the second metal is titanium, nickel, molybdenum or tungsten.

An embodiment of the present invention provides a preparation method of a SiC floating junction UMOSFET device integrated with a novel etching process JBS, including:

growing a first N- epitaxial layer on the upper surface of the N+ substrate layer;

Perform selective ion implantation on the upper surface of the first N- epitaxial layer to form a P+ ion implantation region;

growing a second N- epitaxial layer on the first N- epitaxial layer and the P+ ion implantation region;

Etching is performed on the second N-epitaxial layer to form a first trench and a second trench, and the first trench and the second trench are spaced apart;

Ion implantation is performed on the groove surface of the first trench to form a first P+ implantation region, and ion implantation is performed on the groove surface of the second trench to form a second P+ implantation region. The first P+ implantation region and the second N- epitaxial layer between the second P+ implanted regions forms spacers;

Well implantation is performed on the side of the second N- epitaxial layer away from the second trench to form a third P-well region, and N ion implantation is performed in the third P-well region to form a third N+ implantation region, the third N+ implantation region is located above the third P-well region;

A third trench is formed by etching the second N- epitaxial layer, the third P-well region and the third N+ implantation region at a target depth on the lower surface of the third P-well region. A third trench divides the third P-well region into a first P-well region and a second P-well region, the third trench divides the third N+ implant region into a first N+ implant region and a second P-well region Two N+ injection regions;

A gate dielectric layer is grown on the surface of the third trench, and a gate electrode is formed by depositing on the gate dielectric layer;

On the upper surface of the first P+ implantation region and the surface of the first trench, the upper surface of the second P+ implantation region and the surface of the second trench and part of the upper surface of the second N+ implantation region depositing a first metal, and the first metal forms an ohmic contact with the contact interface of the first P+ implantation region, the second P+ implantation region and the second N+ implantation region;

A second metal is deposited on the upper surface of the second N- epitaxial layer between the first P+ implantation region and the second P+ implantation region, and the second metal and the second N- epitaxial layer are The contact interface forms a Schottky contact, and the first metal and the second metal are source electrodes;

A drain electrode is formed by depositing metal on the lower surface of the N+ substrate layer.

In an embodiment of the present invention, the first metal forms an ohmic contact with the contact interface of the first P+ implantation region, the second P+ implantation region and the second N+ implantation region, including:

The contact interface between the first metal and the first P+ implantation region, the second P+ implantation region and the second N+ implantation region forms an ohmic contact through a rapid thermal annealing process.

In an embodiment of the present invention, the contact interface between the second metal and the second N-epitaxial layer forms a Schottky contact, including:

The contact interface between the second metal and the second N- epitaxial layer forms a Schottky contact through a low temperature rapid thermal annealing process.

Compared with the prior art, the beneficial effects of the present invention:

1. The SiC floating junction UMOSFET device of the present invention forms a P+ ion implantation region by performing selective ion implantation in the first N- epitaxial layer, that is, adding a floating junction in the first N- epitaxial layer, which can be effective in blocking mode. The reverse voltage withstand capability of the device is improved, and the switching characteristics of the device are further improved.

2. The SiC floating junction UMOSFET device of the present invention forms a Schottky diode inside the device, that is, a Schottky contact is formed with the interface of the second metal through the interval between the first P+ implantation region and the second P+ implantation region, It avoids the need for an additional Schottky diode in anti-parallel as a freewheeling diode in the application process of the power electronic system, improves the freewheeling capability and anti-avalanche capability of the device, improves the switching characteristics of the device, and reduces the fabrication cost of the device.

3. In the SiC floating junction UMOSFET device of the present invention, by carving grooves in the Schottky contact area, the electric field is kept away from the interface in the case of reverse blocking, the withstand voltage capability is improved, the reverse leakage is reduced, and the avalanche resistance of the device is improved. ability. Simultaneously etched grooves help to increase the depths of the first P+ injection region and the second P+ injection region, which can effectively prevent reliability problems caused by strong electric fields at the corners of the trench gate of the device.

Description of drawings

1 is a schematic cross-sectional structure diagram of a SiC floating junction UMOSFET device integrated with a novel etching process JBS provided by an embodiment of the present invention;

2 is a flowchart of a method for preparing a SiC floating junction UMOSFET device integrating novel etching process JBS provided by an embodiment of the present invention;

3a to 3i are schematic diagrams of a fabrication process of a SiC floating junction UMOSFET device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

It should be noted that the "up", "down", "left" and "right" mentioned in this embodiment are the positional relationship when the device structure of the SiC floating junction UMOSFET is in the state shown in the figure, and "long" refers to the SiC floating junction UMOSFET The lateral dimension of the device structure in the illustrated state, and "depth" is the vertical dimension of the SiC floating junction UMOSFET device structure in the illustrated state.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional structure diagram of a SiC floating junction UMOSFET device integrated with a novel etching process JBS according to an embodiment of the present invention. A SiC floating junction UMOSFET device integrated with a new etching process JBS, including:

N+ substrate layer 1;

The first N- epitaxial layer 2 is arranged on the upper surface of the N+ substrate layer 1;

The P+ ion implantation region 3 is located inside the first N- epitaxial layer 2;

The second N- epitaxial layer 4 provided with the first trench 16 and the second trench 17 is disposed on the upper surface of the first N- epitaxial layer 2, and the first trench 16 and the second trench 17 are arranged adjacent to each other at intervals ;

The first P+ implantation region 5 is arranged around the side surface and the ground of the first trench 16;

The second P+ implantation region 6 is arranged around the side surface and the ground of the second trench 17;

The gate electrode 8 is located in the third trench 21 of the second N- epitaxial layer 4;

The gate dielectric layer 7 is arranged around the side and bottom surface of the gate electrode 8, and is spaced from the first P+ injection region 5 and the second P+ injection region 6, and the gate dielectric layer 7 and the second P+ injection region 6 are respectively arranged in the first P+ Both sides of the injection zone 5;

The first P-well region 9 is located inside the second N- epitaxial layer 4 and is arranged on the side of the gate dielectric layer 7 away from the first P+ implantation region 5;

The second P-well region 10 is located inside the second N- epitaxial layer 4 and is arranged between the gate dielectric layer 7 and the first P+ implantation region 5;

The first N+ implantation region 11 is located inside the second N- epitaxial layer 4 and above the first P- well region 9;

The second N+ implantation region 12 is located inside the second N- epitaxial layer 4 and above the second P- well region 10;

The first metal 13 covers the upper surface of the first P+ implantation region 5 and the surface of the first trench 16 , the upper surface of the second P+ implantation region 6 and the surface of the second trench 17 and part of the second N+ implantation region 12 On the surface, the contact interface between the first metal 13 and the first P+ implantation region 5, the second P+ implantation region 6 and the second N+ implantation region 12 is an ohmic contact;

The second metal 14 covers the surface of the second N- epitaxial layer 4 between the first P+ implantation region 5 and the second P+ implantation region 6, and the contact interface between the second metal 14 and the second N- epitaxial layer 4 is a small special contact;

The drain electrode 15 is disposed on the lower surface of the N+ substrate layer 1 .

Further, the P+ ion implantation region 3 includes a first floating junction 31, a second floating junction 32 and a third floating junction 33, wherein,

The first floating junction 31 is located under the first P-well region 9, the second floating junction 32 is located under the second P-well region 10 and part of the first P+ implant region 5, and the third floating junction 33 is located under part of the second P+ implant region Zone 6 below.

In this embodiment, P+ ions (floating junction) are implanted inside the first N- epitaxial layer 2 to form a P+ ion implantation region 3, which can effectively improve the reverse voltage withstand capability of the device. The P+ ion implantation region 3 includes three horizontally distributed floating junctions, the first floating junction 31 is located under the first P-well region 9 , and the second floating junction 32 is located in the second P-well region 10 and part of the first P+ implantation region 5 Below, the third floating junction 33 is located below a portion of the second P+ implantation region 6 . The depth range of the P+ ion implantation region 3 is 0.5 μm to 1 μm, and the width range is 0.5 μm to 1.5 μm. Preferably, the depth of the P+ ion implantation region 3 is 1 μm, the width is 1.5 μm, and the doping concentration is 6×10 ¹⁷ cm ^-3 .

The target interface between the first metal 13 and the first P+ implantation region 5, the second P+ implantation region 6 and the second N+ implantation region 12 is in ohmic contact; the second metal 14 and the first P+ implantation region 5 and the second P+ implantation region covered by the second metal 14 are in ohmic contact The interface of region 6 is a Schottky contact. That is, the Schottky diode structure is integrated in the SiC floating junction UMOSFET device, which avoids the need for anti-parallel additional Schottky diodes as freewheeling diodes in the application process, improves the freewheeling capability of the device, and reduces the cost of device fabrication. At the same time, etching is performed on the second N- epitaxial layer 4 to form the first trench 16 and the second trench 17, and then ion implantation is performed to form the first P+ implantation region 5 and the second P+ implantation region 6, which helps to increase the number of A depth of the P+ implantation region 5 and the second P+ implantation region 6, the first P+ implantation region 5 can protect the gate dielectric layer 7 and the gate electrode 8, so that the voltage stress will not be too large, and at the same time, the leakage current of the Schottky diode can be prevented. becomes smaller and improves the avalanche resistance of the device.

Further, the ohmic contact is connected with the Schottky contact to form the source electrode of the SiC floating junction UMOSFET device.

In this embodiment, the depth of the N+ substrate layer 1 ranges from 200 μm to 500 μm. Preferably, the depth of the N+ substrate layer 1 is 350 μm and the doping concentration is 5×10 ¹⁸ cm ⁻³ .

The depth of the first N- epitaxial layer 2 ranges from 3 μm to 100 μm. Preferably, the depth of the first N- epitaxial layer 2 is 10 μm and the doping concentration is 6×10 ¹⁵ cm ⁻³ .

The depth of the second N- epitaxial layer 4 ranges from 3 μm to 7 μm. Preferably, the depth of the second N- epitaxial layer 4 is 6 μm and the doping concentration is 6×10 ¹⁵ cm ⁻³ .

Further, the depth of the first P+ implantation region 5 is greater than the depth of the gate dielectric layer 7 .

Further, the depth of the second P+ implantation region 6 is greater than the depth of the gate dielectric layer 7 .

The depths of the first P+ implantation region 5 and the second P+ implantation region 6 are the same, the depths are in the range of 2 μm to 6 μm, and the widths are in the range of 0.5 μm to 1 μm. The width of the spacer region ranges from 1.5 μm to 5 μm. Preferably, the width of the spacer region between the first P+ implantation region 5 and the second P+ implantation region 6 is 2 μm. The first P+ implantation region 5 and the second P+ implantation region 6 do The impurity concentration is 1×10 ¹⁹ cm ^-3 . If the width of the spacer is too small, the Schottky contact area will not be well turned on; if the width of the spacer is too large, it will lead to SiC floating junction UMOSFET devices. The leakage current is too large and the device area is too large, which is not conducive to the improvement of device performance.

The doping concentrations of the first P-well region 9 and the second P-well region 10 are both 5×10 ¹⁶ cm ⁻³ .

The doping concentrations of the first N+ implantation region 11 and the second N+ implantation region 12 are both 1×10 ¹⁹ cm ⁻³ .

Further, the material of the gate electrode 8 is polysilicon.

Further, the material of the first metal 13 is aluminum.

Further, the material of the second metal 14 is titanium, nickel, molybdenum or tungsten.

Further, the material of the drain electrode 15 is titanium, nickel or silver.

Further, the gate dielectric layer 7 is made of silicon dioxide.

Embodiment 2

Please refer to FIG. 2 and FIG. 3a to FIG. 3i. FIG. 2 is a flowchart of a method for preparing a SiC floating junction UMOSFET device integrating a novel etching process JBS provided by an embodiment of the present invention; The example provides a schematic diagram of the preparation process of a SiC floating junction UMOSFET device. A preparation method of a SiC floating junction UMOSFET device integrated with a new etching process JBS, comprising:

Step 1. A first N- epitaxial layer 2 is grown on the upper surface of the N+ substrate layer 1 .

Please refer to Fig. 3a again. First, the N+ substrate layer 1 of silicon carbide material is cleaned by RCA standard, the depth can be 350μm, and the doping concentration can be 5×10 ¹⁸ cm ^-3 , and then the N+ substrate layer 1 is subjected to epitaxial growth method. A first N-epitaxial layer 2 with a thickness of 10 μm and a doping concentration of 6×10 ¹⁵ cm ⁻³ is grown on it.

Step 2, performing selective ion implantation on the upper surface of the first N- epitaxial layer 2 to form a P+ ion implantation region 3 .

Referring to FIG. 3 b again, AI ion implantation is performed on a part of the upper surface of the first N− epitaxial layer 2 to form a P+ ion implantation region 3 . The P+ ion implantation region 3 includes three horizontally distributed floating junctions, the first floating junction 31 is located under the first P-well region 9 , and the second floating junction 32 is located in the second P-well region 10 and part of the first P+ implantation region 5 Below, the third floating junction 33 is located below a portion of the second P+ implantation region 6 . The depth range of the P+ ion implantation region 3 is 0.5 μm to 1 μm, and the width range is 0.5 μm to 1.5 μm. Preferably, the depth of the P+ ion implantation region 3 is 1 μm, the width is 1.5 μm, and the doping concentration is 6×10 ¹⁷ cm ^-3 .

Step 3 , growing a second N- epitaxial layer 4 on the first N- epitaxial layer 2 and the P+ ion implantation region 3 .

Referring to FIG. 3c again, a second N- epitaxial layer 4 is formed by epitaxial growth on the first N- epitaxial layer 2 and the P+ ion implantation region 3, and the depth of the second N- epitaxial layer 4 is 3 μm˜7 μm. Preferably, the depth of the second N-epitaxial layer 4 is 6 μm and the doping concentration is 6×10 ¹⁵ cm ⁻³ .

Step 4, performing etching on the second N- epitaxial layer 4 to form first trenches 16 and second trenches 17, and the first trenches 16 and the second trenches 17 are spaced apart.

Referring to FIG. 3d again, a photoresist with a thickness of 2 μm is deposited on the second N- epitaxial layer 4 to form a first mask layer, a first mask pattern is formed by a photolithography etching process, and then formed by an ICP etching method The first trenches 16 and the second trenches 17, the depths of the first trenches 16 and the second trenches 17 are both 0.5 μm to 2.5 μm, and the widths are both 0.5 μm to 1.5 μm. Preferably, the first trenches Both the groove 16 and the second groove 17 have a depth of 1.5 μm and a width of 1 μm. If the groove depth is too large, it will increase the difficulty of fabrication; if the groove depth is too small, the effect of increasing the junction depth will not be obvious. If the trench width is too large, the area of the SiC floating junction UMOSFET device will be wasted; if the trench width is too small, it is not conducive to the increase of the corresponding junction depth.

Step 5. Perform well implantation on the side of the second N- epitaxial layer 4 away from the second trench 17 to form a third P-well region 19, and perform N ion implantation in the third P-well region 19 to form a third N+ The implantation region 20 and the third N+ implantation region 20 are located above the third P-well region 19 .

Referring to FIG. 3f again, the first mask layer is removed by a cleaning method, a photoresist is deposited on the upper surface of the second N- epitaxial layer 4 from which the first mask layer has been removed to form a second mask layer, and a second mask layer is formed by photolithography The etching process forms a second mask pattern, performs well implantation on the side of the second N- epitaxial layer 4 away from the second trench 17, and implants AI ions to form a third P-well region 19, which is in the third P-well region. N ion implantation is performed in 19 to form a third N+ implantation region 20 .

Step 6: Perform ion implantation on the groove surface of the first trench 16 to form a first P+ implantation region 5, and perform ion implantation on the groove surface of the second trench 17 to form a second P+ implantation region 6, the first P+ implantation region The second N- epitaxial layer 4 between 5 and the second P+ implanted region 6 forms spacer regions 18 .

Referring to FIG. 3e again, the second mask layer is removed by a cleaning method, a photoresist is deposited on the upper surface of the second N- epitaxial layer 4 from which the second mask layer has been removed to form a third mask layer, and a third mask layer is formed by photolithography The etching process forms a third mask pattern. The preliminary structure of the P+ implantation region is formed on the groove surface of the first trench 16 by the AI ion implantation method, and then the first P+ implantation region 5 is formed by activation, and then the P+ implantation region is formed on the groove surface of the second trench 17. The preliminary structure is then activated to form the second P+ implanted region 6 , and the second N− epitaxial layer 4 between the first P+ implanted region 5 and the second P+ implanted region 6 is the spacer region 18 .

The activation process includes: sputtering a carbon film on the surface of the second N- epitaxial layer 4 by a carbon film sputtering machine, and activating the implanted AI ions by a high-temperature annealing method, the annealing temperature is 1650 ° C, and the annealing time is 45min. , and then remove the carbon film by an oxidation method. The model of the carbon film sputtering machine can be, for example, JCPY500.

The depth of the first P+ implantation region 5 is the same as the depth of the second P+ implantation region 6 , both in the depth range of 2 μm to 6 μm and the width in the range of 0.5 μm to 1 μm, and both are greater than the depth of the third P-well region 19 . The width of the spacer region 18 ranges from 1.5 μm to 5 μm.

Preferably, the width of the spacers 18 is 2 μm. If the width of the spacer region 18 is too small, the corresponding Schottky contact region cannot conduct well; if the width of the spacer region 18 is too large, the leakage current of the device will increase, and the device area will become larger, which is not conducive to the improvement of device performance.

Step 7. Etch the second N- epitaxial layer 4, the third P- well region 19 and the third N+ implantation region 20 at the target depth on the lower surface of the third P-well region 19 to form a third trench 21, and the third trench 21 is formed. The trench 21 divides the third P-well region 19 into the first P-well region 9 and the second P-well region 10 , and the third trench 21 divides the third N+ implantation region 20 into the first N+ implantation region 11 and the second P-well region 10 . The second N+ implantation region 12 .

Referring to FIG. 3g again, the third mask layer is removed by a cleaning method, photoresist is deposited on the upper surface of the second N- epitaxial layer 4 from which the third mask layer has been removed to form a fourth mask layer, and the fourth mask layer is formed by photolithography The fourth mask pattern is formed by the etching process, and then the third trench 21 is formed by the ICP etching method.

The depth of the third trench 21 ranges from 1 μm to 3 μm and the width ranges from 0.5 μm to 2 μm. If the depth of the third trench 21 is too large, the manufacturing difficulty will be increased; if the depth of the third trench 21 is too small, the effect of increasing the junction depth will not be obvious. The width of the third trench 21 is too large, which will waste the area of the SiC floating junction UMOSFET device; the width of the third trench 21 is too small, which is not conducive to increasing the junction depth.

Step 8 , growing a gate dielectric layer 7 on the surface of the third trench 21 , and performing deposition on the gate dielectric layer 7 to generate a gate electrode 8 .

Referring to FIG. 3g again, the formation process of the gate dielectric layer 7 and the gate electrode 8 includes: performing sacrificial oxidation on the surface of the third trench 21 to form a sacrificial oxide layer; after removing the sacrificial oxide layer, after removing the sacrificial oxide layer, a third A layer of silicon dioxide is deposited on the surface of the trench 21 to form an isolation dielectric layer; a layer of silicon dioxide is grown by a thermal oxidation method to form a gate dielectric layer 7, and after thermal oxidation is completed, annealing is performed in a nitrogen monoxide atmosphere, and the annealing temperature is 1200 ° C. The time is 1h; a layer of highly doped polysilicon is deposited by chemical vapor deposition, and then the gate electrode 8 is formed by existing processes such as photolithography and etching.

Step 9. On the upper surface of the first P+ implantation region 5 and the surface of the first trench 16 , the upper surface of the second P+ implantation region 6 and the surface of the second trench 17 and part of the upper surface of the second N+ implantation region 12 A first metal 13 is deposited, and the first metal 13 forms an ohmic contact with the contact interfaces of the first P+ implantation region 5 , the second P+ implantation region 6 and the second N+ implantation region 12 .

Further, the contact interface between the first metal 13 and the first P+ implantation region 5 and the second P+ implantation region 6 forms an ohmic contact, including:

The contact interface between the first metal 13 and the first P+ implantation region 5 and the second P+ implantation region 6 forms an ohmic contact through a rapid thermal annealing process.

Referring to FIG. 3h again, the specific process of forming the ohmic contact by the rapid thermal annealing process includes: first, the surfaces of the first trench 16 and the second trench 17 are exposed by using existing processes such as photolithography and etching; Metal 13 is deposited on the upper surface and groove surface of the first P+ implantation region 5, the upper surface and groove surface of the second P+ implantation region 6 and the target upper surface of the second N+ implantation region 12. The thermal annealing process enables the contact surfaces of the first metal 13 with the first P+ implantation region 5 and the second P+ implantation region 6 to form electrode patterns, that is, ohmic contacts. The annealing temperature is 1000° C., the annealing time is 3 minutes, and the first metal 13 may be an aluminum material.

Step 10, depositing a second metal 14 on the upper surface of the second N- epitaxial layer 4 between the first P+ implantation region 5 and the second P+ implantation region 6, and the contact between the second metal 14 and the second N- epitaxial layer 4 The interface forms a Schottky contact, and the first metal 13 and the second metal 14 are source electrodes.

Further, forming a Schottky contact at the contact interface between the second metal 14 and the second N- epitaxial layer 4 includes: forming a Schottky contact between the second metal 14 and the second N- epitaxial layer 4 through a low temperature rapid thermal annealing process.

Referring to FIG. 3h again, the specific process of forming the Schottky contact by the low-temperature rapid thermal annealing process includes: firstly protecting the metal on the backside of the first N- epitaxial layer 2 , and performing photolithography on the upper surface of the spacer region 18 A Schottky contact window is formed, while the second metal 14 is deposited on the upper surface of the spacer region 18 , and the interface between the upper surface of the spacer region 18 and the second metal 14 is formed into Schottky contact by a low temperature rapid thermal annealing process. The annealing temperature is 500° C., the annealing time is 2 minutes, and the second metal 14 may be a titanium material.

The first metal 13 and the second metal 14 are in contact and connected, and are the source electrodes of the SiC floating junction UMOSFET device.

Step 11 , depositing metal on the lower surface of the N+ substrate layer 1 to form a drain electrode 15 .

Referring to FIG. 3i again, a part of the drain electrode 15 is formed by depositing a thick metal layer on the lower surface of the N+ substrate layer 1 through a rapid thermal annealing process, and the thick metal can be titanium, nickel or silver.

In the description of the present invention, the terms "first", "second" and "third" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", "third" may expressly or implicitly include one or more of that feature.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A novel integrated etching process JBS's SiC floating junction UMOSFET device which characterized in that includes:

an N + substrate layer (1);

the first N-epitaxial layer (2) is arranged on the upper surface of the N + substrate layer (1);

a P + ion implantation region (3) located inside the first N-epitaxial layer (2);

the second N-epitaxial layer (4) is provided with a first groove (16) and a second groove (17) and is arranged on the upper surface of the first N-epitaxial layer (2), and the first groove (16) and the second groove (17) are arranged adjacently at intervals;

a first P + implant region (5) disposed around the sides of the first trench (16) and the ground;

a second P + implant region (6) disposed around the sides of the second trench (17) and the ground;

a gate electrode (8) located within the third trench (21) of the second N-epitaxial layer (4);

the gate dielectric layer (7) is arranged around the side face and the bottom face of the gate electrode (8) and is arranged at intervals with the first P + injection region (5) and the second P + injection region (6), and the gate dielectric layer (7) and the second P + injection region (6) are respectively arranged on two sides of the first P + injection region (5);

the first P-well region (9) is positioned in the second N-epitaxial layer (4) and is arranged on one side, far away from the first P + injection region (5), of the gate dielectric layer (7);

the second P-well region (10) is positioned in the second N-epitaxial layer (4) and is arranged between the gate dielectric layer (7) and the first P + injection region (5);

a first N + implantation region (11) located inside the second N-epitaxial layer (4) and above the first P-well region (9);

a second N + implantation region (12) located inside the second N-epitaxial layer (4) and above the second P-well region (10);

a first metal (13) covering the upper surface of the first P + injection region (5) and the surface of the first trench (16), the upper surface of the second P + injection region (6) and the surface of the second trench (17), and a part of the upper surface of the second N + injection region (12), wherein the contact interfaces between the first metal (13) and the first P + injection region (5), the second P + injection region (6), and the second N + injection region (12) are ohmic contacts;

a second metal (14) covering the surface of the second N-epitaxial layer (4) between the first P + injection region (5) and the second P + injection region (6), wherein the contact interface of the second metal (14) and the second N-epitaxial layer (4) is Schottky contact;

and the drain electrode (15) is arranged on the lower surface of the N + substrate layer (1).

2. The integrated new etch process JBS SiC floating junction UMOSFET device of claim 1, wherein said P + ion implantation region (3) comprises a first floating junction (31), a second floating junction (32) and a third floating junction (33), wherein,

the first floating junction (31) is located below the first P-well region (9), the second floating junction (32) is located below the second P-well region (10) and a portion of the first P + implant region (5), and the third floating junction (33) is located below a portion of the second P + implant region (6).

3. The integrated novel JBS SiC floating-junction UMOSFET device of claim 1, wherein the depth of the first P + implant region (5) is greater than the depth of the gate dielectric layer (7).

4. The integrated novel JBS SiC floating-junction UMOSFET device of claim 1, wherein the depth of the second P + implantation region (6) is greater than the depth of the gate dielectric layer (7).

5. The integrated novel etch process JBS SiC floating-junction UMOSFET device of claim 1, wherein the gate electrode (8) is made of polysilicon.

6. The integrated novel etch process JBS SiC floating-junction UMOSFET device of claim 1, wherein the material of the first metal (13) is aluminum.

7. The integrated novel etch process JBS SiC floating-junction UMOSFET device of claim 1, wherein the material of the second metal (14) is titanium, nickel, molybdenum or tungsten.

8. A preparation method of a SiC floating junction UMOSFET device integrated with a novel etching process JBS is characterized by comprising the following steps:

growing a first N-epitaxial layer (2) on the upper surface of the N + substrate layer (1);

carrying out selective ion implantation on the upper surface of the first N-epitaxial layer (2) to form a P + ion implantation region (3);

growing a second N-epitaxial layer (4) on the first N-epitaxial layer (2) and the P + ion implantation region (3);

etching on the second N-epitaxial layer (4) to form a first groove (16) and a second groove (17), wherein the first groove (16) and the second groove (17) are distributed at intervals;

performing ion implantation on the groove surface of the first groove (16) to form a first P + implantation region (5), performing ion implantation on the groove surface of the second groove (17) to form a second P + implantation region (6), and forming a spacer region (18) on the second N-epitaxial layer (4) between the first P + implantation region (5) and the second P + implantation region (6);

performing well implantation on one side of the second N-epitaxial layer (4) far away from the second trench (17) to form a third P-well region (19), performing N ion implantation in the third P-well region (19) to form a third N + implantation region (20), wherein the third N + implantation region (20) is positioned above the third P-well region (19);

etching the second N-epitaxial layer (4), the third P-well region (19) and the third N + injection region (20) at a target depth on the lower surface of the third P-well region (19) to form a third trench (21), wherein the third trench (21) divides the third P-well region (19) into a first P-well region (9) and a second P-well region (10), and the third trench (21) divides the third N + injection region (20) into a first N + injection region (11) and a second N + injection region (12);

growing a gate dielectric layer (7) on the surface of the third groove (21), and depositing on the gate dielectric layer (7) to generate a gate electrode (8);

depositing a first metal (13) on the upper surface of the first P + injection region (5) and the surface of the first trench (16), the upper surface of the second P + injection region (6) and the surface of the second trench (17), and part of the upper surface of the second N + injection region (12), wherein the first metal (13) forms ohmic contact with the contact interfaces of the first P + injection region (5), the second P + injection region (6), and the second N + injection region (12);

depositing a second metal (14) on the upper surface of the second N-epitaxial layer (4) between the first P + injection region (5) and the second P + injection region (6), wherein the contact interface of the second metal (14) and the second N-epitaxial layer (4) forms a Schottky contact, and the first metal (13) and the second metal (14) are source electrodes;

and depositing a metal generation drain electrode (15) on the lower surface of the N + substrate layer (1).

9. The method for preparing a SiC floating-junction UMOSFET device integrating a novel etching process JBS as claimed in claim 8, wherein the ohmic contact is formed between the first metal (13) and the contact interfaces of the first P + injection region (5), the second P + injection region (6) and the second N + injection region (12), and comprises the following steps:

and the contact interfaces of the first metal (13) and the first P + injection region (5), the second P + injection region (6) and the second N + injection region (12) form ohmic contact through a rapid thermal annealing process.

10. The method for preparing a SiC floating-junction UMOSFET device integrating a novel etching process JBS as claimed in claim 8, wherein the Schottky contact is formed at the contact interface of the second metal (14) and the second N-epitaxial layer (4), and comprises the following steps:

and the contact interface of the second metal (14) and the second N-epitaxial layer (4) forms a Schottky contact through a low-temperature rapid thermal annealing process.

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