CN111865100A - Power conversion device - Google Patents

Abstract

The invention provides a power conversion device, which can restrain the enlargement of the device and the increase of the transmission loss and can increase the capacity of the supplied power.

Description

Power conversion device

technical field

The present invention relates to a power conversion device, and more particularly, to a power conversion device including a smoothing capacitor and an inverter unit.

Background technique

Conventionally, a power conversion device including a smoothing capacitor and an inverter unit has been disclosed. Such a power conversion device is disclosed in, for example, Japanese Patent Laid-Open No. 2017-118693.

Japanese Patent Application Laid-Open No. 2017-118693 describes a power supply device for induction heating (power converter) including a DC power supply unit (AC power supply and converter unit), a smoothing unit (smoothing capacitor), an inverter unit, and an output unit device). In the power supply device for induction heating described in Japanese Patent Application Laid-Open No. 2017-118693, the DC power supply unit converts AC power supplied from a commercial AC power supply into DC power. In addition, the smoothing unit smoothes the pulsating current of the DC power output from the DC power supply unit. In addition, the inverter unit reversely converts the DC power smoothed by the smoothing unit into high-frequency AC power. In addition, the output unit outputs the AC power converted by the inverter unit to the heating coil.

In the power supply device for induction heating described in Japanese Patent Laid-Open No. 2017-118693, the inverter unit includes two bridge circuits having a plurality of bridge arms in which two power semiconductor elements are connected in series. And the output part side of the two bridge circuits is connected in parallel with respect to the heating coil. Thereby, the power supply to the heating coil is distributed to the two bridge circuits. That is, in the power supply device for induction heating described in Japanese Patent Laid-Open No. 2017-118693, a plurality (two) of inverter units are provided on the output side of the bridge circuit so as to be connected in parallel with each other.

Here, in the conventional power conversion device as described in Japanese Patent Laid-Open No. 2017-118693, in order to increase the capacity of power that can be supplied, it is considered to increase the number of parallel-connected inverter units to supply power to each other. method of current increase. However, when the current is increased, it is necessary to increase the thickness of the conductor in accordance with the increased current in the portion where the currents of the paralleled inverter units converge, which increases the size of the device. In addition, the heat loss lost as heat energy at the resistance (conductor) depends on the magnitude of the current. Therefore, when the current increases, the energy loss (transmission loss) in the power transmission path becomes large. Therefore, in the conventional power conversion device as described in Japanese Patent Laid-Open No. 2017-118693, there is a desire to increase the capacity of the power that can be supplied while suppressing the increase in the size of the device and the increase in power transmission loss.

SUMMARY OF THE INVENTION

Invention to solve problem

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a power conversion device that can suppress an increase in the size of the device and increase in power transmission loss and increase the capacity of the power that can be supplied. .

solution to the problem

In order to achieve the above object, an aspect of the present invention provides a power conversion device, wherein the power conversion device includes: a smoothing capacitor connected to an output side of a rectifier circuit that rectifies an AC voltage; and an inverter unit , which includes a semiconductor switching element section having a plurality of semiconductor switching elements, and converts the DC voltage smoothed by the smoothing capacitor into an AC voltage through switching of the semiconductor switching elements, and the circuit unit including the smoothing capacitor and the inverter section is in the inverter. A plurality of output sides of the circuit are connected in series with each other.

In the power conversion device according to an aspect of the present invention, as described above, a plurality of circuit units including the smoothing capacitor and the inverter unit are provided on the output side of the inverter unit so as to be connected in series with each other. As a result, the voltage of the entire plurality of inverter units connected in series becomes the sum of the voltages of the inverter units among the plurality of inverter units connected in series, so that it is possible to prevent the voltage from flowing through the inverter units. When the current of the power converter increases, the voltage output from the power conversion device is increased (higher voltage). Furthermore, since the current flowing in the inverter unit is not increased, it is not necessary to increase the thickness of the conductor (enlarge the device) as in the case of connecting a plurality of inverter units in parallel. In addition, since the heat loss lost as heat energy in the resistance (conductor) does not depend on the magnitude of the voltage, the energy loss (transmission loss) does not increase even when the voltage of the entire inverter unit increases. . As a result, it is possible to increase the capacity of power that can be supplied while suppressing an increase in the size of the device and an increase in power transmission loss.

In the power conversion device according to the above aspect, it is preferable that each of the plurality of circuit units includes an intra-unit connecting portion that connects the smoothing capacitor and the semiconductor switching element portion, and that each of the plurality of circuit units includes a unit of The internal connection portion is configured so that the inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other. Here, in the inverter unit that performs switching of the semiconductor switching elements, a surge voltage (a large wave voltage that is generated instantaneously exceeding a steady state) may be generated when the switching elements are turned ON/OFF. In addition, when surge voltages of different magnitudes are generated between the inverter units connected in series, an unexpected circulating current may flow between the inverter units connected in series. That is, in each inverter part connected in series, compared with a case where the surge voltages are equal to each other, there are device defects such as device breakage and malfunction due to the surge voltage. Furthermore, the surge voltage depends on the current flowing in the circuit and the inductance in the circuit. Therefore, by configuring as described above, the inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other among the plurality of circuit units, and therefore, it is possible to suppress a large difference in surge voltage among the plurality of circuit units. As a result, in each inverter unit connected in series, it is possible to suppress the failure of the device due to the surge voltage.

In this case, it is preferable that the circuit unit includes a first circuit unit and a second circuit unit which are connected in series to each other and are arranged in the first direction, and the structure in the first circuit unit and the structure in the second circuit unit are preferably included. The structure is configured to be symmetrical with respect to the center plane in the center between the first circuit unit and the second circuit unit, which is orthogonal to the first direction. With such a configuration, since the intra-unit connection portion of the first circuit unit and the intra-unit connection portion of the second circuit unit have the same shape, the connection between the first circuit unit and the second circuit unit can be easily realized. A structure in which the inductances between the smoothing capacitor and the semiconductor switching element portion are made equal to each other. In addition, in each of the first circuit unit and each of the second circuit units, the members other than the connecting portion within the unit have the same shape, so that the mutual flow between the first circuit unit and the second circuit unit connected in series can be suppressed. The current becomes electrically unbalanced.

In the configuration in which the first circuit unit and the second circuit unit are symmetrical to each other with respect to the center plane between the first circuit unit and the second circuit unit, it is preferable that the first circuit unit and the second circuit unit are each The smoothing capacitor has a rectangular parallelepiped shape including a terminal arrangement surface for the terminal arrangement of the smoothing capacitor, the semiconductor switching element portions of the first circuit unit and the second circuit unit are arranged along the side surfaces intersecting with the terminal arrangement surface, and the first circuit unit and the The second circuit unit is arranged so that the terminal arrangement surface of the first circuit unit and the terminal arrangement surface of the second circuit unit face each other. With this configuration, since the first circuit unit and the second circuit unit are arranged so that the terminal arrangement surface of the first circuit unit and the terminal arrangement surface of the second circuit unit face each other, it is possible to arrange the terminals in the first circuit unit The intra-unit connection portion to which the terminal of the surface-arranged smoothing capacitor is connected and the intra-unit connection portion to which the terminal of the smoothing capacitor arranged on the terminal arrangement surface of the second circuit unit is connected are arranged relatively close to each other. Therefore, for example, in order to reduce the inductance between the smoothing capacitor and the semiconductor switching element portion, in each of the first circuit cells and each of the second circuit cells, the size between the smoothing capacitor and the semiconductor switching element portion at the connection portion within the cell is reduced. In the case of the distance, the semiconductor switching element portion of the first circuit unit and the semiconductor switching element portion of the second circuit unit can be arranged relatively close. In this case, the increase in the connection distance when connecting the first circuit unit and the second circuit unit can be suppressed, the inductance between the smoothing capacitor and the semiconductor switching element portion can be reduced, and the connection between the units can also be reduced. Inductance in connected components. In addition, in each of the first circuit units and each of the second circuit units, the semiconductor switching element portion can be arranged along a side surface (a surface different from the terminal arrangement surface) intersecting with the terminal arrangement surface on which the terminals of the smoothing capacitor are arranged. Compared with the case where the semiconductor switching element portion is arranged along the surface on which the terminals of the smoothing capacitor are arranged (terminal arrangement surface), the space around the smoothing capacitor having a rectangular parallelepiped shape can be effectively used for arranging members.

In this case, it is preferable that the power conversion device further includes an inter-unit connection portion for connecting the semiconductor switching element portion of the first circuit unit and the semiconductor switching element portion of the second circuit unit, and the semiconductor switch of the first circuit unit A plurality of element portions are provided on the side surface in a manner of being aligned in a second direction orthogonal to the first direction, and the semiconductor switching element portion of the second circuit unit is provided with each of the plurality of semiconductor switching element portions of the first circuit unit. A plurality of semiconductor switching element portions are provided on the side surface in a row in a second direction orthogonal to the first direction in a corresponding manner. With this configuration, since the plurality of semiconductor switching element portions provided in the first circuit unit and the plurality of semiconductor switching element portions provided in the second circuit unit are arranged in a row in the second direction so as to correspond to each other, the simplification can be achieved. The shape of the inter-cell connection portion that connects the semiconductor switching element portion of the first circuit unit and the semiconductor switching element portion of the second circuit unit.

In the structure provided with the above-mentioned inter-cell connection portion, it is preferable that the inter-cell connection portion includes at least one of a notch and a through hole. With this configuration, at least one of the notch and the via hole can be used to adjust the difference in the length of the current path from each of the semiconductor switching element portions of the circuit unit to be small. As a result, it is possible to suppress an increase in electrical imbalance of the current flowing from each of the semiconductor switching element portions of the circuit unit.

In the structure provided with the above-mentioned inter-unit connection portion, it is preferable that the inter-unit connection portion has a symmetrical shape with respect to the center line of the inter-unit connection portion in the second direction along the first direction. With this configuration, the lengths of the current paths from the semiconductor switching element portions of the plurality of semiconductor switching element portions of the circuit unit can be made equal to one side and the other side in the second direction with the center line as the center. It is possible to suppress an increase in electrical unbalance of the current flowing from each of the semiconductor switching element portions of the circuit unit.

In the structure including the above-mentioned inter-cell connection portion, it is preferable that the inter-cell connection portion includes a first portion provided in a manner extending in the second direction in a phase with the plurality of semiconductor switching element portions of the first circuit unit. Corresponding positions; a second portion provided at positions corresponding to the plurality of semiconductor switching element portions of the second circuit unit so as to extend along the second direction; and a third portion with a portion extending along the first direction The mode is provided independently from the first part and the second part, and connects the first part and the second part. With this configuration, since the third part is provided independently of the first part provided in the first circuit unit and the second part provided in the second circuit unit, the first part and the second part are respectively set as the In each of the units connected to the first circuit unit and the second circuit unit, the third part is treated as a connection part that connects the units to each other, so that the workability at the time of assembly and maintenance of the device can be improved.

Description of drawings

FIG. 1 is a circuit diagram of a power conversion device according to an embodiment of the present invention.

2 is a perspective view showing a schematic structure of the power conversion device according to the embodiment of the present invention.

3 is a perspective view of a stacking portion (Japanese: スタック) of the power conversion device according to the embodiment of the present invention.

4 is an exploded perspective view ( 1 ) of the stacking portion of the power conversion device according to the embodiment of the present invention.

5 is a cross-sectional view (side view) of the power conversion device according to the embodiment of the present invention.

6 is an exploded perspective view ( 2 ) of the power conversion device according to the embodiment of the present invention.

FIG. 7 is a front view for explaining the arrangement between stacking parts of the power conversion device according to the embodiment of the present invention.

FIG. 8 is a side view for explaining the arrangement between stacking parts of the power conversion device according to the embodiment of the present invention.

Detailed ways

Hereinafter, embodiments that embody the present invention will be described based on the drawings.

The configuration of a power conversion device 100 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8 . The power conversion device 100 is the power conversion device 100 for the induction heating device 200 of a melting furnace for melting metal by induction heating. The power conversion device 100 is configured to generate alternating current from the alternating current power supply 300 using the semiconductor switching element 31 .

(Circuit Configuration of Power Conversion Device)

First, the circuit configuration of the power conversion device 100 will be described with reference to FIG. 1 .

As shown in FIG. 1 , the power conversion device 100 includes a plurality of rectifier circuits 10 (rectifier circuits 10a to 10d ), a plurality of smoothing capacitors 20 (smoothing capacitors 20a to 20d ), and a plurality of inverter units 30 (inverter units 30a～30d).

The rectifier circuit 10 converts the AC voltage input from the AC power source 300 into a DC voltage. The rectifier circuit 10 is provided in plural (two) with respect to one AC power source 300 . That is, the rectifier circuit 10a and the rectifier circuit 10b are provided with respect to the AC power supply 301 (transformer 301). Moreover, the rectifier circuit 10c and the rectifier circuit 10d are provided with respect to the alternating current power supply 302 (transformer 302). In addition, the anode side and the cathode side of the rectifier circuit 10a are electrically connected to the anode side and the cathode side of the rectifier circuit 10c, respectively. In addition, the anode side and the cathode side of the rectifier circuit 10b are electrically connected to the anode side and the cathode side of the rectifier circuit 10d, respectively.

The smoothing capacitor 20 is connected to the output side of the rectifier circuit 10 that rectifies the AC voltage. One smoothing capacitor 20 is provided for each rectifier circuit 10 . That is, smoothing capacitors 20a, 20b, 20c, and 20d are connected to the output sides of the rectifier circuits 10a, 10b, 10c, and 10d, respectively. In addition, the positive electrode side and the negative electrode side of the smoothing capacitor 20a are electrically connected to the positive electrode side and the negative electrode side of the smoothing capacitor 20c, respectively. In addition, the positive electrode side and the negative electrode side of the smoothing capacitor 20b are electrically connected to the positive electrode side and the negative electrode side of the smoothing capacitor 20d, respectively.

The inverter unit 30 converts the DC voltage smoothed by the rectifier circuit 10 into an AC voltage by switching the semiconductor switching element 31 . Then, the converted AC voltage is output from the inverter unit 30 to the induction heating coil 210 of the induction heating device 200 . In addition, one inverter unit 30 is provided for each rectifier circuit 10 . That is, inverter units 30a, 30b, 30c, and 30d are provided with respect to the rectifier circuits 10a, 10b, 10c, and 10d, respectively.

The inverter section 30 includes a semiconductor package 32 (semiconductor package 32a and semiconductor package 32b ) having a plurality of semiconductor switching elements 31 . The semiconductor switch element 31a and the semiconductor switch element 31b are accommodated in the semiconductor package 32a. The semiconductor switch element 31c and the semiconductor switch element 31d are accommodated in the semiconductor package 32b. In addition, the semiconductor element 32 is an example of the "semiconductor switching element part" of a claim.

In addition, although not shown in FIG. 1, the semiconductor element 32a and the semiconductor element 32b are each connected in parallel with each other, for example, each of six semiconductor elements is provided in parallel. In addition, a full bridge circuit is constituted by the semiconductor switching elements 31a to 31d. In addition, the connection point where the semiconductor switching element 31a of the inverter unit 30a (inverter unit 30c) and the semiconductor switching element 31b are connected is electrically connected to one end side of the induction heating coil 210 . In addition, the connection point where the semiconductor switching element 31c of the inverter unit 30b (inverter unit 30d ) and the semiconductor switching element 31d are connected is electrically connected to the other end side of the induction heating coil 210 .

Further, in the power conversion device 100 , the stacking portion (circuit unit) 40 is constituted by the smoothing capacitor 20 and the inverter portion 30 . Moreover, the stacking part 40 is provided with a plurality of (stacking parts 40a to 40d). In addition, the stacking part 40a and the stacking part 40c are an example of the "1st circuit unit" of a claim. In addition, the stacking part 40b and the stacking part 40d are an example of the "2nd circuit unit" of a claim.

Specifically, the stacking portion 40a is constituted by the smoothing capacitor 20a and the inverter portion 30a. In addition, the stacking portion 40b is constituted by the smoothing capacitor 20b and the inverter portion 30b. In addition, the stacking portion 40c is constituted by the smoothing capacitor 20c and the inverter portion 30c. In addition, the stacking portion 40d is constituted by the smoothing capacitor 20d and the inverter portion 30d.

Here, in the present embodiment, the stacking parts 40 including the smoothing capacitor 20 and the inverter part 30 are connected in series with each other on the output side of the inverter part 30 . In detail, the output side of the inverter part 30a of the stacking part 40a and the output side of the inverter part 30b of the stacking part 40b are electrically connected in series. In addition, the output side of the inverter portion 30c of the stack portion 40c and the output side of the inverter portion 30d of the stack portion 40d are electrically connected in series.

Specifically, the connection point of the semiconductor switching element 31c and the semiconductor switching element 31d of the inverter part 30a is electrically connected to the connection point of the semiconductor switching element 31a and the semiconductor switching element 31b of the inverter part 30b. In addition, the connection point of the semiconductor switching element 31c and the semiconductor switching element 31d of the inverter part 30c is electrically connected to the connection point of the semiconductor switching element 31a and the semiconductor switching element 31b of the inverter part 30d.

(Schematic structure of power conversion device)

Next, a schematic configuration of the power conversion device 100 will be described with reference to FIG. 2 .

As shown in FIG. 2 , in the power conversion device 100 , two stacking parts 40 (stacking part 40 a and stacking part 40 b ) are arranged in a row in the vertical direction (Z direction) in one housing 50 . In addition, the stacking portion 40a and the stacking portion 40b are respectively arranged on the lower side (Z2 side) and the upper side (Z1 side) in the casing 50 . In addition, the arrangement structure of the stacking portion 40c and the stacking portion 40d is substantially the same as the arrangement structure of the stacking portion 40a and the stacking portion 40b, which is not shown in FIG. 2 .

In the following description, the up-down direction, the left-right direction, and the front-rear direction of the casing 50 are referred to as the Z direction, the X direction, and the Y direction, respectively. In addition, the upper direction (upper side), the lower direction (lower side), the left side, the right side, the front side, and the rear side are referred to as the Z1 direction (Z1 side), the Z2 direction (Z2 side), the X1 side, and the X2 side, respectively. , Y1 side and Y2 side. In addition, the Z direction and the Y direction are examples of the "first direction" and the "second direction" in the claims, respectively.

(Structure of Stacking Section)

Next, the structure of the stacking portion 40 will be described with reference to FIGS. 3 to 6 . In addition, in FIGS. 3-6, as the stacking part 40, the arrangement|positioning (direction) of the stacking part 40a shown in FIG. 2 is used and demonstrated.

As shown in FIGS. 3 and 4 , the smoothing capacitor 20 is constituted by a film capacitor having a substantially rectangular parallelepiped shape. Further, as shown in FIG. 4 , the smoothing capacitor 20 includes a terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are linearly arranged. The terminal arrangement surface 22 is the surface on the Z1 side of the smoothing capacitor 20 . In addition, the terminal 21 includes a positive-side terminal 21p and a negative-side terminal 21n. The positive-side terminals 21p and the negative-side terminals 21n are alternately arranged along the Y direction on the terminal arrangement surface 22 .

The semiconductor element 32 includes a positive-side terminal 32p, a negative-side terminal 32n, and an output terminal 32o. The positive side terminal 32p, the negative side terminal 32n, and the output terminal 32o are arranged in the order of the positive side terminal 32p, the negative side terminal 32n, and the output terminal 32o from the Z1 side toward the Z2 side.

The semiconductor element 32 is arranged along the side surface 23 of the smoothing capacitor 20 that intersects with the terminal arrangement surface 22 , and the side surface 23 is line-symmetric with respect to the linearly arranged terminals 21 . In addition, a plurality of semiconductor elements 32 are arranged in the Y direction on the side surface 23 . Specifically, among the plurality of semiconductor elements 32 , for example, six semiconductor elements 32 a in parallel (six pieces) are arranged along the Y direction on the side surface 23 a on the X2 side of the smoothing capacitor 20 . In addition, as shown in FIG. 5 , six parallel (six) semiconductor elements 32 b are arranged along the Y direction on the side surface 23 b on the X1 side of the smoothing capacitor 20 . In addition, the semiconductor element 32 is arranged so that the surface of the semiconductor element 32 (the surface on which the positive-side terminal 32p, the negative-side terminal 32n, and the output terminal 32o are provided) follows the side surface 23 .

In addition, as shown in FIG. 4 , the semiconductor element 32 is arranged in the vicinity of the terminal arrangement surface 22 in the Z direction. Specifically, the semiconductor element 32 is arranged at a position closer to the Z1 side than the center C in the Z direction of the side surface 23 . Thereby, the distance between the positive-side terminal 32p of the semiconductor element 32 and the positive-side terminal 21p of the smoothing capacitor 20 can be made relatively small. In addition, the distance between the negative-side terminal 32n of the semiconductor element 32 and the negative-side terminal 21n of the smoothing capacitor 20 can be made relatively small. As a result, it is possible to reduce the inductance of the bus bar 60 (described later) that connects the positive-side terminal 32p of the semiconductor element 32 and the positive-side terminal 21p of the smoothing capacitor 20 and to connect the negative-side terminal 32n of the semiconductor element 32 to the The inductance of the bus bar 60 (described later) connected between the negative-side terminals 21 n of the smoothing capacitor 20 is reduced.

In addition, as shown in FIG. 5 , the height position h1 of the semiconductor element 32 a arranged on the side surface 23 a on the X2 side with respect to the terminal 21 of the smoothing capacitor 20 with respect to the smoothing capacitor 20 and the terminal arranged with respect to the smoothing capacitor 20 The height position h2 of the semiconductor element 32b on the side surface 23b on the X1 side of 21 with respect to the smoothing capacitor 20 is substantially equal. Specifically, the height position h1 of the end portion on the Z1 side of the semiconductor element 32a and the height position h2 of the end portion on the Z1 side of the semiconductor element 32b are substantially equal. In addition, the height positions h1 of the six semiconductor elements 32a are equal to each other. In addition, the height positions h2 of the six semiconductor elements 32b are equal to each other.

In addition, as shown in FIG. 3 , the stack portion 40 is provided with bus bars 60 (positive side bus bar 61 and negative side bus bar 62 ) that connect between the smoothing capacitor 20 and the semiconductor element 32 . The positive side bus bar 61 is electrically connected to the positive side terminal 32p of the semiconductor element 32 and the positive side terminal 21p of the smoothing capacitor 20 . The negative side bus bar 62 is electrically connected to the negative side terminal 32n of the semiconductor element 32 and the negative side terminal 21n of the smoothing capacitor 20 . In addition, the bus bar 60 is an example of the "connection part in a cell" of a claim.

Here, in the power conversion device 100 , the plurality of semiconductor elements 32 are arranged on the surface with respect to the terminal arrangement so that the impedances (each impedance) between each of the plurality of semiconductor elements 32 and the smoothing capacitor 20 are substantially equal. Both the side surface 23 a on the X2 side of 22 and the side surface 23 b on the X1 side with respect to the terminal arrangement surface 22 .

Specifically, as shown in FIG. 5 , the distance on the positive side bus bar 61 between the positive side terminal 32 p of the semiconductor element 32 a arranged on one side (side surface 23 a ) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20 L1 (the distance indicated by the one-dot chain line in FIG. 5 ) is on the positive side between the positive side terminal 32 p of the semiconductor element 32 b arranged on the other side (side surface 23 b ) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20 The distances L2 on the bus bars 61 are approximately equal. In addition, the distance L11 on the negative side bus bar 62 between the negative side terminal 32n of the semiconductor element 32a and the terminal 21 of the smoothing capacitor 20 is the same as the distance L11 between the negative side terminal 32n of the semiconductor element 32b and the terminal 21 of the smoothing capacitor 20 on the negative side The distance L12 on the negative side bus bar 62 is approximately equal. As a result, the impedance (each impedance) between each of the semiconductor elements 32 and the smoothing capacitor 20 can be made substantially equal, so that the current flowing between the semiconductor elements 32 and the smoothing capacitor 20 can be stabilized .

In addition, in the power conversion device 100 , as shown in FIG. 4 , the positive-side bus bar 61 and the negative-side bus bar 62 are provided in common with the plurality of semiconductor elements 32 , respectively. 5 , the positive side bus bar 61 and the negative side bus bar 62 each have a substantially U shape covering the terminal arrangement surface 22 and the regions of the side surfaces 23 a and 23 b on both sides of the smoothing capacitor 20 . Specifically, with respect to the smoothing capacitor 20 , the positive side bus bar 61 and the negative side bus bar 62 are stacked in the order of the positive side bus bar 61 and the negative side bus bar 62 . That is, the substantially U-shaped positive side bus bar 61 is arranged inside the substantially U-shaped negative side bus bar 62 . In addition, the positive side bus bar 61 and the negative side bus bar 62 are each formed by bending one metal plate. Thereby, compared with the case where the bus bar 60 is formed by connecting a plurality of metal plates, it is possible to reduce the inductance of the bus bar 60 .

In addition, as shown in FIG. 6 , insulating paper 70 is arranged between the positive side bus bar 61 and the negative side bus bar 62 . The insulating paper 70 is provided in a manner of overlapping a plurality of sheets. That is, the bus bar 60 is a bus bar having a laminated structure in which a conductive layer and an insulating layer are stacked.

Further, as shown in FIG. 5 , the positive side bus bar 61 includes a first portion 61a extending in the X direction and a second portion 61b extending toward the Z2 side from both ends of the first portion 61a in the X direction. In addition, the negative bus bar 62 includes a first portion 62a extending in the X direction and a second portion 62b extending toward the Z2 side from both ends of the first portion 62a in the X direction. Furthermore, the length L21 in the X direction of the first portion 61 a of the positive side bus bar 61 is smaller than the length L22 in the X direction of the first portion 62 a of the negative side bus bar 62 . In addition, the length L31 in the Z direction of the second portion 61b of the positive side bus bar 61 is smaller than the length L32 in the Z direction of the second portion 62b of the negative side bus bar 62 .

The positive side bus bar 61 has a leg portion 61c connected to the positive side terminal 32p of the semiconductor package 32a and the positive side terminal 32p of the semiconductor package 32b. In addition, the negative side bus bar 62 has a leg portion 62c connected to the negative side terminal 32n of the semiconductor element 32a and the negative side terminal 32n of the semiconductor element 32b. The leg portion 61c of the positive-side bus bar 61 is connected to the positive-side terminal 32p of the semiconductor package 32 through the screw member 71 . In addition, the leg portion 62c of the negative-side bus bar 62 is connected to the negative-side terminal 32n of the semiconductor package 32 through the screw 71 . Moreover, the leg part 61c and the leg part 62c are provided along the X direction. In addition, the length L41 in the X direction of the leg portion 61 c of the positive side bus bar 61 is smaller than the length L42 in the X direction of the leg portion 62 c of the negative side bus bar 62 .

The interval D1 in the Z direction between the first portion 61a of the positive side bus bar 61 and the first portion 62a of the negative side bus bar 62 is relatively small. In addition, the interval D2 in the X direction between the second portion 61b of the positive side bus bar 61 and the second portion 62b of the negative side bus bar 62 is relatively small. On the other hand, the interval D3 in the Z direction between the leg portion 61c of the positive side bus bar 61 and the leg portion 62c of the negative side bus bar 62 is relatively large. However, in the entire region of the positive side bus bar 61, a portion having a relatively large interval with the negative side bus bar 62 is only the leg portion 61c (only a relatively small region). Thereby, the leg portion 61c (leg portion 62c) corresponds to the bus bar 60 (the positive side bus bar 61 and the negative side bus bar 62) realized by laminating the positive side bus bar 61 and the negative side bus bar 62 with the insulating paper 70 therebetween. The effect of low inductance is less affected.

In addition, as shown in FIG. 6 , the front-side bus bar 61 is provided with a plurality of hole portions 61d. In addition, the negative-side bus bar 62 is provided with a plurality of hole portions 62d. In addition, the insulating paper 70 is provided with a plurality of hole portions 70a. The screw 71 is screwed to the positive terminal 21p of the smoothing capacitor 20 from the Z1 side via the hole 62d of the negative bus bar 62, the hole 70a of the insulating paper 70, and the positive bus bar 61. Thereby, the positive side bus bar 61 is connected to the positive side terminal 21p of the smoothing capacitor 20 . The screw 71 is screwed to the negative terminal 21n of the smoothing capacitor 20 from the Z1 side via the negative bus bar 62, the hole 70a of the insulating paper 70, and the hole 61d of the positive bus bar 61. Thereby, the negative side bus bar 62 is connected to the negative side terminal 21 n of the smoothing capacitor 20 .

(Structure between a plurality of stacked parts)

Next, the structure between the plurality of stacking parts 40 of the power conversion device 100 will be described with reference to FIGS. 7 and 8 .

As shown in FIG. 7 , in the present embodiment, each of the plurality of stacked parts 40 includes a bus bar 60 that connects the smoothing capacitor 20 and the semiconductor element 32 . In addition, the bus bars 60 are configured so that the inductances between the smoothing capacitor 20 and the semiconductor element 32 are substantially equal to each other.

Specifically, as shown in FIGS. 7 and 8 , the bus bars 60 of the stacking portion 40a and the busbars 60 of the stacking portion 40b are configured to be orthogonal to each other with respect to the Z direction between the stacking portion 40a and the stacking portion 40b The central central plane 90 is substantially symmetrical. That is, in the power conversion device 100, the configurations in the plurality of stacking parts 40 (the stacking parts 40a to 40d) (the shapes of the members in the stacking part 40 and the relative arrangement between the members in the stacking part 40) are configured to be mutually roughly equal.

Specifically, as shown in FIG. 7 , in the power conversion device 100 , the stacking portion 40a and the stacking portion 40b are arranged such that the terminal arrangement surface 22 of the stacking portion 40a and the terminal arrangement surface 22 of the stacking portion 40b face each other. That is, the stacking portion 40a is arranged on the lower side (Z2 side) of the housing 50 so that the terminal arrangement surface 22 becomes the upper side (Z1 side). In addition, the stack portion 40b is arranged on the upper side of the housing 50 so that the terminal arrangement surface 22 becomes the lower side.

Along with this, the first portion 61a (first portion 62a) of the positive side bus bar 61 (negative side bus bar 62) of the stack portion 40a is arranged on the upper side (Z1 side) of the stack portion 40a. Moreover, the 1st part 61a (1st part 62a) of the positive side bus bar 61 (negative side bus bar 62) of the stack part 40b is arrange|positioned on the lower side (Z2 side) of the stack part 40b.

In addition, a plurality of semiconductor elements 32 of the stacked portion 40a are provided on the side surface 23 so as to be aligned in the Y direction orthogonal to the Z direction. In addition, a plurality of semiconductor elements 32 of the stack portion 40b are provided on the side surface 23 in a row in the Y direction orthogonal to the Z direction so as to correspond to each of the semiconductor elements 32 of the plurality of semiconductor elements 32 of the stack portion 40a. status.

Here, in the present embodiment, as shown in FIG. 8 , the power conversion device 100 includes a bus bar 80 that connects the semiconductor elements 32 of the stack portion 40 a and the semiconductor elements 32 of the stack portion 40 b. Moreover, the bus bar 80 is an example of the "inter-unit connection part" of a claim.

Specifically, the bus bar 80 has a substantially symmetrical shape with respect to the center line 91 in the Y direction of the bus bar 80 along the Z direction. Further, the bus bar 80 includes a first portion 81 provided on the stack portion 40a side, a second portion 82 provided on the stack portion 40b side, and a third portion provided so as to connect the first portion 81 and the second portion 82 83.

Specifically, the first portion 81 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40a so as to extend in the Y direction. In addition, the second portion 82 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40b so as to extend in the Y direction. Moreover, the 3rd part 83 is extended in the Z direction so that the 1st part 81 and the 2nd part 82 may be connected.

The first part 81 , the second part 82 and the third part 83 are provided independently of each other, and between the first part 81 and the third part 83 and between the second part 82 and the third part 83 are tightened with bolts and nuts. solid. Moreover, the 3rd part 83 is arrange|positioned at the approximate center of the 1st part 81 and the 2nd part 82 in the Y direction.

In addition, in this embodiment, the bus bar 80 includes the through hole 80a. Specifically, a through hole 80a formed in a slit shape so as to extend in the Y direction is provided in the substantially central portion of the first portion 81 and the substantially central portion of the second portion 82, respectively. Moreover, the length in the Y direction of the through-hole 80a is larger than the length in the Y direction of the third portion 83 .

(Effect of Embodiment)

In the present embodiment, the following effects can be obtained.

In the present embodiment, as described above, a plurality of stacking sections 40 including the smoothing capacitor 20 and the inverter section 30 are provided on the output side of the inverter section 30 to be connected to each other in series. As a result, the voltage of the entire plurality of inverter units 30 connected in series becomes the total value of the voltage of each inverter unit 30 among the plurality of inverter units 30 connected in series. When the current flowing through the power converter 30 increases, the voltage output from the power conversion device 100 is increased (higher voltage). Furthermore, since the current flowing in the inverter unit 30 is not increased, it is not necessary to increase the thickness of the conductor (enlarge the power conversion device 100 ) as in the case of connecting a plurality of inverter units 30 in parallel. In addition, since the heat loss lost as heat energy in the resistance (conductor) does not depend on the magnitude of the voltage, the energy loss (transmission loss) does not change even when the voltage of the entire inverter unit 30 increases. big. As a result, it is possible to increase the capacity of power that can be supplied while suppressing an increase in size of the power conversion device 100 and an increase in power transmission loss.

In addition, in the present embodiment, as described above, each of the plurality of stacked portions 40 is configured to include the bus bar 60 that connects the smoothing capacitor 20 and the semiconductor element 32 . In addition, the bus bars 60 of the plurality of stacked portions 40 are configured so that the inductances between the smoothing capacitor 20 and the semiconductor element 32 are substantially equal to each other. Thereby, the inductances between the smoothing capacitor 20 and the semiconductor element 32 are substantially equal to each other among the plurality of stacked parts 40 , and therefore, it is possible to suppress a large difference in surge voltage among the plurality of stacked parts 40 . As a result, in each inverter unit 30 connected in series, the failure of the power conversion device 100 due to the surge voltage can be suppressed.

In addition, in the present embodiment, as described above, the stacking portion 40 is configured to include the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) that are connected in series to each other and are arranged in line in the Z direction. Also, the structure in the stacking portion 40a (stacking portion 40c ) and the structure in the stacking portion 40b (stacking portion 40d ) are configured such that the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b are orthogonal to each other with respect to the Z direction The center surface 90 of the center between (stack part 40d) is substantially symmetrical. As a result, the bus bars 60 of the stacking portion 40a (stacking portion 40c) and the busbars 60 of the stacking portion 40b (stacking portion 40d) have substantially the same shape. Between (stacked portions 40d), a structure in which the inductances between the smoothing capacitor 20 and the semiconductor element 32 are made substantially equal to each other can be easily realized. In addition, in each stacking portion 40a (stacking portion 40c ) and each stacking portion 40b (stacking portion 40d ), members other than the bus bars 60 have substantially the same shape, so that the stacking portion 40a (stacking portion 40d ) connected in series can be suppressed from forming. The mutual currents flowing between the portion 40c) and the stack portion 40b (stack portion 40d) become electrically unbalanced.

In addition, in the present embodiment, as described above, the smoothing capacitors 20 of the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ) are configured to have a terminal arrangement including the arrangement of the terminals 21 of the smoothing capacitors 20 . The substantially rectangular parallelepiped shape of the face 22 . In addition, the semiconductor elements 32 of the stacking portion 40 a (stacking portion 40 c ) and the stacking portion 40 b (stacking portion 40 d ) are arranged along the side surfaces 23 intersecting with the terminal arrangement surface 22 . In addition, the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ) face the terminal arrangement surface 22 of the stacking portion 40a (stacking portion 40c ) and the terminal arrangement surface 22 of the stacking portion 40b (stacking portion 40d ) way to configure. Thus, since the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ) face each other with the terminal arrangement surface 22 of the stacking portion 40a (stacking portion 40c ) and the terminal arrangement surface 22 of the stacking portion 40b (stacking portion 40d ) Therefore, the bus bar 60 connected to the terminal 21 of the smoothing capacitor 20 arranged on the terminal arrangement surface 22 of the stack portion 40a (stack portion 40c ) and the terminal of the stack portion 40b (stack portion 40d ) can be arranged The bus bars 60 to which the terminals 21 of the smoothing capacitors 20 arranged on the surface 22 are connected are arranged relatively close. Therefore, in order to reduce the inductance between the smoothing capacitor 20 and the semiconductor element 32, the smoothing capacitor 20 on the bus bar 60 and the smoothing capacitor 20 and the In the case of the distance between the semiconductor elements 32, the semiconductor elements 32 of the stack part 40a (stack part 40c) and the semiconductor elements 32 of the stack part 40b (stack part 40d) can be arranged relatively close. As a result, it is possible to suppress the increase in the connection distance when connecting the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ), so that the inductance between the smoothing capacitor 20 and the semiconductor element 32 can be reduced, and It is also possible to reduce the inductance in the member (the bus bar 80 ) that connects the stacked portions 40 . In addition, in each stacking portion 40a (stacking portion 40c) and each stacking portion 40b (stacking portion 40d), the semiconductor element 32 can be placed along the side surface 23 (with the terminal arrangement surface 22 where the terminals 21 of the smoothing capacitor 20 are arranged) intersecting with each other. Compared with the case where the semiconductor components 32 are arranged along the surface on which the terminals 21 of the smoothing capacitor 20 are arranged (the terminal arrangement surface 22 ), it is possible to effectively use for the arrangement member The space around the smoothing capacitor 20 having a substantially rectangular parallelepiped shape.

In addition, in the present embodiment, as described above, the power conversion device 100 is configured to include a bus that connects the semiconductor elements 32 of the stacking portion 40a (stacking portion 40c ) and the semiconductor elements 32 of the stacking portion 40b (stacking portion 40d ). Article 80. In addition, a plurality of semiconductor elements 32 of the stacked portion 40a (stacked portion 40c) are provided on the side surface 23 intersecting with the terminal arrangement surface 22 so as to be aligned in the Y direction orthogonal to the Z direction. In addition, the semiconductor elements 32 of the stacking portion 40b (stacking portion 40d) are placed on the side intersecting the terminal arrangement surface 22 so as to correspond to each semiconductor element 32 of the plurality of semiconductor elements 32 of the stacking portion 40a (stacking portion 40c). 23, a plurality of them are arranged in the Y direction orthogonal to the Z direction. As a result, the plurality of semiconductor elements 32 provided in the stacking portion 40a (stacking portion 40c ) and the plurality of semiconductor elements 32 provided in the stacking portion 40b (stacking portion 40d ) are aligned in the Y direction so as to correspond to each other. The shape of the bus bar 80 that connects the semiconductor elements 32 of the stack portion 40a (stack portion 40c) and the semiconductor elements 32 of the stack portion 40b (stack portion 40d) can be simplified.

In addition, in the present embodiment, as described above, the bus bar 80 is configured to include the through hole 80a. Thereby, the through hole 80a can be used to adjust so that the difference in the length of the current path of each semiconductor element 32 from among the plurality of semiconductor elements 32 (arranged in the Y direction) from the stack portion 40 is small. As a result, it is possible to suppress an increase in the electrical imbalance of the current flowing from each of the semiconductor elements 32 in the stack portion 40 .

In the present embodiment, as described above, the bus bar 80 is configured to have a substantially symmetrical shape with respect to the center line 91 of the bus bar 80 in the Y direction along the Z direction. Thereby, the lengths of the current paths from each of the semiconductor switching element portions of the stack portion 40 can be made on one side (the Y1 side) and the other side (the Y1 side) in the Y direction with the center line 91 as the center. Y2 side) are substantially equal, so that it is possible to suppress an increase in the electrical imbalance of the current flowing from each of the semiconductor elements 32 of the plurality of semiconductor elements 32 in the stack portion 40 .

In addition, in the present embodiment, the bus bar 80 is configured to include the first portion 81 , the second portion 82 , and the third portion 83 as described above. In addition, the first portion 81 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40a so as to extend in the Y direction. In addition, the second portion 82 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40b so as to extend in the Y direction. In addition, the third portion 83 is provided independently of the first portion 81 and the second portion 82 so as to extend in the Z direction, and the third portion 83 connects the first portion 81 and the second portion 82 . Thus, the third portion 83 is provided independently of the first portion 81 provided in the stacking portion 40a (stacking portion 40c ) and the second portion 82 provided in the stacking portion 40b (stacking portion 40d ). The part 81 and the second part 82 are treated as the units connected to the stacking part 40a and the stacking part 40b, respectively, and the third part 83 is handled as a connecting part that connects the units to each other, so that the assembly and maintenance of the power conversion device 100 can be improved. time workability.

[Variation]

The embodiments disclosed this time should be considered to be illustrative and not restrictive in all respects. The scope of the present invention is indicated by the claims, not the description of the above-described embodiments, and the scope of the present invention includes the meaning equivalent to the claims and all the changes (modifications) within the scope.

For example, in the above-described embodiment, the bus bar 80 is configured to include the first portion 81 provided at the position corresponding to the plurality of semiconductor elements 32 of the stack portion 40 a (stack portion 40 c ), and the first portion 81 provided in the stack portion 40 b A second portion 82 provided at positions corresponding to the plurality of semiconductor elements 32 of the stack portion 40 d , and a second portion provided independently of the first portion 81 and the second portion 82 to connect the first portion and the second portion 3 part 83 example, but the present invention is not limited to this. In the present invention, the "inter-unit connection portion" may be configured as one member in which the first part, the second part, and the third part are integrally provided.

In addition, in the above-mentioned embodiment, the example in which the bus bar 80 is comprised so that the through hole 80a may be included was shown, but this invention is not limited to this. In the present invention, the "inter-cell connection portion" may be configured to include a notch instead of a through hole. In addition, the "inter-cell connection portion" may be configured to include both a through hole and a notch.

In addition, in the above-described embodiment, the semiconductor elements 32 of the stacking portion 40a (stacking portion 40c ) are provided in a plurality of arrays in the Y direction, and the semiconductor elements 32 of the stacking portion 40b (stacking portion 40d ) are Although a plurality of semiconductor elements 32 of the plurality of semiconductor elements 32 in the stacking portion 40a (stacking portion 40c) are arranged in a row in the Y direction so as to correspond to each other, the present invention is not limited to this example. In the present invention, the “semiconductor switching element portion” of the “first circuit unit” and the “semiconductor switching element portion” of the “second circuit unit” may be configured to be arranged in a plurality of directions that are different from each other.

In addition, in the above-described embodiment, the smoothing capacitors 20 of the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ) are each configured to have a terminal arrangement surface including a terminal arrangement surface where the terminals 21 of the smoothing capacitor 20 are arranged. 22 has a substantially rectangular parallelepiped shape, and the stacking portion 40a (stacking portion 40c) and stacking portion 40b (stacking portion 40d) are arranged with the terminal arrangement surface of stacking portion 40a (stacking portion 40c) 22 and the stacking portion 40b (stacking portion 40d) terminals An example in which the arrangement surfaces 22 are arranged so as to face each other, but the present invention is not limited to this. In the present invention, the "first circuit unit" and the "second circuit unit" may be arranged such that the terminal arrangement surface of the "first circuit unit" and the terminal arrangement surface of the "second circuit unit" do not face each other.

In addition, in the above-described embodiment, the smoothing capacitors 20 of the stacking portion 40a (stacking portion 40c ) and the stacking portion 40b (stacking portion 40d ) are each configured to have a terminal arrangement surface including a terminal arrangement surface where the terminals 21 of the smoothing capacitor 20 are arranged. 22 has a substantially rectangular parallelepiped shape, and the semiconductor elements 32 of the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) are arranged along the side surface 23 intersecting the terminal arrangement surface 22, but the present invention does not limited to this. In the present invention, the “semiconductor switching element portion” of each of the “first circuit unit” and the “second circuit unit” may be arranged along a side other than a side surface intersecting with a terminal arrangement surface such as a terminal arrangement surface where the terminals of the smoothing capacitor are arranged. face configuration.

In addition, in the above-described embodiment, the stacking portion 40 is shown to include two stacking portions 40 (stacking portion 40 a (stacking portion 40 c ) and stacking portion 40 b (stacking portion 40 a (stacking portion 40 c ) and stacking portion 40 b ( An example of the stacking portion 40d)), but the present invention is not limited to this. In the present invention, the “circuit unit” may be configured to include three or more “circuit units” that are connected in series with each other and arranged to be aligned with each other in the Z direction.

For example, in the above-described embodiment, the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) are shown to be configured to be orthogonal to each other with respect to the Z direction, the stacking portion 40a (stacking portion 40c) and the stacking portion 40c are shown. Although the center surface 90 of the center between the stacking parts 40b (stacking part 40d) is substantially symmetrical, this invention is not limited to this. In the present invention, the “first circuit unit” and the “second circuit unit” may be configured to be substantially symmetrical to each other with respect to a plane other than the central plane between the “first circuit unit” and the “second circuit unit”. In addition, the "first circuit unit" and the "second circuit unit" may be configured to be asymmetrical to each other. In this case, it is desirable to configure the “first circuit unit” and the “second circuit unit” so that the inductances between the smoothing capacitor and the “semiconductor switching element portion” are substantially equal to each other.

Claims (8)

1. A power conversion apparatus, wherein,

the power conversion device is provided with:

a smoothing capacitor connected to an output side of a rectifier circuit that rectifies an alternating-current voltage; and

an inverter unit including a semiconductor switching element unit having a plurality of semiconductor switching elements, the inverter unit converting the DC voltage smoothed by the smoothing capacitor into an AC voltage by switching the semiconductor switching elements,

A plurality of circuit units including the smoothing capacitor and the inverter unit are provided on an output side of the inverter unit so as to be connected in series with each other.

2. The power conversion apparatus according to claim 1,

each of the plurality of circuit units includes an intra-unit connection portion connecting the smoothing capacitor and the semiconductor switching element portion,

the intra-cell connection portion of each of the plurality of circuit cells is configured such that inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other.

3. The power conversion apparatus according to claim 2,

the circuit units include a 1 st circuit unit and a 2 nd circuit unit connected in series with each other and arranged in a manner of being arranged in a 1 st direction,

the 1 st and 2 nd circuit units are configured to be plane-symmetric with respect to a center of a center between the 1 st and 2 nd circuit units, the center being orthogonal to the 1 st direction.

4. The power conversion apparatus according to claim 3,

the smoothing capacitor of each of the 1 st circuit unit and the 2 nd circuit unit has a rectangular parallelepiped shape including a terminal arrangement surface on which terminals of the smoothing capacitor are arranged,

The semiconductor switching element portions of the 1 st circuit unit and the 2 nd circuit unit are arranged along a side surface intersecting the terminal arrangement surface,

the 1 st circuit unit and the 2 nd circuit unit are arranged such that the terminal arrangement surface of the 1 st circuit unit and the terminal arrangement surface of the 2 nd circuit unit face each other.

5. The power conversion apparatus according to claim 4,

the power conversion device further includes an inter-cell connection portion that connects the semiconductor switching element portion of the 1 st circuit cell and the semiconductor switching element portion of the 2 nd circuit cell,

a plurality of the semiconductor switching element portions of the 1 st circuit unit are provided on the side surface so as to be aligned in a 2 nd direction orthogonal to the 1 st direction,

the semiconductor switching element portions of the 2 nd circuit unit are provided in plurality in the 2 nd direction orthogonal to the 1 st direction on the side surface so as to correspond to the respective semiconductor switching element portions of the plurality of semiconductor switching element portions of the 1 st circuit unit.

6. The power conversion apparatus according to claim 5,

the inter-unit connection portion includes at least any one of a notch and a through hole.

7. The power conversion apparatus according to claim 5 or 6,

the inter-cell connecting portion has a shape symmetrical with respect to a center line in the 2 nd direction of the inter-cell connecting portion along the 1 st direction.

8. The power conversion apparatus according to claim 5,

the inter-cell connection portion includes:

a 1 st portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 1 st circuit unit so as to extend in the 2 nd direction;

a 2 nd portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 2 nd circuit unit so as to extend along the 2 nd direction; and

a 3 rd part provided independently from the 1 st part and the 2 nd part in such a manner as to extend in the 1 st direction, and provided to connect the 1 st part and the 2 nd part.

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