CN111769906B - Data transmission method and device for adaptively reducing processing delay of coding layer and link layer - Google Patents

Abstract

The invention discloses a data transmission method and a device for adaptively reducing the processing delay of an encoding layer and a link layer.A FEC-decoded link layer message A and a non-FEC-decoded link layer message B are respectively generated for data to be FEC-decoded by a PCS layer; the LLP layer receives the link layer message B first, and if the link layer message B passes the check, the link layer message B is output as a correct result; otherwise, if the error of the link layer message B is an error code which can be corrected, outputting the corrected link layer message B after error correction, if the error correction fails, waiting for a subsequent link layer message A, and if the link layer message A passes the check, outputting the link layer message A as a correct result; otherwise, discarding the link layer message to start message retransmission of the target message. The invention takes the transaction layer message as the control granularity, and automatically selects whether to carry out the error correction processing of the FEC decoder according to the error code condition of the physical medium, thereby adaptively reducing the processing delay of the coding layer and the link layer.

Description

A data transmission method and device for adaptively reducing the processing delay of coding layer and link layer

technical field

The invention relates to the field of communication chips, in particular to a data transmission method and device for adaptively reducing the processing delay of the coding layer and the link layer.

Background technique

In a communication chip, the data link layer (LLP) and the physical coding layer (PCS) are located between the transaction layer and the physical medium. As shown in Figure 1, the coding layer (PCS) is responsible for encoding and decoding the data of the link layer (LLP) according to the special requirements of the physical medium, and the link layer (LLP) adopts the retransmission mechanism to be responsible for the reliable transmission of the message , the data transmission and reception between the transaction layer and the physical medium can only be realized through the data link layer and the physical coding sublayer. At present, the transmission rate of physical media has reached 25Gbps~50Gbps. In this rate range, in order to ensure the correctness of data transmission, the coding layer of the IEEE 802.3cd standard uses forward error correction coding (FEC) to correct errors in data transmission. For errors that exceed the error correction capability of FEC, the link layer further ensures reliable data transmission by retransmitting error packets.

FIG. 2 shows the processing flow of link layer and physical layer data transmission in the prior art. The data transmission at the transaction layer is in units of packets, each packet contains multiple fragments (FLITs) with a fixed length of 256 bits, and the packets enter the link layer sequentially in units of fragments. The processing flow of the data sender is: Generate CRC: The link layer CRC generation logic calculates the CRC checksum of the message data and fills it in the FLIT fixed field at the end of the message. Retransmission management: The link layer fills in the packet sequence number (SEQ) in the FLIT fixed field of the packet header and sends it to the encoding layer, and at the same time copies the packet to the retransmission management logic for possible packet retransmission. 64/66 encoding and rate matching: The encoding layer performs 64/66 encoding on the 256-bit message FLIT to generate 264-bit data blocks. 264/257 encoding: The encoding layer compresses and encodes 264-bit data blocks into 257-bit data blocks. Scrambling: The coding layer scrambles the data, and the scrambling polynomial is X^X39^X58. Where X represents the current scrambled data bits, X39 and X58 represent the first 39 and 58 bits of the current data respectively, and ^ is the exclusive OR operator. Inserting an alignment mark: The coding layer periodically inserts a specific symbol string into the data as the alignment mark of the FEC block. The insertion period is 4096 FEC blocks, and each FEC block contains 5140 bits of user data. FEC encoding: The encoding layer generates a 300-bit checksum for each FEC block of 5140 bits of user data, and inserts the checksum at the end of the FEC block. Symbol distribution: The coding layer transmits data to the adaptation layer interface of the four physical media sequentially and in turn in units of 10-bit symbols. The processing flow of the data receiving end is: channel lock alignment and resequencing: the coding layer receives data from the adaptation layer interfaces of the four physical media, identifies the alignment marks contained in the data, rearranges the 4-way data according to the alignment marks, aligns the data and send. FEC decoding: The encoding layer decodes each 5440-bit FEC block. If the bypass error correction function is enabled in the configuration, the 5140-bit user data of the FEC block is directly taken out after the checksum is checked and sent; otherwise, the correctness of the 5140-bit user data is checked according to the 300-bit checksum of the FEC block. , if there is an error, error correction is performed. Remove alignment marks: The coding layer removes FEC block alignment marks that appear periodically in the data. Descramble: The encoding layer descrambles the data, and the descrambling polynomial is X^X39^X58. 257/264 decoding: The encoding layer decompresses and encodes 257-bit data into 264-bit data blocks. 66/64 decoding and rate matching: The encoding layer performs 66/64 decoding on the 264-bit data block to generate a 256-bit data block and sends it to the link layer. CRC and sequence number check: The link layer checks the CRC checksum and sequence number SEQ of the message in units of messages. If it is correct, it will be sent to the data output logic, otherwise the message will be discarded. Data output: output data packets to the transaction layer.

In the data transmission process flow of the above link layer and physical layer, the user can control the working mode of the FEC decoder by enabling/disabling the bypass error correction function of the configuration management module: if the bypass error correction is enabled in the configuration, the FEC The decoder does not perform error correction processing on each FEC data block; if the disable bypass error correction is configured, the FEC decoder must perform error correction processing on each FEC data block. The processing delay of an FEC decoder with error correction bypass enabled is about 50 clock cycles higher than that with error correction bypass enabled, so configuring bypass error correction is generally considered as a way to reduce the processing delay of the coding layer. Generally, the basic principle of enabling/disabling bypass error correction is: if there is no bit error in the underlying physical medium, configure the enabling bypass error correction function to reduce the processing delay of the coding layer; otherwise, if there is an error in the underlying physical medium If the FEC decoding fails to correct the error, the data link layer will ensure the reliability of the data through retransmission, and if the FEC Decoding can only correct errors, which means that the purpose of forward error correction is achieved. However, the prior art and its configuration method have the following outstanding problems: (1) It is difficult to adapt to the variability of the bit error situation of the physical medium. In practical application systems, due to the influence of various environmental factors such as temperature, humidity, and electromagnetism, the bit error situation of the underlying physical medium of the network changes dynamically. In the prior art, the configuration is usually statically selected according to the bit error situation of the physical medium in the training phase, so it is difficult to adapt to its variability. If the configuration is dynamically selected according to the current state of the physical medium, the dynamic configuration change will bring about loss of user packets. Serious error problem. (2) It is difficult to adapt to the granularity difference between transaction layer packets and FEC blocks. Transaction layer packets and FEC data blocks are defined in different network layers and their granularity is different (usually, the FEC size is fixed, while the transaction layer data is a variable-length packet). It does not mean that error correction processing is required for each FEC block. Even if a single FEC data block needs to undergo error correction processing, it does not mean that each transaction layer packet in the FEC block needs to undergo error correction processing. In the prior art, when the underlying physical medium has bit errors, it is configured to disable and bypass the error correction function, so that in this case, all transaction layer message transmissions have a relatively large fixed FEC decoding delay. The above two situations that are difficult to adapt to in the prior art will eventually lead to disadvantages such as high retransmission rate or large average transmission delay in the processing flow of the link layer and the coding layer.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention: in view of the above-mentioned problems of the prior art, a data transmission method and device for adaptively reducing the processing delay of the coding layer and the link layer are provided. The medium error condition automatically selects whether to perform error correction processing of the FEC decoder, thereby adaptively reducing the processing delay of the coding layer and the link layer, so as to automatically adapt to the dynamic change of the physical medium error condition with the transaction layer message as the granularity. The purpose of the processing delay of the coding layer and the link layer.

In order to solve the above-mentioned technical problems, the technical scheme adopted in the present invention is:

A data transmission method for adaptively reducing the processing delay of the coding layer and the link layer, the method comprises the following steps:

1) The PCS layer generates the first channel of data decoded by FEC and the second channel of data not decoded by FEC for the received data of the target packet to be FEC decoded, respectively, and generates the link layer packet A from the first channel of data. And output it to the LLP layer; generate the link layer packet B of the second channel of data and output it to the LLP layer;

2) The LLP layer first receives the link layer packet B and checks the CRC and serial number. If the link layer packet B passes the check, it discards the link layer packet A that arrives later, and uses the link layer packet B as the link layer packet. If the correct result is output, end; otherwise, if the link layer packet B checks and finds an error, go to the next step;

3) Determine whether the error found in the inspection result of the link layer packet B is a correctable error code. If it is a correctable error code, correct the link layer packet B as the correct result. Output, end; otherwise, discard the link layer packet B and wait for the subsequent link layer packet A, and skip to step 4);

4) The LLP layer receives the link layer message A and checks the CRC and serial number. If the link layer message A passes the check, it outputs the link layer message A as the correct result, and ends; otherwise, if the link layer If packet A checks and finds an error, it starts the packet retransmission of the target packet.

Optionally, before step 1), the PCS layer further includes the step of performing channel lock alignment and re-sequencing on the received target packet to obtain the data to be decoded by FEC.

Optionally, the step of generating the first channel of data decoded by FEC and the second channel of data not decoded by FEC in step 1) includes:

S1) Checksum verification is performed according to the first 5140 bits of user data of each input FEC data block, and the error detection mark and checksum are generated. At the same time, the first 5140 bits of user data are written into the level 1 cache and fixed in the level 1 cache. The number of clock beats is cached as the second data output, and copied and input to the 2-level cache for a fixed number of clock beats;

S2) The offset and the bit error amount are obtained by calculating the bit error amount for the check sum of the checksum verification calculation;

S3) Perform error correction on the user data output by the level 2 cache according to the offset and the bit error amount, output the error correction success or failure mark, and output the error-corrected data as the first channel data.

Optionally, in step 1), the step of generating the link layer message B from the second channel of data includes: sequentially removing the alignment mark, descrambling, 257/264 encoding, 66/64 decoding, and rate matching the second channel of data. Obtain link layer packet B.

Optionally, the step of generating the link layer message A from the first path of data in step 1) includes: sequentially removing the alignment mark, descrambling, 257/264 encoding, 66/64 decoding, and rate matching the first path of data. Obtain link layer packet A.

In addition, the present invention also provides a data transmission device for adaptively reducing the processing delay of the coding layer and the link layer for applying the aforementioned data transmission method for adaptively reducing the processing delay of the coding layer and the link layer, comprising an LLP sending module, an LLP A receiving module, an LLP management module, a PCS sending module, and a PCS receiving module, the LLP management modules are respectively connected with the LLP sending module and the LLP receiving module, and the received signal from the physical layer is sent to the transaction layer through the PCS receiving module and the LLP receiving module; The sending signal from the transaction layer is sent to the physical layer through the LLP sending module and the PCS sending module; it is characterized in that, the PCS receiving module includes:

The channel lock alignment and resequencing module is used to perform channel lock alignment and resequencing on the data received by the PCS receiving module to generate FEC decoded data;

A single-input and two-output FEC decoding module, which is used to generate the FEC-decoded first-path data and the FEC-decoded second-path data respectively for the FEC-decoded data;

The sub-process A module is used to generate the link layer message A from the first data and output it to the LLP layer;

The sub-process B module is used to generate the link layer message B of the second channel of data and output it to the LLP layer;

The LLP receiving module includes:

CRC and serial number check A module, which is used to check the CRC and serial number of the link layer message A;

CRC and serial number check B module, which is used to check the CRC and serial number of the link layer message B;

The multiplexing module is used to first receive the link layer packet B and check the CRC and serial number. If the link layer packet B passes the check, discard the link layer packet A that arrives later, and report the link layer packet to the link layer. The message B is output as the correct result and ends; otherwise, if an error is found in the link layer message B check, it is judged whether the error found in the check result of the link layer message B is a correctable error code, if it is a correctable error code If the error code is wrong, the link layer packet B will be corrected and output as the correct result, and the end; otherwise, the link layer packet B will be discarded and the link layer packet A will be waited for the subsequent arrival, and the link layer packet will be received. If the link layer packet A passes the check, the link layer packet A is output as the correct result, and the end is ended; otherwise, if the link layer packet A is checked and found to be wrong, the target is started. Packet retransmission of the packet.

Optionally, the single-input two-output FEC decoding module includes:

The checksum verification sub-module is used to perform checksum verification on the first 5140 bits of user data of each input FEC data block, and generate error detection positive and error flags and checksums;

Level 1 cache, which is used to cache the first 5140 bits of user data in each input FEC data block for a fixed number of clock beats and then output it as the second way data, and copy the input to the level 2 cache;

Level 2 cache, used to cache the output of level 1 cache with a fixed number of clock beats;

The bit error calculation module is used to calculate the offset and bit error for the checksum calculated by the checksum and then calculate the bit error;

The error correction module is used to correct the user data output from the level 2 cache according to the offset and the error amount, output the error correction success or failure mark, and output the error corrected data as the first channel data.

In addition, the present invention also provides a communication chip, which includes the aforementioned data transmission device for adaptively reducing the processing delay of the coding layer and the link layer.

In addition, the present invention also provides a computer device including the aforementioned communication chip.

In addition, the present invention also provides a network switching device including the aforementioned communication chip.

Compared with the prior art, the present invention has the following advantages: the present invention takes the transaction layer message as the control granularity, and automatically selects whether to bypass the error correction function of the FEC decoder according to the bit error situation of the physical medium, thereby adaptively reducing the coding layer and the error correction function. Link layer processing delay, so as to achieve the purpose of automatically adapting to the dynamic change of the physical medium bit error situation with the transaction layer message as the granularity and reducing the processing delay of the coding layer and the link layer. Under the condition that there is no bit error in the underlying physical medium, the present invention can automatically obtain the same low-delay effect as the prior art method of configuring the bypass error correction function. Under the condition that the underlying physical medium has bit errors, for the error-free message, the present invention can obtain a lower processing delay of the coding layer and the link layer than the prior art. For error-correctable error messages, the present invention can obtain coding layer and link layer processing delays equal to those of the prior art. For the error message that is not error-correctable but can be corrected after one retransmission, the present invention can also obtain lower coding layer and link layer processing delay than the prior art.

Description of drawings

FIG. 1 is a schematic diagram of a frame structure of a prior art communication chip.

FIG. 2 is a schematic diagram of the processing flow of the standard coding layer and the link layer in the prior art.

FIG. 3 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a single-input and two-output FEC decoding process flow diagram of the method and apparatus according to an embodiment of the present invention.

FIG. 6 is a schematic diagram showing the comparison of processing delays of the coding layer and the link layer in the prior art.

FIG. 7 is a schematic diagram showing the comparison of processing delays of the coding layer and the link layer according to an embodiment of the present invention.

Detailed ways

As shown in Figure 3, the data transmission method for adaptively reducing the processing delay of the coding layer and the link layer in this embodiment includes the following steps:

1) The PCS layer generates the first channel of data decoded by FEC and the second channel of data not decoded by FEC for the received data of the target packet to be FEC decoded, respectively, and generates the link layer packet A from the first channel of data. And output it to the LLP layer; generate the link layer packet B of the second channel of data and output it to the LLP layer;

2) The LLP layer first receives the link layer packet B and checks the CRC and serial number. If the link layer packet B passes the check, it discards the link layer packet A that arrives later, and uses the link layer packet B as the link layer packet. If the correct result is output, end; otherwise, if the link layer packet B checks and finds an error, go to the next step;

3) Determine whether the error found in the inspection result of the link layer packet B is a correctable error code. If it is a correctable error code, correct the link layer packet B as the correct result. Output, end; otherwise, discard the link layer packet B and wait for the subsequent link layer packet A, and skip to step 4);

4) The LLP layer receives the link layer message A and checks the CRC and serial number. If the link layer message A passes the check, it outputs the link layer message A as the correct result, and ends; otherwise, if the link layer If packet A checks and finds an error, it starts the packet retransmission of the target packet.

Referring to Fig. 3, it can be seen that a new FEC decoding processing flow is constructed in the method of this embodiment, which is characterized by a single input and two outputs, that is, one channel of data is input, but two channels of data are output. This is different from the single-input single-output FEC decoding processing flow in the prior art, that is, both input and output are one channel of data. After generating the first channel of data decoded by FEC and the second channel of data not decoded by FEC, respectively generate link layer packet A from the first channel of data and output it to the LLP layer (referred to as sub-process A); Road data generates link layer packet B and outputs it to the LLP layer (referred to as sub-process B). The output processing flow of the first channel of data is equivalent to the prior art FEC decoding process configured to disable the bypass error correction function, and the output processing flow of the second channel of data is equivalent to the prior art configured to enable the bypass error correction function FEC decoding process. Compared with the existing functions, the configuration management module and its related enabling/disabling bypass error correction function configuration signals are simplified in the method of this embodiment, because the method of this embodiment no longer needs the configuration for single-input and two-output FEC decoding. signal as its input control signal.

In this embodiment, before step 1), the PCS layer further includes the step of performing channel lock alignment and re-sequencing on the received target message to obtain the data to be decoded by FEC.

In this embodiment, the step of generating the first channel of data decoded by FEC and the second channel of data not decoded by FEC in step 1) includes:

S1) Checksum verification is performed according to the first 5140 bits of user data of each input FEC data block, and the error detection mark and checksum are generated. At the same time, the first 5140 bits of user data are written into the level 1 cache and fixed in the level 1 cache. The number of clock beats is cached as the second data output, and copied and input to the 2-level cache for a fixed number of clock beats;

S2) The offset and the bit error amount are obtained by calculating the bit error amount for the check sum of the checksum verification calculation;

S3) Perform error correction on the user data output by the level 2 cache according to the offset and the bit error amount, output the error correction success or failure mark, and output the error-corrected data as the first channel data.

In this embodiment, the step of generating the link layer packet B from the second channel of data in step 1) includes: sequentially removing the alignment mark, descrambling, 257/264 encoding, 66/64 decoding and rate The link layer packet B is obtained by matching.

In this embodiment, the step of generating the link layer message A from the first channel of data in step 1) includes: sequentially removing the alignment mark, descrambling, 257/264 encoding, 66/64 decoding and rate The link layer packet A is obtained by matching.

In this embodiment, in step 2), the LLP layer first receives the link layer packet B and checks the CRC and serial number. When checking the CRC and serial number, it discards the packets that fail the CRC checksum check, and also checks the CRC and the serial number. Packets that fail the SEQ check are discarded. CRC adopts the CRC-32 international standard, and its polynomial is:

x ³² +x ²⁶ +x ²³ +x ²² +x ¹⁶ +x ¹² +x ¹¹ +x ¹⁰ +x ⁸ +x ⁷ +x ⁵ +x ⁴ +x ² +x+1

The CRC check recalculates the CRC checksum of the message data, and compares it with the CRC checksum filled in the FLIT fixed field at the end of the message. If they are equal, the check passes, otherwise the check fails. The sequence number check is based on the sequence number of the last valid message plus 1 as the expected sequence number of the next message. The expected sequence number is compared with the sequence number SEQ filled in the FLIT fixed field at the beginning of the message. If they are equal, the check is passed, otherwise Check failed. In this embodiment, the output signals of the CRC and serial number checking of sub-process A and sub-process B are respectively connected to the two input signals of the multiplexer, and the output signal of the multiplexer is directly connected to the input signal of the data output logic.

As shown in FIG. 4 , the data transmission apparatus for adaptively reducing the processing delay of the coding layer and the link layer in this embodiment includes an LLP sending module, an LLP receiving module, an LLP management module, a PCS sending module, and a PCS receiving module. The LLP management module It is respectively connected with the LLP sending module and the LLP receiving module, the received signal from the physical layer is sent to the transaction layer through the PCS receiving module and the LLP receiving module; the sending signal from the transaction layer is sent to the physical layer through the LLP sending module and the PCS sending module; It is characterized in that, the PCS receiving module includes:

The channel lock alignment and resequencing module is used to perform channel lock alignment and resequencing on the data received by the PCS receiving module to generate FEC decoded data;

A single-input and two-output FEC decoding module, which is used to generate the FEC-decoded first-path data and the FEC-decoded second-path data respectively for the FEC-decoded data;

The sub-process A module is used to generate the link layer message A from the first data and output it to the LLP layer;

The sub-process B module is used to generate the link layer message B of the second channel of data and output it to the LLP layer;

The LLP receiving module includes:

CRC and serial number check A module, which is used to check the CRC and serial number of the link layer message A;

CRC and serial number check B module, which is used to check the CRC and serial number of the link layer message B;

The multiplexing module is used to first receive the link layer packet B and check the CRC and serial number. If the link layer packet B passes the check, discard the link layer packet A that arrives later, and report the link layer packet to the link layer. The message B is output as the correct result and ends; otherwise, if an error is found in the link layer message B check, it is judged whether the error found in the check result of the link layer message B is a correctable error code, if it is a correctable error code If the error code is wrong, the link layer packet B will be corrected and output as the correct result, and the end; otherwise, the link layer packet B will be discarded and the link layer packet A will be waited for the subsequent arrival, and the link layer packet will be received. If the link layer packet A passes the check, the link layer packet A is output as the correct result, and the end is ended; otherwise, if the link layer packet A is checked and found to be wrong, the target is started. Packet retransmission of the packet.

As shown in Figure 5, the single-input two-output FEC decoding module includes:

The checksum verification sub-module is used to perform checksum verification on the first 5140 bits of user data of each input FEC data block, and generate error detection positive and error flags and checksums;

Level 1 cache, which is used to cache the first 5140 bits of user data in each input FEC data block for a fixed number of clock beats and then output it as the second way data, and copy the input to the level 2 cache;

Level 2 cache, used to cache the output of level 1 cache with a fixed number of clock beats;

The bit error calculation module is used to calculate the offset and bit error for the checksum calculated by the checksum and then calculate the bit error;

The error correction module is used to correct the user data output from the level 2 cache according to the offset and the error amount, output the error correction success or failure mark, and output the error corrected data as the first channel data.

The LLP sending module uses FLIT as the parallel interface unit to receive the message FLIT sent by the transaction layer, fills in the sequence number SEQ in the fixed field of FLIT at the beginning of the message, and fills in the checksum CRC in the fixed field of FLIT at the end of the message, and then uses FLIT as the parallel interface The unit is sent to the PCS sending module. The sequence number SEQ of the message is generated by the LLP management module, the initial sequence number SEQ of starting data to be sent is set to 0, and the sequence number SEQ of the data message is increased by 1 each time a data message is sent. The checksum CRC of the message adopts the CRC32 international standard, and its polynomial is x ³² +x ²⁶ +x ²³ +x ²² +x ¹⁶ +x ¹² +x ¹¹ +x ¹⁰ +x ⁸ +x ⁷ +x ⁵ +x ⁴ + ^x2 +x+1.

In this embodiment, the packet is retransmitted according to the sequence number SEQ and the CRC check result, so as to ensure the reliability of data transmission. The specific method for retransmission management is as follows: when a message is directly sent to the PCS, the message is copied into the retransmission buffer, and the LLP management module starts the timer of the message. If the LLP receiving module receives a response message marked with the message SEQ before the timer expires, it will delete the message from the retransmission buffer. Otherwise, the LLP sending module retransmits the message and its subsequent messages in sequence.

The LLP receiving module uses the FLIT as the parallel interface unit to receive the two-channel message FLIT sent by the PCS receiving module, and independently and parallelly checks the CRC checksum and serial number SEQ of the message in the unit of the message. If the check passes, the message is used as the Valid packets are multiplexed and output to the transaction layer with FLIT as the parallel interface unit, otherwise the packets are discarded. The specific method of CRC and serial number SEQ check is as follows: CRC check is to recalculate the CRC checksum of the message data, and compare it with the CRC checksum filled in the FLIT fixed field at the end of the message. If they are equal, the check is passed, otherwise Check failed. The SEQ sequence number check is based on adding 1 to the sequence number of the previous valid message as the expected sequence number of the next message, and compares the expected sequence number with the SEQ filled in the FLIT fixed field at the beginning of the message. If they are equal, the check passes, otherwise the check Did not pass. The calculation of the checksum of the message adopts the CRC32 international standard, and the calculation of the expected serial number is implemented by the LLP management module.

Referring to Figure 4, the LLP management module includes link state management, timer management, and sequence number management. Link status management monitors the link status, and the basic link status includes LINK_UP and LINK_DOWN status. If the LLP is in the LINK_UP state, both the LLP sending module and the LLP receiving module are open to the transaction layer; and if the LLP is in the LINK_DOWN state, both the LLP sending module and the LLP receiving module are closed to the transaction layer. Timer management provides timing and timeout functions for the LLP sending module to implement packet retransmission management. The serial number management includes the sending serial number management provided for the LLP sending module and the receiving serial number management provided for the LLP receiving module.

In order to manage the retransmission of the message, the serial number management logic of the LLP management module obtains the serial number SEQ of the current valid message from the LLP receiving module, and needs to start the LLP sending module to send the message SEQ as the mark to the peer LLP receiving module response message. The response message is generated at the link layer, terminated at the link layer, and will not be passed to the transaction layer.

The PCS sending module uses FLIT as the parallel interface unit to receive the message FLIT sent by the LLP sending module. The 64-bit parallel data is sent to the adaptation layer interface of the four physical media respectively.

In this embodiment, the 64/66 encoding and the rate matching process perform 64/66 encoding on a 256-bit message FLIT to generate a 264-bit data block; the 264/257 encoding process compresses and encodes the 264-bit data block into a 257-bit data block; The scrambling process scrambles the data, and the standard polynomial for scrambling is X^X39^X58; the insertion alignment mark processing periodically inserts a specific symbol string into the data as the alignment mark of the FEC block, and the insertion period is 4096 FEC blocks, Each FEC block contains 5140 bits of user data; the FEC encoding process generates a 300-bit checksum for each FEC block of 5140 bits of user data, and inserts the checksum at the end of the FEC block; the symbol distribution process converts the data into 10-bit symbols as The units are sequentially transmitted to the adaptation layer interfaces of the 4 physical media in turn.

The PCS receiving module receives 64-bit parallel data from 4 physical media respectively. After channel locking alignment and re-sequencing, FEC decoding, removing alignment marks, descrambling, 257/264 decoding, 66/64 decoding and rate matching, the data is processed in two The channel FLIT parallel interface is sent to the LLP receiving module in units. Among them, FEC decoding, deletion of alignment marks, descrambling, 257/264 decoding, 66/64 decoding and rate matching, as well as CRC and serial number checking processing of the LLP receiving module constitute a sub-process, and the technical device of the present invention includes two sub-processes in total, That is, sub-process A and sub-process B.

In this embodiment, the channel lock alignment and resequencing process receives data from the adaptation layer interfaces of the four physical media, identifies the alignment marks contained in the data, and rearranges and aligns the four channels of data according to the alignment marks; The FEC data block is decoded; the FEC block alignment mark that periodically appears in the deletion data is deleted; the descrambling process descrambles the data, and the polynomial of the descrambling is X^X ³⁹ ^X ⁵⁸ ; 257/264 decoding process Decompress and encode 257-bit data into 264-bit data blocks; 66/64 decoding and rate matching process 66/64 decoding of 264-bit data blocks to generate 256-bit data blocks and hand them over to the link layer.

In this embodiment, the output signal of the channel lock alignment and resequencing processing logic is connected to the input of the single-input two-output FEC decoder. The data after channel lock alignment and re-sequencing goes directly to the 1-in 2-out FEC decoder. The first and second data signals of the logic output of the single-input two-output FEC decoder are respectively connected to the input of the deletion and alignment mark processing of the sub-process A and the sub-process B.

In this embodiment, the single-input two-output FEC decoder receives the data output from the channel lock alignment and re-sequencing processing flow, and performs checksum verification according to the first 5140 bits of user data and the last 300 bits of checksum of each FEC data block. The checksum calculation will output a correct or false control flag, which is used to control the restart of the channel lock alignment process. Regardless of the FEC data verification result, the single-input two-output FEC decoder writes the 5140-bit user data of the FEC block into the level 1 buffer, and the data is buffered by a fixed number of clock beats in the level 1 buffer and is output as the second channel data to the The delete alignment mark processing flow of sub-process B. At the same time, the actual checksum of the user data generated by the checksum verification calculation is processed by the bit error amount calculation process, and the offset and bit error amount generated by the bit error amount calculation process are input to the processing flow of checking and correcting errors. In addition to directly outputting the second channel data, the level 1 buffer also copies and inputs the data to the level 2 buffer. The data is buffered by a fixed number of clock beats in the level 2 buffer as the input of the error correction process. The error checking and correction processing performs error correction on the user data output by the 2-stage buffer according to the offset and the error amount generated by the error amount calculation process. The error correction code processing will output the error correction success or failure mark, and output the error-corrected data as the second channel data to the deletion alignment mark processing flow of sub-process A. In terms of function and actual processing flow, the first output processing flow of the single-input two-output FEC decoder is equivalent to the prior art FEC decoding flow configured with the de-enable bypass error correction function, and the second output of the single-input two-output FEC decoder The channel output processing flow is equivalent to the prior art FEC decoding flow with the bypass error correction function enabled.

In this embodiment, the CRC and checksum check output signals of sub-process A and sub-process B are respectively connected to the two input signals of the multiplexer, and the output signal of the multiplexer is directly connected to the data output logic of the LLP receiving module input signal.

The data transmission method for adaptively reducing the processing delay of the coding layer and the link layer in this embodiment has the following advantages: The case-by-case discussion is as follows:

Case 1: In the case where there is no bit error in the underlying physical medium: the prior art can reduce the processing delay of the coding layer by enabling the bypass error correction function through static configuration, while the technical method of the present invention: due to the single input and two output FEC decoder two channels The data will output correct data, so both sub-process A and sub-process B will output correct packets, but since sub-process B is equivalent to configuring and enabling the bypass error correction function, and sub-process A is equivalent to configuring enabling bypass correction. Therefore, the packet data of sub-process B will reach the LLP receiving module before the packet data of sub-process A (a difference of about 50 clock cycles). Since the LLP module decides whether to receive the message according to the expected sequence number and CRC, the LLP receiving module will obtain the message from its sub-process B and discard the message output by the sub-process A, so that the same as that of the prior art method can be obtained. Low latency effect.

Scenario 2: In the case of bit errors in the underlying physical medium: if the bypass error correction function is enabled in the prior art method, the coding layer will not correct the bit errors, and the reliable data transmission depends entirely on the retransmission guarantee of the LLP. The problem of high retransmission rate occurs; if the prior art method is configured to disable the bypass error correction function, the processing delay of the coding layer is fixed by about 50 clock cycles higher than that when the bypass error correction is configured to be enabled. In fact, due to the randomness of bit errors in the physical medium, not every link layer packet has bit errors even in the case of bit errors in the underlying medium. For the convenience of discussion, the message in this case can be classified into three types: no error code, error correctable error code, and uncorrectable error code.

If there is no bit error in the message, this situation is similar to (case 1), the single-input and two-output FEC decoder will output correct data for both channels, so both sub-process A and sub-process B will output correct packets, but the sub-process will output correct data. The packet data of B will reach the LLP receiving module before the packet data of sub-process A. Since the LLP module decides whether to receive the message according to the expected sequence number and CRC, the LLP receiving module will obtain the message from its sub-process B and discard the message output by the sub-process A, thus obtaining the same configuration as the prior art method. De-enable bypass error correction function for lower processing latency (~50 clock cycles difference);

If there are error-correctable errors in the message, the first data processing of the single-input two-output FEC decoder will output the correct data after successful error correction, and the second data processing of the FEC decoder will output the errors without error correction processing. data. Therefore, the sub-process A will output the correct message and the sub-process B will output the wrong message, and the message data of the sub-process B will reach the LLP receiving module before the message data of the sub-process A. Since the LLP module decides whether to receive the message according to the expected sequence number and CRC, the message that arrives first in sub-process B will be discarded due to the CRC check error, so the message that arrives after sub-process A will be correctly received. Usually, the retransmission timeout of the LLP is greater than 50 clock cycles, so the error packet that arrives first in the sub-process B does not trigger the retransmission of the LLP, and the error packet that arrives first in the sub-process B is received. It can be seen that in this case, the technical method of the present invention obtains the same delay effect as the prior art method configured to disable the bypass error correction function.

If there is an uncorrectable error in the message, the single-input and double-output FEC decoder will output the wrong data, so both sub-process A and sub-process B will output the wrong message, which will reach the LLP receiving module successively. Since the LLP module decides whether to receive the message according to the expected sequence number and CRC, the messages arriving successively from the sub-process B and the sub-process A will be discarded due to the CRC check error. In this case, the peer LLP module starts to retransmit the message because it has not received the confirmation message sent by the local LLP module within a fixed period of time. The retransmitted message can be divided into several situations: There are errors, there are correctable errors, and there are uncorrectable errors, and the processing methods are as described above. It can be seen that in this case, the technical method of the present invention obtains the same delay effect as the prior art method configured to disable the bypass error correction function.

Case 3: In the case of dynamic change of the underlying physical medium error conditions: the technology of the present invention does not need to configure the enabling/disabling bypass error correction function, and the processing flow is consistent with the processing flow of the above (case 2). The self-adaptive selection processing flow in the case of text errors is equivalent to the self-adaptive selection of whether to bypass the error correction function. The prior art either selects the configuration statically according to the bit error condition of the physical medium in the training phase, or dynamically selects the configuration according to the current state of the physical medium. The static selection configuration is difficult to adapt to its variability: if the disable bypass function is configured when there are currently no errors, the packet transmission delay will increase; if the enable bypass function is configured when there are current errors, it will cause LLP A large number of retransmissions are generated, thereby reducing the transmission efficiency. Dynamic configuration may cause communication interruption due to packet loss.

From the above three situations, it can be seen that the method of this embodiment has the advantage of adaptively reducing the processing delay of the coding layer and the link layer according to the bit error conditions of the physical medium. Compared with the method in the prior art, the method in this embodiment does not need to configure the enabling/disabling bypass error correction function, and can achieve a better overall technical effect. The method of this embodiment uses the transaction layer message as the control granularity, and automatically selects whether to bypass the error correction function of the FEC decoder according to the bit error condition of the physical medium, thereby adaptively reducing the processing delay of the coding layer and the link layer. In the case where there is no bit error in the underlying physical medium, this embodiment can automatically obtain the same low delay effect as the prior art method of configuring the bypass error correction function. In the case where there is a bit error in the underlying physical medium, the prior art usually configures a disable bypass error correction function to reduce the link layer retransmission rate. FIG. 6 and FIG. 7 are schematic diagrams for comparison between the coding layer and link layer processing delays of the present embodiment and the prior art (configured with the de-enable bypass error correction function) when there is a bit error in the underlying physical medium. Referring to FIG. 6 and FIG. 7 , it can be seen that, for error-free packets, this embodiment can obtain lower processing delays at the coding layer and the link layer than in the prior art. For error-correctable error packets, the present embodiment can obtain the processing delay of the coding layer and the link layer equal to that of the prior art. For an error message that is not error-correctable but can be corrected after one retransmission, this embodiment can also obtain lower processing delays at the coding layer and the link layer than in the prior art.

The data transmission device for adaptively reducing the processing delay of the coding layer and the link layer according to the present invention is a device corresponding to the data transmission method for adaptively reducing the processing delay of the coding layer and the link layer according to the present invention, and also has an automatic data transmission method according to the present invention. The technical effect of the data transmission method for reducing the processing delay of the coding layer and the link layer is the same, and will not be repeated here.

In addition, this embodiment also provides a communication chip, which includes the aforementioned data transmission device for adaptively reducing the processing delay of the coding layer and the link layer.

In addition, this embodiment also provides a computer device, where the computer device includes the aforementioned communication chip.

In addition, this embodiment also provides a network switching device, where the network switching device includes the aforementioned communication chip.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein. The present application refers to flowcharts of methods, apparatus (systems), and computer program products according to embodiments of the present application and/or processor-executed instructions generated for implementing a process or processes and/or block diagrams in a flowchart. A means for the function specified in a block or blocks. These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions An apparatus implements the functions specified in a flow or flows of the flowcharts and/or a block or blocks of the block diagrams. These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in one or more of the flowcharts and/or one or more blocks of the block diagrams.

The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims (10)

1. A data transmission method for adaptively reducing processing delays at a coding layer and a link layer, the method comprising the steps of:

1) the PCS layer respectively generates a first path of data which is FEC decoded and a second path of data which is not FEC decoded aiming at the data to be FEC decoded of the received target message, and respectively generates the first path of data into a link layer message A and outputs the link layer message A to the LLP layer; outputting the second path of data generation link layer message B to the LLP layer;

2) the LLP layer receives the link layer message B and carries out CRC and serial number check, if the link layer message B passes the check, the subsequent link layer message A is discarded, the link layer message B is output as a correct result, and the operation is finished; otherwise, if the link layer message B is checked to find errors, executing the next step;

3) judging whether the error found in the checking result of the link layer message B is an error code which can be corrected, if so, outputting the error-corrected link layer message B as a correct result, and ending; otherwise, discarding the link layer message B and waiting for the subsequent arriving link layer message A, and skipping to execute the step 4);

4) the LLP layer receives the link layer message A and checks the CRC and the serial number, if the link layer message A passes the check, the link layer message A is output as a correct result, and the operation is finished; otherwise, if the link layer message A checks and finds errors, the message retransmission of the target message is started.

2. The data transmission method for adaptively reducing the processing delay of the coding layer and the link layer according to claim 1, wherein the step 1) is preceded by a step of the PCS layer performing channel lock alignment and reordering on the received target packet to obtain the data to be FEC decoded.

3. The data transmission method for adaptively reducing the processing delay of the coding layer and the link layer according to claim 1, wherein the step of generating the first way of FEC-decoded data and the second way of data without FEC decoding in step 1) comprises:

s1) carrying out check sum calculation according to the first 5140 bit user data of each FEC data block to generate error detection, correction and error detection marks and check sums, meanwhile, writing the first 5140 bit user data into a level 1 cache, outputting the first path of data after the level 1 cache carries out fixed number clock beat cache, and copying and inputting the second path of data to a level 2 cache to carry out fixed number clock beat cache;

s2) calculating the error amount of the checksum verification to obtain the offset and the error amount;

s3) correcting the user data output by the level 2 buffer according to the offset and the error amount, outputting a mark indicating whether the error correction is successful or not, and outputting the data after error correction as a first path of data.

4. The data transmission method for adaptively reducing processing delay of an encoding layer and a link layer according to claim 3, wherein the step of generating the link layer packet B from the second path of data in step 1) comprises: and the second path of data is subjected to the alignment mark deletion, the descrambling, the 257/264 encoding, the 66/64 decoding and the rate matching in sequence to obtain a link layer message B.

5. The data transmission method for adaptively reducing processing delay of an encoding layer and a link layer according to claim 3, wherein the step of generating the link layer packet a from the first path of data in step 1) comprises: and sequentially carrying out alignment mark deletion, descrambling, 257/264 encoding, 66/64 decoding and rate matching on the first path of data to obtain a link layer message A.

6. A data transmission device for adaptively reducing the processing delay of an encoding layer and a link layer, which is applied to the data transmission method for adaptively reducing the processing delay of the encoding layer and the link layer, according to any one of claims 1 to 5, and comprises an LLP sending module, an LLP receiving module, an LLP management module, a PCS sending module and a PCS receiving module, wherein the LLP management module is respectively connected with the LLP sending module and the LLP receiving module, and a received signal from a physical layer is sent to a transaction layer through the PCS receiving module and the LLP receiving module; the transmission signal from the transaction layer is transmitted to the physical layer through the LLP transmission module and the PCS transmission module; wherein the PCS receiving module comprises:

the channel locking alignment and re-sequencing module is used for performing channel locking alignment and re-sequencing on the data received by the PCS receiving module to generate FEC decoding data;

the single-input and two-output FEC decoding module is used for respectively generating a first path of FEC decoded data and a second path of data which is not FEC decoded for the FEC decoded data;

the sub-process A module is used for generating a link layer message A from the first path of data and outputting the link layer message A to the LLP layer;

the sub-process B module is used for generating a link layer message B from the second path of data and outputting the link layer message B to the LLP layer;

the LLP receiving module comprises:

a CRC and serial number check A module used for carrying out CRC and serial number check on the link layer message A;

a CRC and serial number check B module used for carrying out CRC and serial number check on the link layer message B;

the multi-path selection module is used for receiving the link layer message B and checking the CRC and the serial number, discarding the subsequent link layer message A if the link layer message B passes the check, outputting the link layer message B as a correct result, and ending; otherwise, if the link layer message B is checked to find errors, judging whether the errors found in the checking result of the link layer message B are error codes which can be corrected or not, if the errors are error codes which can be corrected, outputting the link layer message B after error correction as a correct result, and ending; otherwise, discarding the link layer message B and waiting for a subsequent link layer message A, receiving the link layer message A and carrying out CRC and serial number check, if the link layer message A passes the check, outputting the link layer message A as a correct result, and ending; otherwise, if the link layer message A checks and finds errors, the message retransmission of the target message is started.

7. The data transmission apparatus for adaptively reducing coding layer and link layer processing delays of claim 6, wherein the single-in two-out FEC decoding module comprises:

the checksum checking sub-module is used for carrying out checksum checking on the first 5140-bit user data of each FEC data block to generate error detection, correction and error correction marks and a checksum;

the level 1 cache is used for performing fixed number clock beat cache on the first 5140-bit user data cache of each input FEC data block, outputting the data as a second path of data, and copying and inputting the data to the level 2 cache;

the level 2 cache is used for performing clock beat cache with a fixed number on the output of the level 1 cache;

the error code quantity calculation module is used for calculating the check sum of the check sum check calculation to obtain the offset and the error code quantity;

and the error checking and correcting module is used for correcting the user data output by the 2-level cache according to the offset and the error amount, outputting a mark indicating whether the error correction is successful or not, and outputting the data after error correction as the first path of data.

8. A communication chip, characterized in that the communication chip comprises a data transmission device for adaptively reducing the processing delay of the coding layer and the link layer according to any one of claims 6 to 7.

9. A computer device comprising the communication chip of claim 8.

10. A network switching device comprising the communication chip of claim 8.

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