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CN111430335B - A stacked structure cascaded GaN-based power device and packaging method thereof - Google Patents

A stacked structure cascaded GaN-based power device and packaging method thereof Download PDF

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CN111430335B
CN111430335B CN202010204594.3A CN202010204594A CN111430335B CN 111430335 B CN111430335 B CN 111430335B CN 202010204594 A CN202010204594 A CN 202010204594A CN 111430335 B CN111430335 B CN 111430335B
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clad
chip
silicon
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CN111430335A (en
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王洪
胡文龙
高升
武智斌
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South China University of Technology SCUT
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

本发明提供了一种叠层级联型GaN基功率器件及其封装方法。该器件结构为TO‑220框架上面粘接设有通孔和凹槽的DBC双面陶瓷基板，DBC陶瓷基板凹槽中粘接GaN基芯片，垂直结构的硅基MOSFET叠放于GaN基芯片源极上形成Cascode级联结构。本发明通过对GaN基芯片和硅基MOSFET芯片合理布局实现Cascode级联结构，减小了芯片占用框架的面积，减小封装体体积且提高了封装形式的选择性；通过设有通孔和凹槽结构的高导热DBC双面陶瓷基板增大了芯片与高导热材料的接触面积，提高了芯片散热性能、优化了工艺步骤，使器件的可靠性和实用性提高。

The present invention provides a stacked cascade GaN-based power device and a packaging method thereof. The device structure is a DBC double-sided ceramic substrate with through holes and grooves bonded on a TO-220 frame, a GaN-based chip bonded in the groove of the DBC ceramic substrate, and a vertically structured silicon-based MOSFET stacked on the source of the GaN-based chip to form a Cascode cascade structure. The present invention realizes the Cascode cascade structure by rationally arranging the GaN-based chip and the silicon-based MOSFET chip, thereby reducing the area of the frame occupied by the chip, reducing the volume of the package body and improving the selectivity of the packaging form; the high thermal conductivity DBC double-sided ceramic substrate with through holes and groove structures increases the contact area between the chip and the high thermal conductivity material, improves the heat dissipation performance of the chip, optimizes the process steps, and improves the reliability and practicality of the device.

Description

Cascade GaN-based power device with laminated structure and packaging method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a GaN-based power device and a packaging method thereof.
Background
Since the twentieth century, the fields of mobile communication, electronic automobiles, large-scale automatic industrial production and the like have been vigorously developed, and higher requirements are put forward for corresponding electronic systems. Power electronics, an essential core element in electronic systems, is one of the main directions for improving system performance. In order to meet the requirements of electronic system applications, power devices are evolving towards high voltages, high currents, high frequencies, high integration and intellectualization. GaN power devices have become a hot spot in the field of power electronics due to their excellent characteristics of large forbidden bandwidth, high saturated electron mobility, high thermal conductivity, etc., and HEMTs (high electron mobility transistors) made based on GaN materials are the most mature.
The GaN HEMT mainly has an enhancement mode and a depletion mode, wherein the existing preparation technology of the high-voltage GaN HEMT in the single enhancement mode is not mature, and the prepared device still has a plurality of problems, such as small gate voltage swing, unstable threshold voltage and the like, which affect the reliability of the device and the large-scale use of the device. The monomer depletion type GaN HEMT is a mode naturally formed in the preparation process, has good stability and a mature preparation process, can easily realize high voltage with breakdown voltage of more than 600V, and has the characteristics of wider driving power supply range and the like. So the single body depletion type GaN HEMT has more advantages in high-voltage high-power application. However, the depletion mode is conducted when the grid is not biased, so that the system continuously consumes energy, and the static power consumption of the system is greatly increased relative to that of the enhancement mode, so that the enhancement mode is very necessary to be formed by cascading the high-voltage depletion GaN HEMT and the low-voltage enhancement type silicon-based MOS tube.
Fig. 1 is a schematic diagram of a GaN HEMT and silicon-based MOS transistor in cascade to form a hybrid transistor with a forward turn-on voltage enhancement mode of operation. The left side is a low-voltage silicon-based MOS tube which controls the on and off of the whole mixing tube, and the right side is a high-voltage depletion GaN-based HEMT chip which plays a role in bearing high voltage when the mixing tube is turned off.
Fig. 2 is one of the implementations of fig. 1 commonly used in the prior art. In the prior art, a GaN-based cascade power device and a packaging method thereof (application number: 201810953473.1) are disclosed, wherein a TO-220FL copper frame is used as a packaging frame, a high-voltage depletion type GaN HEMT and a silicon-based MOSFET are respectively adhered TO the right and the left of a frame base island through insulating glue, and a GaN HEMT grid electrode (G2) and a silicon-based MOSFET source electrode (S1) are respectively and directly electrically connected TO the frame base island through copper wires and aluminum wires. Because the frame base island is the source electrode (S) of the hybrid tube and the low-voltage MOS tube drain electrode (D1) of the vertical structure is arranged at the bottom of the chip, according to the circuit connection mode of fig. 1, the silicon-based MOS tube drain electrode (D1) cannot be directly adhered to the frame base island.
The above technology has the disadvantages that:
1. the high-voltage depletion type GaN HEMT and the silicon-based MOSFET are respectively arranged on the right and the left of the frame base island, the arrangement layout needs to occupy the area of two chips, the GaN chips are high-power devices, the chip area is usually larger, and the problems that the design packaging layout wiring is limited, the frame selection is limited, the packaging volume is larger, the application requirements are not met and the like are often caused.
2. The MOS tube with the vertical structure is adhered to the small copper substrate through silver paste, and the small copper substrate is adhered to the frame base island through insulating glue.
3. The grid electrode of the MOS tube is larger in distance from the grid electrode pin of the frame, the wire diameter of the copper wire is small, problems easily occur in the wire bonding process, and the device is invalid due to the fact that wire punching and even direct wire breakage easily occur in the injection molding process of the subsequent plastic packaging process.
4. The used small copper substrate is easy to oxidize in the curing process of silver paste and insulating glue, so that the subsequent conductivity and bonding stability are reduced.
5. The packaging is carried out by using a copper frame, the frame is easy to oxidize in the high-temperature curing process after the insulating glue process and the silver paste process are used, in addition, when the bonding of grid copper wires is carried out, the frame is oxidized due to the fact that the frame is preheated in a guide rail of a press welder, copper wires of a silicon-based MOS tube connected to a grid of a GaN power device and copper wires of a source electrode of the silicon-based MOS tube connected to a frame base island are difficult to bond due to the fact that copper oxide is generated on the surface of the oxidized frame, and the device is invalid due to the fact that the second welding spot is subjected to cold joint and cold joint.
Disclosure of Invention
The invention provides a cascade GaN-based power device with a laminated structure and a packaging method thereof. The method uses smaller frame base island area to realize cascade structure package, so that the package frame and the chip layout have more choices.
The invention provides a cascade GaN-based power device with a laminated structure, which comprises a GaN-based high-voltage depletion type HEMT chip, a low-voltage enhancement type silicon-based MOSFET with a vertical structure, a TO-220 frame, a DBC double-sided ceramic substrate with a through hole and a groove and a high-heat-conductivity plastic package. And a DBC double-sided ceramic substrate with through holes and grooves is bonded on the TO-220 frame, a GaN-based chip is bonded in the groove of the DBC ceramic substrate, and a silicon-based MOSFET with a vertical structure is stacked on a source electrode of the GaN-based chip TO form a Cascade structure.
The invention is realized by the following technical scheme.
The invention provides a cascade GaN-based power device with a laminated structure, which comprises a GaN-based chip, a silicon-based MOSFET chip, a TO-220 frame and a DCB double-sided ceramic substrate provided with a through hole and a groove.
The laminated structure is that the silicon-based MOSFET chips are laminated on the GaN-based chips in a cascading mode, so that the effects of reducing the chip layout space and reducing the use of inner leads are achieved.
And the back surface of the DBC double-sided copper-clad ceramic substrate provided with the through holes and the grooves is covered with copper, and the front surface of the DBC double-sided copper-clad ceramic substrate is provided with two copper-clad conductive substrates. The copper-clad conductive substrate is electrically connected to the copper-clad layer on the back of the substrate through the through hole, the groove is arranged on the front of the DBC ceramic substrate, the depth of the groove is shallower than the thickness of the DBC substrate, and the groove is not electrically connected with the copper-clad plate on the back.
The base island of the TO-220 framework is connected with the middle pin and is set as a source pin of the GaN-based power device, the left pin is set as a gate pin of the GaN-based power device, and the right pin is set as a drain pin of the GaN-based power device.
The two copper-clad conductive substrates are respectively a first copper-clad conductive substrate and a second copper-clad conductive substrate, the first copper-clad conductive substrate is electrically connected TO the back copper-clad plate through a through hole and is connected TO the source electrode of the silicon-based MOSFET chip and the grid electrode of the GaN chip through an inner lead, the second copper-clad conductive substrate is connected TO the grid electrode of the MOSFET chip and the grid electrode pin of the TO-220 frame through an inner lead, and the drain electrode pin of the TO-220 frame is directly connected TO the drain electrode of the GaN chip through the inner lead.
Preferably, the GaN-based HEMT chip is a high-voltage depletion mode n-channel HEMT (high electron mobility transistor) chip with a horizontal structure, and the top surface includes a gate, a source, and a drain. GaN-based HEMTs with dimensions of 5000-6700 μm and thicknesses of 400-700 μm are provided.
Preferably, the silicon-based MOSFET is a low-voltage enhanced n-channel MOS tube with a vertical structure, a grid electrode and a source electrode are arranged on the top surface of the chip, a drain electrode is arranged on the bottom surface of the chip, the specific size of the silicon-based MOSFET is 1500 mu m-2500 mu m-1500 mu m, the thickness is 200 mu m-400 mu m,
Preferably, the size of the DBC double-sided copper-clad ceramic substrate provided with the through holes and the grooves is the same as that of the frame base island, the specific size is 6000-5000-7300 μm 6300 μm, the thickness is 600-800 μm, the thickness comprises the thickness of the back copper-clad plate and the thickness of the front conductive substrate, copper metal is filled in the through holes, and the back copper-clad layer and the first copper-clad conductive substrate where the through holes of the DBC ceramic substrate are located are electrically connected.
Preferably, the surfaces of the first copper-clad conductive substrate and the second copper-clad conductive substrate on the front surface of the DBC ceramic substrate are plated with gold or silver.
The invention provides a packaging method of a cascade GaN-based power device with a laminated structure, which comprises the following steps:
(1) Bonding the DBC ceramic substrate on the frame base island through conductive solder, and enabling the back surface to face downwards and the right side to face upwards so as to electrically connect the copper-clad plate on the back surface of the substrate with the frame base island;
(2) Bonding a GaN HEMT chip onto the DBC ceramic substrate groove through an insulating adhesive process;
(3) Bonding the silicon-based MOSFET with the right side facing upwards and the back side facing downwards to a GaN source electrode through high-conductivity silver paste to form a laminated cascading structure;
(4) And connecting the drain electrode of the GaN HEMT chip with the lead of the frame drain electrode through an aluminum wire, connecting the grid electrode of the silicon-based MOSFET with the second copper-clad conductive substrate through a copper wire, connecting the second copper-clad conductive substrate with the lead of the frame source electrode through an aluminum wire, connecting the source electrode of the silicon-based MOSFET with the first copper-clad conductive substrate through an aluminum wire, and finally obtaining the cascade GaN-based power device with the laminated structure through plastic package.
Preferably, the conductive solder is solder paste or lead-tin-silver solder, the thickness is 30-50 mu m, and the thickness of the insulating adhesive and the high-conductivity silver paste is 20-40 mu m.
Preferably, the wire diameter of the copper wire is 25-50 mu m, and the wire diameter of the aluminum wire is 100-200 mu m.
Compared with the prior art, the invention has the following beneficial effects and advantages:
(1) The invention provides a new chip layout method, which can adopt the mode that silicon-based MOS tubes are stacked on the source electrode of a GaN HEMT chip in a cascading mode, compared with the prior art, the GaN chip and the silicon-based MOSFET chip with the same size are laid out on the same plane water surface, so that the chip layout space is greatly saved, the selectivity of the packaging form is wider, and the volume of a packaging body is further reduced;
(2) The DBC ceramic substrate is made of a material with high heat conduction performance, the middle of the ceramic substrate is grooved, and the chip is placed in the groove to enable the chip to be fully contacted with the ceramic material, so that good heat diffusion is formed;
(3) The invention uses the DBC double-sided copper-clad ceramic substrate with the through holes, wherein partial electrode copper-clad layers are already arranged on the ceramic substrate, thereby reducing the complexity of process steps in the packaging process and the precision requirement on a press welder, and silver plating is carried out on the surface of the copper-clad conductive substrate, thereby improving the weldability, preventing the copper-clad plate from being not wired due to oxidation and further improving the reliability of products.
(4) According to the invention, the grid lead is led out through the conductive substrate and is electrically connected to the pin through the aluminum inner lead, so that the length of the inner lead is shortened, the grid lead is not easy to break in a subsequent process, and the reliability of the device is improved.
Drawings
FIG. 1 is a schematic circuit diagram of a cascade connection of a HEMT chip and a silicon-based MOSFET chip;
FIG. 2 is a schematic diagram of a conventional cascaded GaN package technique;
FIG. 3 is a schematic top view of a stacked-structure cascaded GaN-based power device according to an example of the invention;
FIGS. 4, 5 and 6 are top, front and left schematic views, respectively, of a DBC ceramic substrate used in examples of the present invention;
fig. 7 and 8 are schematic diagrams of a preparation process of a GaN-based power device with a stacked cascade structure in an example of the invention;
The DCB double-sided ceramic substrate 1, a first conductive copper-clad substrate 2, a through hole 3, a second conductive copper-clad substrate 4, a groove 5, a back copper-clad plate 6, an alumina insulating layer 7, a GaN HEMT 8, a silicon-based MOSFET 9, an aluminum inner lead 10 and a copper inner lead 11 are shown in the figure.
Detailed Description
The following examples are presented to further illustrate the practice of the invention, but are not intended to limit the practice and protection of the invention. It should be noted that the following processes, if not specifically described in detail, can be realized or understood by those skilled in the art with reference to the prior art.
Example 1
As shown in fig. 3, a GaN-based power device of a laminated cascade structure includes a GaN HEMT (high voltage depletion mode GaN-based HEMT chip) 8, a silicon-based MOSFET chip 9, a TO-220 frame, and a DCB double-sided ceramic substrate 1 provided with a through hole 3 and a recess 5.
The stacked structure refers to stacking the silicon-based MOSFET chip 8 onto the GaN-based HEMT chip 8 in accordance with the circuit schematic of fig. 1 using a Cascode (Cascode) cascade connection. Compared with the common mode of placing two chips on the same horizontal plane in the prior art, the chip layout mode with the laminated structure can obviously reduce the space required by the chip layout, and the selection of a chip packaging frame and the chip layout wiring are more redundant.
The GaN-based HEMT8 chip is a high-voltage depletion type n-channel HEMT (high electron mobility transistor) chip with a horizontal structure, the top surface comprises a grid electrode (G2), a source electrode (S2) and a drain electrode (D2), the bottom surface is a silicon substrate, the specific size of the GaN-based HEMT8 chip is 5000 [ mu ] m 2400 [ mu ] m, the thickness of the GaN-based HEMT8 chip is 400 [ mu ] m, the size of the source electrode (S2) is 4300 [ mu ] m 1200 [ mu ] m, the size of the drain electrode (D2) is 4800 [ mu ] m 650 [ mu ] m, and the size of the grid electrode (G2) is 300 [ mu ] m 500 [ mu ] m.
The silicon-based MOSFET9 is a vertical low-voltage enhancement n-channel MOS transistor, the gate (G1) and the source (S1) are on the top surface of the chip, the drain (D1) is on the bottom surface of the chip, the specific size thereof is 1900 μm x 1100 μm, the thickness thereof is 240 μm, the size of the source (S1) is about 1450 μm x 960 μm, the size of the drain (D1) is about 1760 μm x 960 μm, and the size of the gate (G1) is about 250 μm x 300 μm.
As shown in fig. 4,5 and 6, the copper-clad ceramic substrate 1 with two copper-clad double-sided DBC surfaces with through holes and grooves has copper-clad layers on the entire back surface thereof to greatly improve the conductivity of the through holes connected to the frame islands, and in addition, the front surface of the ceramic substrate is provided with two copper-clad electrode pads, namely a first conductive copper-clad substrate 2 and a second conductive copper-clad substrate 4. The first conductive copper-clad substrate is electrically connected to the back of the substrate through a through hole, so that a source electrode (S1) of a subsequent silicon-based MOSFET is conveniently connected to a frame base island through an inner lead, silver plating is arranged on the surfaces of the first conductive copper-clad substrate 2 and the second conductive copper-clad substrate 4, so that the substrate has oxidation resistance and solderability, a groove is formed in the front of the DBC ceramic substrate, and the depth of the groove is shallower than the thickness of the DBC substrate and is not electrically connected with a back copper-clad plate. The size of the DBC ceramic substrate is 6000 mu m, 5000 mu m and 800 mu m, wherein the thickness of the DBC ceramic substrate is 800 mu m, the DBC ceramic substrate comprises a back copper-clad layer of 100 mu m, an aluminum oxide ceramic layer of 600 mu m (an aluminum oxide insulating layer 7) and a front two conductive copper-clad electrodes of 100 mu m, and the size of a groove is 5100 mu m, 2500 mu m and 400 mu m. Specifically, according to the calculation result of the fusing current, the first copper-clad conductive substrate 2 is designed to have a size of 4400 μm by 400 μm by 100 μm, wherein the thickness is 100 μm, the second copper-clad conductive substrate 4 is designed to have a size of 400 μm by 2250 μm by 100 μm, wherein the thickness is 100 μm, the aperture size of the through hole 3 is 200 μm, copper metal is filled in the through hole, and the back copper-clad plate 6 is designed to have a size of 6000 μm by 5000 μm by 100 μm.
The size of the selected TO-220 frame base island is 6000 μm 5000 μm, the base island is connected with the middle pin and is set as a source electrode (S) pin of the GaN-based power device, the left pin is set as a grid electrode (G) pin of the GaN-based power device, and the right pin is set as a drain electrode (D) pin of the GaN-based power device.
Specifically, the first conductive copper-clad substrate 2 is connected TO the source electrode (S1) of the silicon-based MOSFET chip 9 and the gate electrode of the GaN chip 8 through inner leads, the second conductive copper-clad substrate 4 is connected TO the gate electrode (G1) of the MOSFET chip 9 and the gate electrode (G) of the TO-220 frame through inner leads, and the drain electrode (D) of the TO-220 frame is directly connected TO the drain electrode (D2) of the GaN chip 8 through inner leads.
Fig. 7 and 8 are schematic diagrams of a preparation process of a GaN-based power device with a stacked cascade structure in the example of the invention, which includes the following steps:
1) Fixing the HEMT wafer and the silicon-based MOSFET wafer through a blue film and an iron ring frame, and then sending the HEMT wafer and the silicon-based MOSFET wafer to a dicing saw to be separated into single chips, wherein a dicing blade with high hardness is required to be used for dicing when the hard dicing channel of the HEMT wafer is 100 mu m, and a normal-specification blade is required to be used for dicing when the soft dicing channel of the silicon-based MOSFET wafer is 60 mu m.
2) And bonding the DBC ceramic substrate on the frame base island through solder paste at the temperature of 370 ℃, and enabling the copper-clad plate on the back of the substrate to be electrically connected with the frame base island by enabling the back to face downwards and the front to face upwards.
3) The GaN chip was bonded to the DBC ceramic substrate groove by an insulating paste having a thickness of about 20-40 μm as shown in fig. 7.
4) The silicon-based MOSFET is bonded to the GaN source by high conductivity silver paste with the front side facing up and the back side facing down as shown in FIG. 8 to form a stacked and cascaded structure, the silver paste having a thickness of about 20-40 μm.
5) And (3) placing the wafer into an oven after bonding, baking for 3 hours, wherein the baking temperature is 175 ℃, keeping the interior of the oven in a nitrogen environment during baking, and ensuring the oxygen content in the oven to be below 100 ppm. And after baking, taking out after waiting to be cooled to room temperature.
6) After setting the ultrasonic, pressure, time and temperature of the press welder table, the chip waiting for press welding is sent into the guide rail, and then is welded according to the lead connection mode shown in fig. 3. Specifically, the GaN drain electrode (D2) is electrically connected with the frame drain electrode (D) pin through 4 aluminum wires with the wire diameter of 150 mu m, the silicon-based MOSFET gate electrode (G1) is electrically connected with the second conductive substrate 4 through 1 copper inner lead wire 11 with the wire diameter of 25 mu m, the second conductive substrate 4 is electrically connected with the frame gate electrode (G) pin through 1 aluminum inner lead wire 10 with the wire diameter of 150 mu m, and the silicon-based MOSFET source electrode (S) is electrically connected with the first conductive substrate (2) through 4 aluminum wires with the wire diameter of 150 mu m, so that the pressure welding is completed.
7) And (3) carrying out injection molding packaging, flash removal, tin coating and separation on the chip subjected to the steps 1-6 to obtain a finished product.
The above examples are only preferred embodiments of the present invention, and are merely for illustrating the present invention, not for limiting the present invention, and those skilled in the art should not be able to make any changes, substitutions, modifications and the like without departing from the spirit of the present invention.

Claims (8)

1. The cascade GaN-based power device with the laminated structure is characterized by comprising a GaN-based chip, a silicon-based MOSFET chip, a TO-220 frame and a DBC double-sided copper-clad ceramic substrate provided with a through hole and a groove; the silicon-based MOSFET chip is stacked on the GaN-based chip in a cascading mode, the whole copper-clad surface of the back of the DBC double-sided copper-clad ceramic substrate provided with a through hole and a groove is provided with two copper-clad conductive substrates, wherein the first copper-clad conductive substrate is electrically connected TO the back of the DBC double-sided copper-clad ceramic substrate through the through hole, the groove is arranged on the front of the DBC double-sided copper-clad ceramic substrate, the depth of the groove is shallower than the thickness of the DBC double-sided copper-clad ceramic substrate and is not electrically connected with a copper-clad plate on the back, a base island of the TO-220 frame is connected with a middle pin and is set as a source pin of a GaN-based power device, a left pin is set as a grid pin of the GaN-based power device, and a right pin is set as a drain pin of the GaN-based power device, and the two copper-clad conductive substrates are respectively electrically connected TO a source electrode of the silicon-based MOSFET chip and a grid electrode of the silicon-based MOSFET chip through an inner lead;
The preparation method of the cascade GaN-based power device with the laminated structure comprises the following steps:
(1) Bonding a DBC double-sided copper-clad ceramic substrate on a frame base island through conductive solder, wherein the back surface faces downwards and the front surface faces upwards, so that a copper-clad plate on the back surface of the substrate is electrically connected with the frame base island;
(2) Bonding the GaN-based chip to the groove of the DBC double-sided copper-clad ceramic substrate through an insulating adhesive process;
(3) Bonding the silicon-based MOSFET with the right side facing upwards and the back side facing downwards to a GaN source electrode through high-conductivity silver paste to form a laminated cascading structure;
(4) And connecting the drain electrode of the GaN-based chip with the lead of the drain electrode of the frame through an aluminum wire, connecting the grid electrode of the silicon-based MOSFET with the second copper-clad conductive substrate through a copper wire, connecting the second copper-clad conductive substrate with the lead of the source electrode of the frame through an aluminum wire, connecting the source electrode of the silicon-based MOSFET with the first copper-clad conductive substrate through an aluminum wire, and finally obtaining the cascade GaN-based power device with the laminated structure through plastic package.
2. The cascade GaN-based power device of claim 1, wherein the GaN-based chip is a high-voltage depletion n-channel HEMT chip of horizontal structure, the top surface of the GaN-based chip comprises a gate, a source and a drain, and the GaN-based chip has dimensions of 5000 μm 2400 μm to 6700 μm 3000 μm and a thickness of 400 μm to 700 μm.
3. The cascade GaN-based power device with the laminated structure according to claim 1, wherein the silicon-based MOSFET is a low-voltage enhanced n-channel MOS transistor with a vertical structure, a grid electrode and a source electrode are arranged on the top surface of a chip, the drain electrode is arranged on the bottom surface of the chip, the size of the silicon-based MOSFET is 1500 μm-1500 μm, and the thickness of the silicon-based MOSFET is 200 μm-400 μm.
4. The laminated structure cascading GaN-based power device of claim 1, wherein the size of the DBC double-sided copper-clad ceramic substrate with the through holes and the grooves is the same as that of the TO-220 frame base island, the size of the DBC double-sided copper-clad ceramic substrate with the through holes and the grooves is 6000 μm 5000-7300 μm 6300 μm, the thickness is 600-800 μm, the thickness comprises the thickness of a back copper-clad plate and a front conductive substrate, copper metal is filled in the through holes, and the back copper-clad layer and the first copper-clad conductive substrate where the through holes of the DBC double-sided copper-clad ceramic substrate are located are electrically connected.
5. The stacked architecture cascade GaN-based power device of claim 4, wherein the front side first and second copper-clad conductive substrates on the DBC double-sided copper-clad ceramic substrate are surface-plated with gold or silver.
6. A packaging method of the cascade GaN-based power device with a laminated structure as claimed in any one of claims 1 to 5, comprising the steps of:
(1) Bonding a DBC double-sided copper-clad ceramic substrate on a frame base island through conductive solder, wherein the back surface faces downwards and the front surface faces upwards, so that a copper-clad plate on the back surface of the substrate is electrically connected with the frame base island;
(2) Bonding the GaN-based chip to the groove of the DBC double-sided copper-clad ceramic substrate through an insulating adhesive process;
(3) Bonding the silicon-based MOSFET with the right side facing upwards and the back side facing downwards to a GaN source electrode through high-conductivity silver paste to form a laminated cascading structure;
(4) And connecting the drain electrode of the GaN-based chip with the lead of the drain electrode of the frame through an aluminum wire, connecting the grid electrode of the silicon-based MOSFET with the second copper-clad conductive substrate through a copper wire, connecting the second copper-clad conductive substrate with the lead of the source electrode of the frame through an aluminum wire, connecting the source electrode of the silicon-based MOSFET with the first copper-clad conductive substrate through an aluminum wire, and finally obtaining the cascade GaN-based power device with the laminated structure through plastic package.
7. The packaging method according to claim 6, wherein the conductive solder in the step (1) is solder paste or lead-tin-silver solder, the thickness is 30-50 μm, the thickness of the insulating glue in the step (2) is 20-40 μm, and the thickness of the high-conductivity silver paste in the step (3) is 20-40 μm.
8. The packaging method according to claim 6, wherein the wire diameter of the copper wire in the step (4) is 25 μm to 50 μm, and the wire diameter of the aluminum wire is 100 μm to 200 μm.
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