CN111223916B - Semiconductor device and its manufacturing method and three-dimensional memory - Google Patents

Abstract

The invention provides a semiconductor device, a preparation method thereof and a three-dimensional memory device, wherein in the preparation method of the semiconductor device, the etching steps of a grid electrode structure (comprising a grid electrode and offset intervals formed on the side wall of the grid electrode) of a high-voltage area are adjusted to be between the lightly doped drain processing steps and the forming steps of interval side walls, so that the problem that in the prior art, when the bottom grid electrode insulating layers on the two sides of the grid electrode structure of the high-voltage area are etched, unexpected etching is caused to oxide interval side walls (first interval side walls) in the interval side walls of the grid electrode structure and oxide offset intervals in the offset intervals at the same time, and defect grooves are formed on the oxide interval side walls and the tops of the oxide offset intervals can be effectively avoided.

Description

Semiconductor device, manufacturing method thereof, and three-dimensional memory

technical field

The invention belongs to the field of semiconductor design and manufacture, and in particular relates to a semiconductor device, a preparation method thereof and a three-dimensional memory.

Background technique

At present, TAS SPACER ETCH adopts a two-step method to ensure that the expected insulating film spaces (insulating film spaces) and the thickness of the gate insulating layer GOX in the high-voltage area are obtained. However, when the gate insulating layer GOX in the high-voltage area is etched, the The top of the oxide layer of the sidewall offset spacer (generally including the inside-out oxide layer and the nitride layer) is also etched away, so that the oxide layer of the offset spacer and the top of the oxide layer of the spacer sidewall Defects of grooves are formed, which will pose hidden dangers to the stability of subsequent fabricated devices.

Therefore, it is necessary to provide a semiconductor device, its manufacturing method and three-dimensional memory to solve the above-mentioned problems in the prior art.

Contents of the invention

In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor device and its preparation method and three-dimensional memory, which are used to solve the problem of offset spacers and spacer sidewalls (generally The top of the oxide layer including the inside-out oxide layer and the nitride layer) will be etched, thereby forming a groove defect on the top of the oxide layer of the offset spacer and the spacer sidewall, which is harmful to the subsequent fabrication of the device There are technical problems with hidden dangers in stability.

In order to achieve the above purpose and other related purposes, the present invention provides a semiconductor device preparation method, the semiconductor device preparation method comprising:

Provided is a semiconductor structure including a substrate having a first region and a second region, a first gate insulating layer and a second gate insulating layer respectively formed on the first region and the second region , and several discrete gate structures respectively formed on the first gate insulating layer and the second gate insulating layer;

performing lightly doped drain treatment on the first region;

Thinning the first gate insulating layer on both sides of the gate structure on the first region to form a boss structure on the upper surface of the first gate insulating layer;

Wherein, the gate structure on the first gate insulating layer is located on the boss structure, and the lower surface of the gate structure on a boss structure completely covers the upper surface of the boss structure .

In one embodiment, the forming process of the gate structure includes:

forming a plurality of discrete gates on the first gate insulating layer and the second gate insulating layer respectively;

Offset intervals are formed on sidewalls of the gate.

In one embodiment, the step of forming offset intervals on the sidewalls of the gate includes sequentially forming a first offset interval and a second offset interval on the sidewalls of the gate from inside to outside.

In one embodiment, the material of the first offset space includes oxide, and the material of the second offset space includes nitride.

In an embodiment, the material of the gate includes polysilicon.

In one embodiment, the first gate insulating layer on both sides of the gate structure on the first region is thinned so that the upper surface of the first gate insulating layer After forming the protrusion structure, it further includes the step of forming spacer sidewalls on the sidewalls of the gate structure.

In one embodiment, the step of forming spacer sidewalls on the sidewalls of the gate structure includes:

forming a spacer sidewall material layer covering the gate structure, etching and removing the spacer sidewall material layer on the top of the gate structure, so as to separate the gate structure on the first region and the The common sidewall of the boss structure and the sidewall of the gate structure located in the second region form the spacer sidewall.

In one embodiment, the formation of the spacer sidewall material layer covering the gate structure, etching and removal of the spacer sidewall material layer on the top of the gate structure, respectively The common sidewall of the gate structure and the mesa structure and the sidewall of the gate structure located in the second region forming the spacer sidewall include:

forming a first spacer sidewall material layer covering the gate structure;

forming a second spacer sidewall material layer covering the first spacer sidewall material layer;

sequentially etching and removing the second spacer sidewall material layer and the first spacer sidewall material layer located on the top of the gate structure, so as to separate from the gate structure and the protrusion structure located in the first region The common sidewall of the gate structure and the sidewall of the gate structure located in the second region form a first spacer sidewall and a second spacer sidewall from inside to outside.

In an embodiment, the material of the first spacer sidewall includes oxide, and the material of the second spacer sidewall includes nitride.

In an embodiment, the thickness of the first spacer sidewall material layer is smaller than the thickness of the boss structure.

In an embodiment, an isolation structure is formed in the substrate, and the isolation structure divides the substrate into the first region and the second region.

In one embodiment, the isolation structure includes shallow trench isolation.

In an embodiment, before the thinning process is performed, the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.

In one embodiment, the first region is a high pressure region, and the second region is a low pressure region.

In an embodiment, the material of the first gate insulating layer includes oxide, and the material of the second gate insulating layer includes oxide.

In one embodiment, the step of performing lightly doped drain treatment on the first region includes:

forming a patterned mask on the semiconductor structure, the patterned mask exposing the first gate insulating layer and the gate structure formed on the first gate insulating layer;

Lightly doped drain treatment is performed on the first region by using the patterned mask.

In an embodiment, the first gate insulating layer on both sides of the gate structure on the first region is thinned so that the first gate insulating layer The step of forming the boss structure on the surface comprises:

Thinning the first gate insulating layer on both sides of the gate structure on the first region by using the patterned mask.

To achieve the above object and other related objects, the present invention also provides a semiconductor device, which includes:

A semiconductor structure comprising:

a substrate having a first region and a second region;

A first gate insulating layer and a second gate insulating layer respectively located on the first region and the second region, the first gate insulating layer has a main body portion and upwards from the upper surface of the main body portion protrudingly formed boss structures; and

a plurality of discrete gate structures respectively formed on the boss structure of the first gate insulating layer and on the second gate insulating layer;

Wherein, a lightly doped drain region is formed in the substrate on both sides of the gate structure located in the first region, and the lower surface of the gate structure formed above a protrusion structure completely covers The upper surface of the boss structure.

In one embodiment, the gate structure includes a gate and offset spacers formed on sidewalls of the gate.

In one embodiment, the offset interval includes a first offset interval and a second offset interval sequentially formed on the sidewall of the gate from inside to outside.

In one embodiment, the material of the first offset space includes oxide, and the material of the second offset space includes nitride.

In an embodiment, the material of the gate includes polysilicon.

In an embodiment, an isolation structure is formed in the substrate, and the isolation structure divides the substrate into the first region and the second region.

In one embodiment, the isolation structure includes shallow trench isolation.

In an embodiment, the thickness of the first gate insulating layer at the protrusion structure is greater than the thickness of the second gate insulating layer.

In one embodiment, the first region is a high pressure region, and the second region is a low pressure region.

In an embodiment, the material of the first gate insulating layer includes oxide, and the material of the second gate insulating layer includes oxide.

In an embodiment, the semiconductor device further includes spacer sidewalls, and the spacer sidewalls are respectively formed on the common sidewalls of the gate structure and the mesa structure on the first region and on the sidewalls on the first region. sidewalls of the gate structure in the second region.

In one embodiment, the spacer sidewalls are sequentially formed on the common sidewalls of the gate structure and the mesa structure located in the first region and the sidewalls located in the second region in sequence from the inside to the outside. The first spacer sidewall and the second spacer sidewall of the sidewall of the gate structure.

In one embodiment, the bottom surface of the second spacer sidewall is lower than the upper surface of the boss structure.

In an embodiment, the material of the first spacer sidewall includes oxide, and the material of the second spacer sidewall includes nitride.

The present invention also provides a three-dimensional memory prepared by using any one of the semiconductor structures described above.

In the present invention, by optimizing the process steps, the etching step of the gate insulating layer on both sides of the gate structure (including the gate and the offset space formed on the sidewall of the gate) in the high-voltage region is adjusted to the lightly doped drain Between the processing step and the step of forming the spacer sidewall, it is possible to effectively avoid oxidation in the spacer sidewall of the gate structure at the same time when etching the bottom gate insulating layer on both sides of the gate structure in the high-voltage region in the prior art The problem that the oxide spacer sidewall (first spacer sidewall) and the oxide offset space in the offset space cause undesired etching, thereby forming a defect groove on the top of the oxide spacer sidewall and the oxide offset space;

Utilizing the present invention, the etching step of the gate insulation layer on both sides of the gate structure in the high-voltage region and the process step of the lightly doped drain LDD in the high-voltage region can share one mask MASK, thereby reducing the production cost.

Description of drawings

FIG. 1 shows a flow chart of an exemplary fabrication process of a semiconductor device.

FIG. 2 is a schematic structural diagram of a semiconductor device prepared by using the manufacturing process of the semiconductor device in FIG. 1 .

Figure 3 shows an enlarged view of the area indicated by the circle in Figure 2.

FIG. 4 shows a TEM photo of a semiconductor device prepared by using the manufacturing process of the semiconductor device in FIG. 1 .

FIG. 5 is a schematic flowchart of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic diagram of a semiconductor structure in the method for manufacturing a semiconductor device of the present invention.

7 is a schematic cross-sectional view of forming a patterned mask layer on a semiconductor structure in the method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a schematic cross-sectional view of lightly doped and drain-treated the first region by using a patterned mask layer in the manufacturing method of the semiconductor device of the present invention.

FIG. 9 shows the results of thinning the first gate insulating layer on both sides of the gate structure on the first region by using a patterned mask layer in the method for manufacturing a semiconductor device of the present invention. Cross-sectional schematic.

10 is a schematic cross-sectional view after forming a spacer sidewall material layer covering the gate structure in the manufacturing method of the semiconductor device of the present invention.

FIG. 11 is a schematic cross-sectional view of forming spacer sidewalls with the sidewalls of the gate structure in the manufacturing method of the semiconductor device of the present invention.

FIG. 12 shows a TEM photograph of a semiconductor device prepared by using the method for preparing a semiconductor device of the present invention.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and size of the components in actual implementation Drawing, the shape, quantity and proportion of each component can be changed arbitrarily during its actual implementation, and the layout of components may also be more complicated.

Fig. 1 shows a schematic flow chart of a method for preparing a semiconductor device in TAS SPACER ETCH. The method for preparing a semiconductor device comprises the following steps:

Step 1, providing a semiconductor structure, which includes a substrate 1' having a high-voltage region and a low-voltage region, a first gate insulating layer 81' and a second gate insulating layer 81' formed on the high-voltage region and the low-voltage region, respectively. The gate insulating layer 82', and several discrete gate structures respectively formed on the first gate insulating layer 81' and the second gate insulating layer 82', wherein the substrate 1' passes The shallow trench isolation 2' disposed therein is divided into a high-voltage region A1 and a low-voltage region A2, and the gate structure includes a gate 3' and offset spacers formed on sidewalls on both sides of the gate 3' , the offset interval includes but not limited to oxide offset interval 4' and nitride offset interval 5';

Step 2, forming a patterned first mask exposing the high-voltage region A1 on the semiconductor structure by using a photolithography process;

Step 3, using the first mask to perform lightly doped drain ion implantation (HV LDD IMP) on the high voltage region A1 to form lightly doped drains in the substrate 1' on both sides of the gate structure on the high voltage region A1 area (not shown), in addition, the first mask needs to be removed and a cleaning process is performed before performing step 4;

Step 4, forming a spacer sidewall material layer on the gate structures in the two regions, specifically, first forming an oxide layer on the gate structures in the two regions, and then forming a layer on the surface of the oxide layer forming a nitride layer;

Step 5, etching the spacer sidewall material layer to form spacer sidewalls on the sidewalls of the gate structures in the two regions, the spacer sidewalls include but not limited to oxide spacer sidewalls 6' and nitride spacer side wall 7';

Step 6, forming a second mask exposing the high voltage region A1 on the structure formed in step 5 through a photolithography process;

Step 7, use the second mask to thin the first gate insulating layer 81' in the high-voltage region to form the semiconductor device shown in Figure 2, and after this step, it is also necessary to perform mask removal and cleaning processes . Please refer to FIG. 2, the upper surface of the first gate insulating layer 81' is formed with a boss structure 812'; wherein, the gate structure on the first gate insulating layer 81' and its two sides The spacer sidewalls are located on the boss structure 812', and the common lower surface of the gate structure on one of the boss structures 812' and the spacer sidewalls on both sides is the same as the upper surface of the boss structure 812'. coincide.

In the above process steps, in step 7, when the first gate insulating layer 81' of the high voltage region A1 is thinned, the offset spacers and spacer sidewalls of the high voltage region A1 are also exposed by the second mask , the tops of the oxide offset spacers 4' and oxide spacer sidewalls 6' in the offset spacers and spacer sidewalls are also etched away, thereby forming defects on top of the oxide offset spacers 4' (not shown ), will also form defects 61' on the top of the oxide spacer sidewall 6', which will have an adverse effect on the stability of the subsequent semiconductor device; mold), which increases the production process steps, thereby increasing the production cost.

Based on this, as shown in FIG. 5, the present invention provides a semiconductor device and its preparation method and a three-dimensional memory, the gate structure of the high-voltage region (including the gate 3 and the offset interval formed on the sidewall of the gate 3 ) The etching step of the gate insulating layer on both sides is adjusted between the lightly doped drain processing step and the formation step of the spacer sidewall, which can effectively avoid the bottom gate on both sides of the gate structure in the high-voltage region in the prior art When the insulating layer is used, it will cause undesired etching to the oxide spacer sidewall (first spacer sidewall 6) in the spacer sidewall of the gate structure and the oxide offset spacer in the offset space at the same time, so that in the oxide Problems with spacer sidewalls and tops of oxide offset spacers forming defect recesses. The technical solutions of the present invention will be described below in conjunction with specific embodiments.

Embodiment one

Please refer to FIG. 5, this embodiment provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device includes:

Step S10, providing a semiconductor structure, the semiconductor structure comprising a substrate 1 having a first region A1 and a second region A2, a first gate insulating layer respectively formed on the first region A1 and the second region A2 layer 81 and the second gate insulating layer 82, and several discrete gate structures respectively formed on the first gate insulating layer 81 and the second gate insulating layer 82;

Step S20, performing lightly doped drain treatment LDD on the first region A1;

Step S30, thinning the first gate insulating layer 81 on both sides of the gate structure on the first region A1, so as to form protrusions on the top of the first gate insulating layer 81. mesa structure 812; wherein, the gate structure on the first gate insulating layer 81 is located on the mesa structure 812, and the lower surface of the gate structure on the mesa structure 812 is completely covered The upper surface of the boss structure 812 .

The manufacturing method of the semiconductor device of this embodiment will be described in detail below with reference to the accompanying drawings, wherein FIGS. 6-11 are structural cross-sectional views of the semiconductor device during the manufacturing process of the semiconductor device according to this embodiment.

In step S10, referring to FIG. 6, a semiconductor structure is provided, the semiconductor structure includes a substrate 1 at the bottom, the substrate 1 is, for example, a semiconductor substrate 1, and the semiconductor substrate is divided into two regions, They are respectively a high-voltage area (that is, the first area A1 ) for forming high-voltage components (such as high-voltage transistors) and a low-voltage area (second area A2 ) for forming low-voltage components. It should be noted that the substrate 1 can be selected according to the actual requirements of the device, and the substrate 1 can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon- on-insulator, silicon-on-insulator) substrate or GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc., in other embodiments, the substrate 1 can also include other elemental semiconductors or compound semiconductors Substrate, such as gallium arsenide, indium phosphide or silicon carbide, etc., the substrate 1 can also be a stacked structure, such as silicon/germanium silicon stack, etc., in this embodiment, the substrate 1 includes single crystal silicon substrate. In addition, the substrate 1 may be a substrate after ion doping, which may be P-type doped or N-type doped.

It should be noted that although in this embodiment, the first area A1 is a high-pressure area and the second area A2 is a low-pressure area, in other embodiments, the first area A1 and the second Area A2 may also be divided in other forms.

Referring to FIG. 6 , an isolation structure is formed in the substrate 1 , and the substrate 1 is divided into high and low voltage regions by the isolation structure. As an example, the isolation structure may be, for example, shallow trench isolation 2, through which the substrate 1 is divided into the first region A1 and the second region A2, and the process of forming the shallow trench isolation 2 region includes an isolation oxide layer Process steps such as deposition, mask layer deposition (such as nitride), etching to form grooves, filling and depositing insulating materials (such as oxides) in the grooves, and planarization.

Please refer to FIG. 6. In this embodiment, shallow trench isolation 2 is selected as the isolation structure. Before performing the etching thinning process, the height of shallow trench isolation 2 is higher than the first The gate insulating layer 81 and the second gate insulating layer 82 on the second region A2. It should be noted that, in some embodiments, the height of the shallow trench isolation 2 can be adjusted according to actual needs; in some embodiments, the shallow trench isolation 2 can also be replaced by other forms of isolation structures.

Referring to FIG. 6, a high-voltage gate insulating layer is formed on the high-voltage region of the substrate 1 as a first gate insulating layer 81, and a low-voltage gate insulating layer is formed on the high-voltage region of the substrate 1 as a second gate insulating layer. Gate insulating layer 82; the thickness of the high-voltage gate insulating layer and the low-voltage gate insulating layer is related to the turn-on voltage or threshold voltage of the components formed in this region. Generally, the thicker the gate insulating layer is, the The corresponding turn-on voltage is also higher, so the thickness of the first gate insulating layer 81 disposed on the surface of the high voltage region is greater than the thickness of the second gate insulating layer 82 disposed on the surface of the low voltage region. As an example, the material of the first and second gate insulating layers 82 may be oxide, for example. In a specific example, the material of the first and second gate insulating layers 81 and 82 may be, for example, silicon dioxide.

In step S10, please refer to FIG. 6 , the forming process of the gate structure includes: forming a plurality of discrete gates 3 on the first gate insulating layer 81 and the second gate insulating layer 82 respectively; Offset intervals are formed on sidewalls of the gate 3 . As an example, for example, a gate material layer may be formed on the first gate insulating layer 81 and the second gate insulating layer 82 respectively, and then through an etching process, the first gate insulating layer 81 and the Several discrete gates 3 are formed on the second gate insulating layer 82 . As an example, the material of the gate material layer may include polysilicon, for example. It should be noted that, in an example, the step of forming several discrete gates 3 on the first gate insulating layer 81 and the second gate insulating layer 82 may be performed in the same process step. Several discrete gates 3 are formed on the first gate insulating layer 81 and the second gate insulating layer 82, and the gates on the first gate insulating layer 81 and the second gate insulating layer 82 have the same structure; in another example, the step of forming several discrete gates 3 on the first gate insulating layer 81 and the second gate insulating layer 82 may also be performed under different process steps. Form the gate 3 on the first gate insulating layer 81 and the gate 3 on the second gate insulating layer 82. When different process steps are used, the gate on the first gate insulating layer 81 The electrode 3 and the gate 3 on the second gate insulating layer 82 may have the same structure or different structures.

In step S10 , the step of forming offset intervals on the sidewalls of the gate 3 includes sequentially forming a first offset interval 4 and a second offset interval 5 on the sidewalls of the gate 3 from inside to outside. As an example, the material of the first offset space 4 includes but not limited to oxide, such as silicon dioxide; the material of the second offset space 5 includes but not limited to nitride, such as silicon nitride. In an example, a first offset spacer material layer covering the gate 3 and other exposed regions of the semiconductor structure may be deposited on the gate 3 prior to the two regions, and then on the first offset spacer layer Continue to deposit the second offset spacer material layer, and finally, sequentially etch and remove the second offset spacer material layer and the first offset spacer material layer covering the top of the gate 3 and both sides of the gate 3, so that the two regions A first offset space 4 and a second offset space 5 are sequentially formed on the sidewalls of the gate 3 from inside to outside. In another example, the first offset spacer material layer covering the gate 3 and other exposed regions of the semiconductor structure may also be deposited on the gate 3 in the two regions, and then etched to remove the top of the gate 3 and the The first offset spacer material layer on both sides of the gate 3, so that the first offset spacers 4 are sequentially formed on the sidewalls of the gate 3 in the two regions from the inside to the outside; then, the structure surface formed in the previous step forming a second offset spacer material layer, and then etching and removing the second offset spacer material layer covering the top of the gate 3 and the exposed sidewalls of the first offset spacer 4, so that the first offset in the two regions A second offset spacer 5 is formed on the exposed sidewall of the spacer 4 . It should be noted that, for example, the first bias can be formed by using a process such as a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process or an atomic layer deposition (Atomic Layer Deposition, ALD). offset layer of spacer material and the second offset layer of spacer material. It should be noted that as the size of the device becomes smaller, the reachable length of the device becomes smaller and smaller, and the ion implantation depth of the source and drain electrodes becomes smaller and smaller. The function of the offset interval is to improve the channel of the formed transistor. length, reducing the short channel effect and the hot carrier effect caused by the short channel effect.

In step S20, please refer to FIGS. 7 and 8. As the width of the gate 3 decreases continuously, the length of the channel under the gate 3 decreases continuously. In order to effectively prevent the short channel effect, it is necessary to A region A1 is subjected to lightly doped drain LDD treatment (with the downward arrow in FIG. 8 ), and the step of performing lightly doped drain LDD treatment on the first region A1 includes forming a patterned mask on the semiconductor structure 9. The patterned mask 9 exposes the first gate insulating layer 81 and the gate structure formed on the first gate insulating layer 81; The lightly doped drain treatment is performed on the first region A1. As an example, for example, the patterned mask 9 can be formed by a photolithography process, and the material of the patterned mask 9 can be photoresist PH, for example. In other examples, the patterned mask 9 can also use other suitable masking material. As an example, the method for forming the LDD may be an ion implantation process or a diffusion process, and the ion implantation process may be completed in one or more steps according to the concentration of dopant ions required. As an example, when performing lightly doped drain LDD treatment, large-mass dopant ions can be used, and the shallow junction formed by the combination of large-mass materials and the amorphous state of the surface of the substrate 1 can be used to reduce the channel leakage current effect between the source and drain . As an example, lightly doped drain implantation LDD can be divided into n-lightly doped drain implantation N-LDD, and p-lightly doped drain implantation P-LDD; when performing N-LDD implantation, phosphorus, arsenic, antimony One or a combination of bismuth, for example, arsenic ions are selected, and arsenic ions are implanted in the area not protected by the patterned mask 9 (such as photoresist) to form a low-energy shallow junction, and arsenic is selected as the N-LDD The implantation of ions is because the high molecular weight of arsenic is conducive to the amorphization of the silicon surface, and a more uniform doping depth can be obtained during the implantation; while in the P-LDD implantation, boron fluoride, which is easier to amorphize the silicon surface, is used. Ion implantation is performed to form a low-energy shallow junction. It should be noted that after the ion implantation is completed, a step of annealing the device after the ion implantation is also included, so as to eliminate semiconductor defects caused by the ion implantation and activate the implanted ions.

In step S30, referring to FIG. 9 , the first gate insulating layer 81 on both sides of the gate structure on the first region A1 is thinned so as to The step of forming the boss structure 812 on the upper surface of the gate insulating layer 81 includes: using the patterned mask 9 to align the first gates on both sides of the gate structure on the first region A1 The insulating layer 81 is thinned to form a boss structure 812 on the upper surface of the first gate insulating layer 81 . As an example, the thinning process may, for example, use a dry etching process to etch the first gate insulating layer 81 exposed by the patterned mask 9, and the gate structure (gate 3 and the offset intervals on both sides) can effectively protect the part of the first gate insulating layer 81 directly below it from being etched, so that only the first gate insulation on both sides of the gate structure on the first region A1 is etched. layer 81 is etched, thereby forming a boss structure 812, the lower surface of the gate structure on the boss structure 812 completely covers the upper surface of the boss structure 812, that is, a gate structure on the boss structure 812 The area of the lower surface of the gate structure is greater than or equal to the area of the upper surface of the protrusion structure 812 . As an example, during the thinning process, the thickness of the first gate insulating layer 81 on both sides of the gate structure, that is, the thickness of the main body portion 811 can be controlled by controlling the etching parameters. As an example, when the first gate insulating layer 81 on both sides of the gate structure on the first region A1 is thinned, the shallow trench isolation 2 in the region will also be thinned. The top is etched simultaneously, so that the surface of the shallow trench isolation 2 in the first region A1 is lower than the surface of the shallow trench isolation 2 in the second region A2. It should be noted that, in the process of thinning the first gate insulating layer 81 on both sides of the gate structure on the first region A1, the bias on both sides of the gate 3 will be Etching the top of the oxide layer OX in the offset space (the first offset space 4) will form a groove defect (not shown in the figure) on the top of the oxide layer in the offset space, but the groove defect will be in In the subsequent step S40 , the first spacer sidewall material layer 60 (usually oxide) is filled, so as to make up for this defect.

It should be noted that, in this embodiment, step S20 and step S30 use the same patterned mask 9 to perform LDD treatment in the high-voltage region and thinning treatment of the first gate insulating layer 81 in the high-voltage region, effectively reducing the production cost . Of course, in other embodiments, in step S20 and step S30, different patterned masks 9 can also be used respectively, so that after the LDD treatment in the high voltage area, the mask material on the semiconductor device needs to be removed first, and then after cleaning, A new patterned mask 9 is remade, and the first gate insulating layer 81 in the high voltage region is thinned using the new patterned mask 9 .

Referring to FIG. 5 , the first gate insulating layer 81 on both sides of the gate structure on the first region A1 is thinned so that the first gate insulating layer 81 After forming the convex structure 812 on the surface, in order to prevent the large dose of source-drain implantation from being too close to the channel, resulting in the channel being too short or even the source-drain being connected, a step S40 is also included: forming spacer sidewalls on the sidewalls of the gate structure .

In step S40, the step of forming spacer sidewalls on the sidewalls of the gate structure includes first forming a spacer sidewall material layer covering the gate structure; etching and removing the spacer sidewall material on the top of the gate structure layer, so as to form the spacer sidewall on the sidewall of the gate structure; wherein, in addition to covering the gate structure, the material layer of the spacer sidewall also covers the exposed surface of the semiconductor device on both sides of the gate structure and the raised The sidewalls of the mesa structure 812, the spacer sidewalls formed after etching are also formed on the sidewalls of the above-mentioned boss structure 812, in other words, the spacer sidewalls are respectively formed on the sidewalls located on the first region A1. The common sidewall of the gate structure and the protrusion structure 812 and the sidewall of the gate structure located in the second region A2.

Specifically, in this embodiment, referring to FIG. 10 and FIG. 11 , the formation of the spacer sidewall material layer covering the gate structure is performed, and the spacer sidewall material layer on the top of the gate structure is etched away, so that The step of forming the spacer sidewall on the sidewall of the gate structure includes: forming a first spacer sidewall material layer 60 covering the gate structure, wherein the first spacer sidewall material layer 60 covers the gate In addition to the pole structure, it also covers the exposed surface of the semiconductor device on both sides of the gate structure and the sidewall of the above-mentioned protrusion structure 812; forms a second spacer sidewall material layer 70 covering the first spacer sidewall material layer 60; Etching and removing the second spacer sidewall material layer 70 and the first spacer sidewall material layer 60 located on the top of the gate structure, so as to separate from the gate structure located in the first region A1 and the protrusion The common sidewall of the mesa structure 812 and the sidewall of the gate structure located in the second region A2 form a first spacer sidewall 6 and a second spacer sidewall 7 from inside to outside. As an example, the material of the first spacer sidewall 6 includes but not limited to oxide, such as silicon dioxide; the material of the second spacer sidewall 7 includes but not limited to nitride, such as silicon nitride. Please refer to FIG. 11 , among the spacer sidewalls formed, the first spacer sidewall 6 has an L shape; the bottom surface of the horizontal part of the first spacer sidewall 6 is in contact with the first grid 3 oxide The top surface of the main body part 811 is flush, and the top exposed surface of the horizontal part of the first partition side wall 6 is formed with the second partition side wall 7, the second partition side wall 7 and the first partition side wall 7 The sidewalls of the vertical portions of the spacer sidewalls 6 are in contact. Please refer to FIG. 11 , in an example, the thickness of the first spacer sidewall material layer is much smaller than the thickness of the boss structure 812, therefore, the height of the bottom of the second spacer sidewall 7 is much lower than the Referring to the top surface of the boss structure 812, it can be understood that, in other examples, the thickness of the first spacer sidewall material layer can be adjusted as required. In a specific example, the thickness of the first spacer sidewall 6 is, for example, between 9-12 nm, the thickness of the boss structure 812 is between 36-45 nm, and the thickness of the second spacer sidewall 7 is 25-12 nm. The height difference between the bottom of the second spacer sidewall 7 and the protrusion structure 812 is between 24-36 nm. Wherein, Fig. 12 shows the TEM photo of the semiconductor device prepared by the method of this embodiment, it can be seen that in the semiconductor device obtained by the preparation method of this embodiment, the first spacer sidewall 6 and the second spacer There is no gap at the top of an offset interval 4. Therefore, the preparation method of this embodiment can effectively solve the problem existing in the preparation process shown in FIG. When the pole insulating layer is used, the oxide spacer sidewall (first spacer sidewall 6) and the oxide spacer (first spacer spacer 4) in the spacer sidewall of the gate structure will be offset at the same time. The top is etched, and groove defects are formed at the corresponding positions, which affects the stability of the device.

It should be noted that, in other embodiments, the formation of the spacer sidewall material layer covering the gate structure is performed, and the spacer sidewall material layer on the top of the gate structure is etched away to facilitate the gate structure. The step of forming the spacer sidewall on the sidewall includes: firstly forming a first spacer sidewall material layer 60 covering the gate structure, and etching and removing the first spacer sidewall material layer 60 at the top of the gate structure , forming the second gate structure in the first region A1 and the sidewall of the protrusion structure 812 in the first region A1 and the sidewall of the gate structure in the second region A2 from inside to outside. A spacer sidewall 6; Next, form a second spacer sidewall material layer 70 covering the first spacer sidewall 6 and the gate structure, etch to remove the top of the gate structure and the first spacer side The second spacer sidewall material layer 70 on the top of the wall 6 is used to form the second spacer sidewall 7 on the exposed sidewall of the first spacer sidewall 6, and the first spacer sidewall 6 and the second spacer sidewall The bottom surface of the spacer sidewall 7 is flush with the surface of the first gate insulating layer 81 on both sides of the ion-thinned mesa structure 812, that is, the height of the bottom of the second spacer sidewall 7 is also much lower than the The top surface of the boss structure 812 .

Embodiment two

Please refer to FIG. 11, this embodiment also provides a semiconductor device prepared by using the preparation method described in the embodiment, and the semiconductor device includes:

A semiconductor structure comprising:

a substrate 1 having a first area A1 and a second area A2;

The first gate insulating layer 81 and the second gate insulating layer 82 respectively located on the first region A1 and the second region A2, the first gate insulating layer 81 has a main body portion 811 and the a boss structure 812 protruding upward from the upper surface of the main body 811; and

a plurality of discrete gate structures respectively formed on the boss structure 812 of the first gate insulating layer 81 and on the second gate insulating layer 82;

Wherein, the lower surface of the gate structure formed above the protrusion structure 812 completely covers the upper surface of the protrusion structure 812 .

Please refer to FIG. 11 , the semiconductor structure includes a substrate 1 at the bottom, the substrate 1 is, for example, a semiconductor substrate 1, and the semiconductor substrate 1 is divided into two regions, which are respectively used to form high-voltage components. (for example, a high-voltage transistor) in a high-voltage region (that is, the first region A1 ) and a low-voltage region (second region A2 ) in which low-voltage components are formed. It should be noted that the substrate 1 can be selected according to the actual requirements of the device, and the substrate 1 can include silicon lining, germanium (Ge) substrate, silicon germanium (SiGe) substrate, SOI (Silicon-on -insulator, silicon-on-insulator) substrate or GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc., in other embodiments, the substrate 1 can also be a substrate including other elemental semiconductors or compound semiconductors base, such as gallium arsenide, indium phosphide or silicon carbide, etc., the substrate 1 can also be a stacked structure, such as silicon/germanium silicon stack, etc., in this embodiment, the substrate 1 includes a single crystal silicon substrate end. In addition, the substrate 1 may be a substrate after ion doping, which may be P-type doped or N-type doped.

It should be noted that although in this embodiment, the first area A1 is a high-pressure area and the second area A2 is a low-pressure area, in other embodiments, the first area A1 and the second Area A2 may also be divided in other forms.

Referring to FIG. 11 , an isolation structure is formed in the substrate 1 , and the substrate 1 is divided into high and low voltage regions by the isolation structure. As an example, the isolation structure may be, for example, shallow trench isolation 2, through which the substrate 1 is divided into the first region A1 and the second region A2, and the process of forming the shallow trench isolation 2 region includes an isolation oxide layer Process steps such as deposition, mask layer deposition (such as nitride), etching to form grooves, filling and depositing insulating materials (such as oxides) in the grooves, and planarization. Please refer to FIG. 11 , in this embodiment, the isolation structure is selected as shallow trench isolation 2 , and the shallow trench isolation 2 can also be replaced by other forms of isolation structures.

Please refer to FIG. 11 , the high-voltage gate insulating layer (first gate insulating layer 81 ) at the bottom of the gate structure in the high-voltage area and the low-voltage gate insulating layer (second gate insulating layer 82 ) at the bottom of the gate structure in the low-voltage area. The thickness of the gate insulating layer is related to the turn-on voltage or threshold voltage of the components formed in this area. Generally, the thicker the gate insulating layer is, the higher the corresponding turn-on voltage is. The thickness of the high-voltage gate insulating layer (that is, the sum of the thicknesses of the boss structure 812 and the main body portion 11 at the bottom) is greater than the thickness of the low-voltage gate insulating layer located at the bottom of the gate structure disposed in the low-voltage region, that is, the above-mentioned The thickness of the first gate structure 81 at the protrusion structure 812 is greater than the thickness of the second gate insulating layer 82 . As an example, the material of the first and second gate insulating layers 82 may be oxide, for example. In a specific example, the material of the first and second gate insulating layers 82 may be, for example, silicon dioxide.

It should be noted that the gate structure includes a gate 3 and an offset interval formed on a sidewall of the gate 3 . As an example, the material of the gate 3 includes polysilicon. As an example, the offset interval includes a first offset interval 4 and a second offset interval 5 that are sequentially formed on the sidewall of the gate 3 from inside to outside, and the material of the first offset interval 4 includes but Not limited to oxide (such as silicon dioxide), the second offset spacer 5 includes but not limited to nitride (such as silicon nitride). It should be noted that as the size of the device becomes smaller, the reachable length of the device becomes smaller and smaller, and the ion implantation depth of the source and drain electrodes becomes smaller and smaller. The function of the offset interval is to improve the channel of the formed transistor. length, reducing the short channel effect and the hot carrier effect caused by the short channel effect. For the formation process of the offset interval, refer to the related part of Embodiment 1 for details, which will not be described again.

It should be noted that as the width of the gate 3 decreases continuously, the length of the channel under the gate 3 decreases continuously. In order to effectively prevent the short channel effect, the first region A1 needs to be lightly doped Drain LDD treatment (indicated by the downward arrow in FIG. 8 ), the first region A1 is also subjected to lightly doped drain LDD treatment, so that LDD regions are formed in the substrate 1 on both sides of the gate structure of the high voltage region ( not shown). It should be noted that, for the lightly doped drain LDD treatment process for the first region A1 , refer to the relevant part in the embodiment for details, and details are not repeated here.

Please refer to FIG. 11 , in order to prevent the source and drain implantation of a large dose from being too close to the channel, resulting in the channel being too short or even the source and drain being connected, the semiconductor device further includes spacer sidewalls, and the spacer sidewalls are formed at the first The sidewalls of the gate structure and the boss structure 812 in the region A1 and the sidewalls of the gate structure in the second region A2, that is, in the first region A1, the spacer sidewalls The sidewalls on both sides of the gate structure on the first region A1 and the sidewalls on both sides of the boss structure 812 below the gate structure are formed, while in the second region A2 the spacer sidewalls are formed on the second Two sidewalls of the gate structure on the region A2. As an example, the spacer sidewalls include the sidewalls of the gate structure and the mesa structure 812 on the first region A1 and the sidewalls of the second region A2 that are sequentially formed from the inside to the outside. The first spacer sidewall 6 and the second spacer sidewall 7 are the sidewalls of the gate structure. As an example, the material of the first spacer sidewall 6 includes but not limited to oxide, such as silicon dioxide; the material of the second spacer sidewall 7 includes but not limited to nitride, such as silicon nitride. Please refer to FIG. 11 , among the spacer sidewalls formed, the first spacer sidewall 6 has an L shape; the bottom surface of the horizontal part of the first spacer sidewall 6 is in contact with the first grid 3 oxide The top surface of the main body part 811 is flush, and the top exposed surface of the horizontal part of the first partition side wall 6 is formed with the second partition side wall 7, the second partition side wall 7 and the first partition side wall 7 The sidewalls of the vertical portions of the spacer sidewalls 6 are in contact. Please refer to FIG. 11 , since the thickness of the first spacer sidewall 6 is much thinner than the thickness of the first gate insulating layer 81 at the position of the boss structure 812 , the height of the bottom of the second spacer sidewall 7 Much lower than the top surface of the boss structure 812 . In a specific example, the thickness of the first spacer sidewall 6 is, for example, between 9-12 nm, the thickness of the boss structure 812 is between 36-45 nm, and the thickness of the second spacer sidewall 7 is 25-12 nm. The height difference between the bottom of the second spacer sidewall 7 and the protrusion structure 812 is between 24-36 nm. Wherein, Fig. 12 shows the TEM photo of the semiconductor device prepared by the method of this embodiment, it can be seen that in the semiconductor device obtained by the preparation method of this embodiment, the first spacer sidewall 6 and the second spacer There is no gap at the top of an offset interval 4. Therefore, the preparation method of this embodiment can effectively solve the problem existing in the preparation process shown in FIG. When the insulating layer is used, the oxide spacer sidewall (first spacer sidewall 6) in the spacer sidewall of the gate structure and the top of the oxide offset spacer (first offset spacer 4) in the offset spacer will be simultaneously Etching is performed to form groove defects at corresponding positions, which affects device stability. It should be noted that, for the formation process of the spacer sidewalls, refer to the relevant part above, and will not be repeated here.

It should be noted that, in other embodiments, the first partition sidewall 6 and the second partition sidewall 7 are parallel structures, and the first partition sidewall 6 and the second partition sidewall 7 The bottoms are respectively in direct contact with the surface of the main body portion 811 of the second gate insulating layer 81 , that is, the height of the bottom of the second spacer sidewall 7 is also much lower than the top surface of the protrusion structure 812 .

It should be noted that the semiconductor device in this embodiment can be used as an intermediate structure in the manufacturing process of the three-dimensional memory.

To sum up, in the present invention, by optimizing the process, the etching of the gate insulating layer on both sides of the gate structure in the high-voltage region (including the gate 3 and the offset interval formed on the sidewall of the gate 3) The step is adjusted between the lightly doped drain processing step and the step of forming the sidewall of the spacer, which can effectively avoid the simultaneous etching of the gate structure when etching the bottom gate insulating layers on both sides of the gate structure in the high-voltage region in the prior art. The oxide spacer sidewall (first spacer sidewall 6) in the spacer sidewall and the oxide offset space in the offset space cause undesired etching, so that the oxide spacer sidewall and the oxide offset spacer Problem with top forming defect grooves. In addition, in the present invention, the etching step of the gate insulating layer on both sides of the gate structure in the high-voltage region and the process step of the lightly doped drain LDD in the high-voltage region share a mask MASK to reduce production costs. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (30)

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor structure comprising a substrate having a first region and a second region, a first gate insulating layer and a second gate insulating layer formed on the first region and the second region, respectively, and a plurality of discrete gate structures formed on the first gate insulating layer and the second gate insulating layer, respectively;

lightly doping and leaking the first area;

thinning the first gate insulating layers positioned on two sides of the gate structure on the first region to form a boss structure on the upper surface of the first gate insulating layer;

The first grid electrode insulating layer is arranged on the first grid electrode insulating layer, the first grid electrode insulating layer is arranged on the boss structure, and the lower surface of the first grid electrode insulating layer completely covers the upper surface of the boss structure.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of the gate structure comprises:

forming a plurality of discrete gates on the first gate insulating layer and the second gate insulating layer, respectively;

and forming offset intervals on the side walls of the grid electrode.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the offset interval on the sidewall of the gate electrode includes sequentially forming a first offset interval and a second offset interval from inside to outside on the sidewall of the gate electrode.

4. The method of manufacturing a semiconductor device according to claim 3, wherein the material of the first offset spacers comprises an oxide and the second offset spacers comprises a nitride.

5. The method of manufacturing a semiconductor device according to claim 2, wherein the material of the gate electrode comprises polysilicon.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate insulating layer on both sides of the gate structure on the first region is thinned to form a spacer sidewall on a sidewall of the gate structure after the boss structure is formed on the upper surface of the first gate insulating layer.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming spacer sidewalls on the sidewalls of the gate structure comprises:

and forming a spacer side wall material layer covering the gate structure, and etching to remove the spacer side wall material layer on the top of the gate structure so as to form the spacer side wall on the common side wall of the gate structure and the boss structure on the first region and the side wall of the gate structure on the second region respectively.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming a spacer sidewall material layer covering the gate structure, etching away the spacer sidewall material layer on top of the gate structure to form the spacer sidewall on a common sidewall of the gate structure and the mesa structure on the first region and a sidewall of the gate structure on the second region, respectively, comprises:

forming a first spacer sidewall material layer overlying the gate structure;

forming a second spacer sidewall material layer overlying the first spacer sidewall material layer;

and sequentially etching and removing the second interval side wall material layer and the first interval side wall material layer which are positioned at the top of the grid electrode structure, so as to form a first interval side wall and a second interval side wall from inside to outside on the common side wall of the grid electrode structure and the boss structure which are positioned in the first area and the side wall of the grid electrode structure which is positioned in the second area.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the material of the first spacer sidewall comprises an oxide and the material of the second spacer sidewall comprises a nitride.

10. The method of manufacturing a semiconductor device according to claim 8, wherein a thickness of the first spacer sidewall material layer is smaller than a thickness of the mesa structure.

11. The method of manufacturing a semiconductor device according to claim 1, wherein an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.

12. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first gate insulating layer is larger than a thickness of the second gate insulating layer before the thinning process is performed.

13. The method of manufacturing a semiconductor device according to claim 1, wherein the first region is a high-voltage region and the second region is a low-voltage region.

14. The method of manufacturing a semiconductor device according to claim 1, wherein a material of the first gate insulating layer includes an oxide, and a material of the second gate insulating layer includes an oxide.

15. The method for manufacturing a semiconductor device according to any one of claims 1 to 14, wherein the step of lightly doping the first region includes:

forming a patterned mask on the semiconductor structure, wherein the patterned mask exposes the first gate insulating layer and the gate structure formed on the first gate insulating layer;

and carrying out lightly doped drain treatment on the first region by utilizing the patterned mask.

16. The method of manufacturing a semiconductor device according to claim 15, wherein the step of thinning the first gate insulating layer on both sides of the gate structure on the first region to form a bump structure on an upper surface of the first gate insulating layer comprises:

and thinning the first gate insulating layer positioned on two sides of the gate structure on the first region by using the patterned mask so as to form a boss structure on the upper surface of the first gate insulating layer.

17. A semiconductor device, the semiconductor device comprising:

a semiconductor structure, the semiconductor structure comprising:

A substrate having a first region and a second region;

a first gate insulating layer and a second gate insulating layer respectively located on the first region and the second region, the first gate insulating layer having a main body portion and a boss structure protruding upward from an upper surface of the main body portion; and

a plurality of discrete gate structures formed on the boss structure of the first gate insulating layer and the second gate insulating layer, respectively;

and the substrate positioned at the two sides of the gate structure of the first region is provided with a lightly doped drain region, and the lower surface of the gate structure above one boss structure completely covers the upper surface of the boss structure.

18. The semiconductor device of claim 17, wherein the gate structure comprises a gate and an offset spacer formed on a sidewall of the gate.

19. The semiconductor device according to claim 18, wherein the offset interval includes a first offset interval and a second offset interval formed sequentially from inside to outside at a sidewall of the gate.

20. The semiconductor device of claim 19, wherein the material of the first offset spacers comprises an oxide and the second offset spacers comprise a nitride.

21. The semiconductor device of claim 18, wherein the material of the gate comprises polysilicon.

22. The semiconductor device of claim 17, wherein an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.

23. The semiconductor device of claim 17, wherein a thickness of the first gate insulating layer at the mesa structure is greater than a thickness of the second gate insulating layer.

24. The semiconductor device according to claim 17, wherein the first region is a high voltage region and the second region is a low voltage region.

25. The method of manufacturing a semiconductor device according to claim 17, wherein a material of the first gate insulating layer comprises an oxide and a material of the second gate insulating layer comprises an oxide.

26. The semiconductor device of any of claims 17-25, further comprising spacer sidewalls formed on a common sidewall of the gate structure and the mesa structure on the first region and a sidewall of the gate structure on the second region, respectively.

27. The semiconductor device of claim 26, wherein the spacer sidewalls are formed sequentially from inside to outside on a common sidewall of the gate structure and the mesa structure in the first region and on first and second spacer sidewalls of the sidewall of the gate structure in the second region, respectively.

28. The semiconductor device of claim 27, wherein a bottom surface of the second spacer sidewall is lower than an upper surface of the mesa structure.

29. The semiconductor device of claim 27, wherein a material of the first spacer sidewall comprises an oxide and a material of the second spacer sidewall comprises a nitride.

30. A three-dimensional memory device fabricated using the semiconductor structure of any one of claims 17-29.

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