CN111061336A

CN111061336A - A multi-channel output clock generator with adjustable delay

Info

Publication number: CN111061336A
Application number: CN201911278677.0A
Authority: CN
Inventors: 王飞; 程知群; 尉倞浩; 田刚
Original assignee: Hangzhou Dianzi University
Current assignee: Hangzhou Dianzi University
Priority date: 2019-12-13
Filing date: 2019-12-13
Publication date: 2020-04-24

Abstract

The invention discloses a multichannel output time-delay-adjustable clock generator which comprises a clock part and an upper computer part, wherein the clock part and the upper computer part are communicated through a USB interface, the clock part comprises a USB interface, a USB controller, an MCU, a clock controller, a balun component, an interface group, a crystal oscillator and an LED group, and the clock controller is respectively connected with the MCU, the crystal oscillator and the balun component; the MCU is also connected with the USB controller and the LED group; the USB controller is connected with the USB interface; the balun component is connected with the interface group. Under the condition that at least 4 channels synchronously output signals with the same frequency, one channel can be used as a reference system, and other channels delay time at different time, so that the clock generator with 4 channels outputting with the same frequency and different phases is realized.

Description

Multichannel output time-delay-adjustable clock generator

Technical Field

The invention belongs to the field of signal processing, and relates to a multi-channel output delay-adjustable clock generator.

Background

Although the conventional multi-channel clock generator can generate multi-channel signals, each channel signal is relatively independent, and independent appointed phase delay can not be performed on a single channel under the condition that multi-channel simultaneous-frequency output is realized, so that clock signals with the same frequency and a certain phase difference of more than 2 channels are realized. That is, when multi-channel output is performed, the first channel cannot be used as a reference clock, and the second or other channels cannot perform time-adjustable delay on the basis of the first channel to output signals, so as to implement accurate phase delay.

At present, application scenes needing high-speed high-precision sampling are gradually increased, for example, high-speed sampling is needed in the fields of image acquisition of a high-speed camera, sampling of high-frequency analog signals, signal jitter, delay measurement and the like, but the conversion rate of the conventional AD device cannot meet the requirement of realizing high-speed high-precision sampling by a single chip. At this time, a clock signal with accurate delay needs to be provided to the multiple pieces of AD for fixed-delay sampling.

Therefore, it is necessary to provide a technical solution to solve the technical problems of the prior art in view of the drawbacks and the application requirements of the prior art.

Disclosure of Invention

In order to solve the above problems, the present invention provides a clock generator capable of performing different time delays on other channels with one of the channels as a reference system under the condition that at least 4 channels synchronously output signals with the same frequency, so as to realize 4 channels of outputs with the same frequency and different phases,

comprises a clock part and an upper computer part which are communicated through a USB interface, wherein,

the clock part comprises a USB interface, a USB controller, an MCU, a clock controller, a balun component, an interface group, a crystal oscillator and an LED group, wherein the clock controller is respectively connected with the MCU, the crystal oscillator and the balun component; the MCU is also connected with the USB controller and the LED group; the USB controller is connected with the USB interface; the balun component is connected with the interface group.

Preferably, the upper computer part comprises a system configuration module, a fault diagnosis module, a communication framing module and an interface display module.

Preferably, the clock controller comprises an AD9516 chip.

Preferably, the MCU includes a 430G2553 chip.

Preferably, the USB controller includes a CH340T chip.

Preferably, the frequency of the crystal oscillator is 20M.

Preferably, the interface set comprises 6 SMA interfaces.

Preferably, the LED group includes 4 LED lamps.

Compared with the prior art, the invention has the following beneficial effects:

1. the upper computer part carries out parameter configuration to form a signal frame of USB communication, transmits information to the clock part through a USB cable and an interface, carries out command analysis according to the received information frame, and then configures hardware to work, thereby realizing multi-path clock signal output with same frequency and different phases (different time delays) or same frequency and same phase or different frequencies, and also constructing more multi-path synchronous or asynchronous clock signals through a plurality of systems;

2. the output multi-path clock signals can realize various combinations: (1) the frequency is the same, the phases are different, wherein the configurable interval of the frequency parameter is 1Hz-1.2GHz, the precision is MHz, and the phase is set in a mode of a certain reference percentage; (2) the frequency and the phase are the same, namely 4 paths of full synchronous output are realized; (3) the frequencies are different, namely 4 paths of clock signals with the frequency range of 1Hz-1.2GHz and the precision of MHz are configured for output;

3. the signal frame of communication is formed by the configuration of the function and the acquisition of the state of the upper part, the upper computer part has 4 modules of system configuration, fault diagnosis, communication framing and interface display, the interface display module has a selection module for inputting low-frequency clock, a frequency division and delay setting module for low-frequency clock, an automatic calculation low-frequency clock information and display module, a frequency multiplication clock parameter display and frequency division delay setting module, an external input high-frequency clock selection module, a frequency multiplication and frequency division setting module, an output channel primary frequency division and secondary frequency division configuration module, an output channel delay setting module, an output selection confirmation parameter and channel module, a fault display suggestion window, a write-in command fault acquisition command button and the like.

Drawings

FIG. 1 is a block diagram of a multi-channel output delay-adjustable clock generator according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a multi-channel output delay-adjustable clock generator according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a USB message exchange of a multi-channel output delay-adjustable clock generator according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a clock portion of a multi-channel output adjustable delay clock generator according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.

Referring to fig. 1-4, a clock portion and a host portion 20 are included, which communicate via a USB interface 15, wherein,

the clock part comprises a USB interface 15, a USB controller 13, an MCU12, a clock controller 11, a balun component 14, an interface group 17, a crystal oscillator 18 and an LED group 16, wherein the clock controller 11 is respectively connected with the MCU12, the crystal oscillator 18 and the balun component 14; the MCU12 is also connected with the USB controller 13 and the LED group 16; the USB controller 13 is connected with a USB interface 15; the balun component 14 is connected to an interface group 17.

After the power supply of the clock part is switched on, the upper computer part 20 is switched on, the USB cable is connected with the USB interface 15, and the cable connection appears on the interface of the upper computer part 20, which indicates that the communication is successful; and operating the upper computer part 20, setting basic parameters such as frequency, time delay and the like, and clicking a WRITE key to WRITE in, thereby realizing the configuration of the upper computer data to the clock part. Referring to the normal case, it is already possible to output a 4-channel waveform at this time. If an abnormality occurs, the LED group 16 of the clock section can be checked to see if there is a fault or not (the fault indication of the LED group 16 needs to be set in the upper computer section 20). If the simple fault can be directly processed, if the fault is complex and cannot be displayed through the LED group 16, the fault problem can be obtained through the upper computer part 20UPDATE key, and the clock part can automatically check the position of the fault problem and feed back the position to the upper computer part 20.

The upper computer portion 20 mainly realizes four types of functions: system configuration, fault diagnosis, communication framing and interface display. The system configuration has three functions of channel selection, frequency setting and time delay setting. And the fault diagnosis realizes the functions of sending codes, implementing hardware diagnosis commands, acquiring fault codes and displaying inspection suggestions through an interface. The basic language format of the communication between the upper computer part 20 and the clock part is completed by communication framing, the configuration parameters are filled with a frame structure and sent to the clock part, and meanwhile, information such as fault feedback sent by the clock part is identified, and effective data is extracted. A whole set of human-computer interface is designed for interface display, and the operation is simple and convenient and the process is clear through graphical display.

The upper left BOARD REF and EXT REF IN parts of the interface of the upper computer part 20 are selected for inputting a low-frequency clock, and the clock part is loaded with a 20MHz crystal oscillator 18, so that the clock frequency cannot be freely input when the BOARD REF function is selected and used, and only the points IN front of the main points are needed. If the EXT REF IN function is selected to indicate that the external low-frequency clock input is selected, a signal of 10M-50M is required to be accessed from the outside, and the actual frequency of the input is filled IN a lower frame. The R DIVIDER function is an input low-frequency clock frequency division function, and the frequency division function can be selected to be 1-5 times. The R DELAY function is an input low-frequency clock DELAY function and can only set the DELAY within 100 ps. The PFD module calculates the actual frequency calculation result entering the PLL frequency multiplication input for the low-frequency input clock finally, the function sets active calculation, and if the calculation result is found to be wrong, recalculation can be carried out according to the PFD. The N DIVIDER and N DELAY functions are similar to the R end function, and the main difference is that the N end is set as PLL frequency multiplication, the frequency division can be set to be 300 times at most, and the time DELAY is 100 ps. The AUTO VCO part calculates a clock value for the final VCO after PLL frequency multiplication, and actively calculates after setting a frequency division coefficient, and can also manually calculate when errors are found. The final calculated VCO frequency is divided to meet the range of 2300-2650 MHz. The EXT CLK is selected by an external input high-frequency clock, if the function is selected to be used, the function configured by the AUTO VCO fails completely, a high-frequency clock source is required to be accessed externally, the range is 2650MHz at 100 ℃, and the actual input value is required to be filled in a lower frame. VCODVIDER is a high frequency division module and can set 1-6 times of frequency division. OUT divide 1/2 is the output first/second divide, which can set up a divide by a factor of up to 32. And the delta T OUT is set for each output delay and is configured in a percentage mode. And OUT is a channel output selection and frequency display function, wherein the frequency display is active calculation, and the OUT key can be pressed to recalculate if an error exists. If which channel output is to be selected, the point in front of the frequency value is good. And a display frame behind the lowest Status is a state display frame, and the inspection suggestion information is displayed when the fault occurs. The LED in the middle of the interface is a clock part onboard LED lamp display state configuration part, 4 LED lamps are used in total, and different states including an error state or a normal operation state can be displayed in a selectable configuration mode. And the upper right corner of the interface, namely the WRITE and the UPDATE, is configured to complete the information writing into the clock part and the fault, and the function of sending a fault information acquisition command is realized.

Table one is a schematic diagram of the structure of a USB information exchange frame,

data transmission from upper computer to clock

Clock part data is transmitted to upper computer part

table-USB information exchange frame structure diagram

There are two types of USB information exchange: 1. the upper computer information is sent to a clock part; 2. the clock section information is sent to the upper computer section 20. The frame structure is a special identification frame structure reorganized on the basis of meeting the serial port UART protocol, belongs to an application layer structure, and is provided with an identification frame head, data and a fixed frame tail. The upper computer information sends a register writing command, a register reading command, a state acquiring command and an information receiving confirmation reply command. The upper computer portion 20 receives information such as write success and failure commands, register value acquisition reply commands, and status acquisition reply commands.

Fig. 3 is a schematic diagram of USB information exchange. The USB information exchange process mainly has three types: 1. a communication docking process after starting up; 2. the upper computer portion 20 writes a command process; 3. the upper computer portion 20 reads the command process. Fig. 3 shows a communication docking process, a process of successful write command of the upper computer portion 20, and a process of failed read command of the upper computer portion 20, and other processes, such as a process of failed write command, and a process of successful read status, successful read command, etc., are similar to the shown processes.

Fig. 4 is a schematic circuit diagram of the clock section. The clock part mainly comprises a USB controller 13CH340T chip, an MCU12430G2553 chip, a clock controller 11AD9516 chip, 4 paths of LED lamps of the LED group 16, 5 paths of balun conversion chips of the balun component 14, a crystal oscillator 18 of 20M, 6 SMA interfaces of the interface group 17 and a miniUSB interface 15. The actual clock part also includes a resistor, capacitor, inductor and power module, which are not shown in detail but are part of the complete function of the hardware.

The USB interface 15MiniUSB port is connected to the D + and D-interfaces of the USB controller 13CH340T through data interfaces D + and D-; the RXD interface of the CH340T is connected to the TXD of the MCU12430G2553, and the TXD of the USB controller 13CH340T is connected to the RXD interface of the MCU12430G2553, so that a UART transmission hardware structure is realized. The 4 paths of LED lamps of the LED group 16 are respectively connected to pins P2.0-P2.3 of the MCU12430G 2553; the MCU12430G2553 has 10 interfaces connected to the clock controller 11AD9516, and can be classified into three categories according to signal types: 1. SPI interface type 3 lines (CS-CS, SCK-SCK, SDIO-SDIO); 2. STATUS signal class 3 lines (P1.0-P1.2 of MCU12430G2553 are connected to REFMIN, LD and STATUS pins of clock controller 11AD9516, respectively); 3. control signal class 4 lines (P1.4-P1.7 of MCU12430G2553 connect REFSEL, SYNC, RESET, PD pins of clock controller 11AD9516, respectively); the clock controller 11AD9516 also has 4 clock input signals which are respectively a REF low-frequency input clock, the REF + is connected with the 20M crystal oscillator 18, and the REF-is connected with one SMA interface; the other 2 paths are differential high-frequency clock inputs and are indirectly connected with an SMA interface through a differential interface connected with the balun component 14, and the SMA interface is connected with a single-end interface of the balun conversion chip; the 8 paths of output signals of the clock controller 11AD9516 are respectively connected with 4 balun conversion chips and are connected in a differential mode, namely, a + end is connected with a P end of the balun conversion chips, a-end is connected with an N end of the balun conversion chips, and single ends of the 4 paths of balun conversion chips are respectively connected with 4 SMA interfaces.

The upper computer part 20 performs parameter configuration to realize at least 4 paths of clock signals with the same frequency but different phases (i.e. different time delays). If a plurality of systems are adopted, a plurality of paths of clock signals with the same frequency and different phases can be realized, taking the realization of at least 16 paths of clocks with the same frequency and different phases as an example, the specific method is as follows: firstly, a set of system is named as A, 4 paths of clock signals A0-A4 with same frequency and phase are realized, then 4 sets of systems are selected for naming B, C, D, E respectively, the previously configured A0-A4 clock signals are connected to the EXT CLK end of BCDE respectively, then delta T OUT delay proportion of four sets of systems of BCDE is configured, and if 16 paths of signals are output equally, the delay is adjusted to 1/16, 2/16 and 3/16 …. According to the method, at least 16 clock signals with the same frequency and different phases can be configured. According to the method, if more sets of systems are selected, more paths of clock signals with the same frequency and different phases can be realized.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. a clock generator of a multi-channel output adjustable delay, is characterized in that, comprises clock part and host computer part, the two communicate by USB interface, wherein,

The clock part includes a USB interface, a USB controller, an MCU, a clock controller, a balun assembly, an interface group, a crystal oscillator and an LED group, and the clock controller is respectively connected with the MCU, the crystal oscillator and the balun assembly; the MCU is also It is connected with the USB controller and the LED group; the USB controller is connected with the USB interface; the balun assembly is connected with the interface group.

2 . The system according to claim 1 , wherein the host computer part comprises a system configuration module, a fault diagnosis module, a communication framing module and an interface display module. 3 .

3. The system of claim 1, wherein the clock controller comprises an AD9516 chip.

4. The system according to claim 1, wherein the MCU comprises a 430G2553 chip.

5. The system of claim 1, wherein the USB controller comprises a CH340T chip.

6. The system according to claim 1, wherein the frequency of the crystal oscillator is 20M.

7. The system of claim 1, wherein the interface group comprises 6 SMA interfaces.

8. The system of claim 1, wherein the LED group comprises 4 LED lights.