CN110873814A - Link integration module, system and method for realizing boundary scan chain integration test - Google Patents
Link integration module, system and method for realizing boundary scan chain integration test Download PDFInfo
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- CN110873814A CN110873814A CN201811004245.6A CN201811004245A CN110873814A CN 110873814 A CN110873814 A CN 110873814A CN 201811004245 A CN201811004245 A CN 201811004245A CN 110873814 A CN110873814 A CN 110873814A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
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Abstract
The invention relates to a technology for testing a board card of communication equipment. The invention solves the problem that the ICT tester can not carry out the boundary scan link integration test at present, and provides a link integration module, a system and a method for realizing the boundary scan chain integration test, and the technical scheme can be summarized as follows: the link integration module comprises a group of input ends and at least two groups of output ends which are respectively connected with the drive isolation circuit, and one group of output ends are used for corresponding to a boundary scanning link on the tested board card one by one; the drive isolation circuit is used for isolating the TCK signal output interface, the TMS signal output interface and the TRST signal output interface of each group of output ends and then connecting the TCK signal output interface, the TMS signal input interface and the TRST signal input interface in the input ends, and keeping the corresponding pull-up and pull-down equivalent resistance unchanged. The invention has the beneficial effects that: the test coverage rate of the interconnected network among different boundary scanning links is improved, and the method is suitable for testing the board card of the communication equipment.
Description
Technical Field
The invention relates to a board test technology of communication equipment, in particular to a technology for integrated test of a plurality of boundary scan chains on a board.
Background
Due to the practical design and production condition limitation of the board card, a plurality of independent boundary scan chains are often designed on the board card, and if the link integration is directly carried out on the board card, the programmable device cannot be burnt on line, the cost of the integrated device is increased and the like; a network of chip interconnects between different boundary scan chains can only be covered by an In Circuit Test (ICT) Test station by integrating tests through the boundary scan chains.
The existing ICT tester, such as TR8100LV, has only 3 independent boundary scan chain test channels, can only test 3 or less boundary scan chains individually, can not test different boundary scan chains integrally, the network of chip interconnection among different boundary scan chains becomes a test blind spot, the ICT test coverage rate is reduced, this is because the implementation of the boundary scan chain integration Test on the ICT tester (TR8100LV) requires connecting the TCK (Test clock input), TMS (Test Mode select) and TRST (Test Reset input) signals of each link of the board card under Test in parallel to the corresponding channels of the boundary scan tester of the device, however, after the TCK signal and the TRST signal are connected in parallel, the pull-down equivalent resistance is reduced, the driving capability of the ICT tester is weakened, and the ICT tester (TR8100LV) cannot perform boundary scan link integration test.
The method realizes the integration test of a plurality of (more than 3) boundary scan chains on the ICT tester under the condition of keeping the existing design of the product unchanged, breaks through the test limitation of the ICT tester, and has great significance for improving the ICT test coverage.
Disclosure of Invention
The invention aims to solve the problem that the conventional ICT tester cannot perform boundary scan link integration test, and provides a link integration module, a system and a method for realizing boundary scan chain integration test.
The technical scheme includes that the link integration module comprises a drive isolation circuit, a group of input ends and at least two groups of output ends, wherein the group of input ends and the at least two groups of output ends are respectively connected with the drive isolation circuit;
each group of output ends comprises a TCK signal output interface, a TMS signal output interface and a TRST signal output interface, and is used for corresponding to a boundary scan link on the tested board card one by one, and the TCK signal output interface, the TMS signal output interface and the TRST signal output interface in each group of output ends are respectively used for corresponding connection with a TCK input end, a TMS input end and a TRST input end of the corresponding boundary scan link;
the input end comprises a TCK signal input interface, a TMS signal input interface and a TRST signal input interface, and the TCK signal input interface, the TMS signal input interface and the TRST signal input interface are respectively used for being connected with a TCK output end, a TMS output end and a TRST output end of the ICT jig;
the drive isolation circuit is used for isolating the TCK signal output interface, the TMS signal output interface and the TRST signal output interface of each group of output ends and then connecting the TCK signal output interface, the TMS signal output interface and the TRST signal output interface to the TCK signal input interface, the TMS signal input interface and the TRST signal input interface in the input end, and keeping the corresponding pull-up and pull-down equivalent resistance unchanged.
Specifically, the driving isolation circuit adopts a 74LV245B chip design, the development cost can be reduced by utilizing the existing chip design, the 74LVT245B is used for asynchronous communication between data buses, and the delay time of transmission is within the acceptable range of an ICT tester.
Another object of the present invention is to provide a system for implementing boundary scan chain integration test, including an ICT testing machine, an ICT fixture, and the above link integration module, wherein the TCK signal input interface, the TMS signal input interface, and the TRST signal input interface of the link integration module are respectively used for connecting to the TCK output terminal, the TMS output terminal, and the TRST output terminal of the ICT fixture, the ICT fixture is installed on the ICT testing machine,
connecting the TCK input end, the TMS input end and the TRST input end of each boundary scanning link of the tested board card with the TCK signal output interface, the TMS signal output interface and the TRST signal output interface in each group of output ends of the link integration module in a one-to-one correspondence manner; connecting the TDI (Test Data input) input end and the TDO (Test Data Output) Output end of each boundary scanning link of the tested board card in series according to a preset link integration sequence, wherein the integrated TDI input end and the integrated TDO Output end after the connection in series are respectively and correspondingly connected with the TDI Output end and the TDO input end of the ICT jig;
and setting a boundary scan chain test program on the ICT tester according to a preset link integration sequence, executing the test program, and providing test signals to the tested board card through probes of the ICT jig to complete related tests.
Specifically, the ICT testing machine is an ICT testing machine of a TR8100LV model, and the ICT testing machine is a conventional ICT testing machine, is mature in technology and does not need to be developed additionally.
Further, the setting of the boundary scan chain test program according to the preset link integration sequence means: modifying the files of the star, bbc in the original program of the ICT tester according to a preset link integration sequence; and the whole program does not need to be changed in a more complex way.
Specifically, the modifying the x. bbc file in the original program of the ICT tester according to the preset link integration sequence means: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence.
Another object of the present invention is to provide a method for implementing a boundary scan chain integration test, comprising the steps of:
step 1, connecting TDI input ends and TDO output ends of boundary scanning links of a tested board card in series according to a preset link integration sequence, wherein the integrated TDI input ends and the integrated TDO output ends after the connection in series are respectively and correspondingly connected with the TDI output ends and the TDO input ends of an ICT jig;
step 2, connecting the TCK input end, TMS input end and TRST input end of each boundary scanning link of the tested board card with the TCK signal output interface, TMS signal output interface and TRST signal output interface in each group of output ends of the link integration module in a one-to-one correspondence manner;
step 3, respectively connecting a TCK signal input interface, a TMS signal input interface and a TRST signal input interface of the link integration module with a TCK output end, a TMS output end and a TRST output end of the ICT jig;
step 4, installing an ICT jig on an ICT testing machine;
and 5, setting a boundary scan chain test program on the ICT test machine according to a preset link integration sequence, executing the test, and providing the test signal to the tested board card through a probe of the ICT jig to complete the related test.
Specifically, in step 4, the ICT testing machine is an ICT testing machine of TR8100LV model, and the ICT testing machine is a conventional ICT testing machine, and has mature technology and no need of additional development.
Further, in step 5, the setting of the boundary scan chain test program according to the preset link integration sequence means: and modifying the files of the star bbc in the original program of the ICT tester according to a preset link integration sequence.
Specifically, the modifying the x. bbc file in the original program of the ICT tester according to the preset link integration sequence means: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence.
The system and the method for realizing the boundary scan chain integration test have the advantages that the existing ICT test machine can be used for different boundary scan link integration tests, the test coverage rate of the interconnected network among different boundary scan links is improved, and the link integration module is only required to be added, so that the material cost of the board card design is not required to be additionally added.
Drawings
Fig. 1 is a schematic structural diagram of a link integration module according to the present invention.
FIG. 2 is a schematic structural diagram of a system for implementing boundary scan chain integration test according to an embodiment of the present invention.
The chip comprises a first U1, a second U2, a third U3, a fourth U4, a fifth U5, a sixth U6, a seventh U7, an eighth U8, a ninth U9, a first TDI1, a second TDI2, a third TDI3, a first TDO1, a second TDO2, a third TDO3, a third TDI signal, a TDO signal, a TCK signal, a TMS signal, a TRST signal, a first TCK signal, a first TMS signal, a first TRST1, a second TCK2, a second TCK signal, a second TMS signal 2, a second TRST2, a second TCK signal, a third TCK3, a third TMS signal, a TRST3, and a third TRST 3.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the embodiments and the accompanying drawings. Before explaining the embodiments of the present invention in detail, technical terms used in the description of the technical solutions of the present application are explained as follows:
test Clock Input, Test Clock Input.
TMS, Test Mode Selector and Test Mode selection.
TDI, Test Data Input.
TDO Test Data Output.
Test Reset, # TRST, Test Reset input.
The link integration module disclosed by the invention is shown in fig. 1 and comprises a drive isolation circuit, a group of input ends and at least two groups of output ends, wherein the group of input ends and the at least two groups of output ends are respectively connected with the drive isolation circuit, each group of output ends comprises a TCK signal output interface, a TMS signal output interface and a TRST signal output interface, and the group of input ends comprises a TCK signal input interface, a TMS signal input interface and a TRST signal input interface, wherein the TCK signal input interface, the TMS signal input interface and the TRST signal input interface are respectively used for being connected with a TCK output end, a TMS output end and a TRST output end of an ICT fixture; the TCK signal output interface, the TMS signal output interface and the TRST signal output interface in each group of output ends are respectively used for being correspondingly connected with the TCK input end, the TMS input end and the TRST input end of the corresponding boundary scanning link one by one; the drive isolation circuit is used for isolating the TCK signal output interface, the TMS signal output interface and the TRST signal output interface of each group of output ends and then connecting the TCK signal output interface, the TMS signal input interface and the TRST signal input interface in the input ends, and keeping the corresponding pull-up and pull-down equivalent resistance unchanged. Therefore, the signal driving capability of the ICT tester can be improved, and the ICT tester can finish different boundary scan link integration tests.
The drive isolation circuit can adopt a 74LV245B chip design, the development cost can be reduced by utilizing the existing chip design, the 74LVT245B chip is used for asynchronous communication among data buses, the delay time of transmission is within the range acceptable by an ICT tester, and data is transmitted from A bus to B bus or B bus to A bus depending on the input logic level of a directional control (DIR) Pin.
The invention discloses a system for realizing boundary scan chain integration test, which comprises an ICT test machine, an ICT fixture and a link integration module, wherein a TCK signal input interface, a TMS signal input interface and a TRST signal input interface of the link integration module are respectively used for being connected with a TCK output end, a TMS output end and a TRST output end of the ICT fixture; connecting the TDI input end and the TDO output end of each boundary scanning link of the tested board card in series according to a preset link integration sequence, wherein the integrated TDI input end and the integrated TDO output end after the connection in series are respectively and correspondingly connected with the TDI output end and the TDO input end of the ICT jig; and setting a boundary scan chain test program on the ICT tester according to a preset link integration sequence, executing the test, and providing a test signal to the tested board card through a probe of the ICT jig to complete the related test. Therefore, only one boundary scan link integration module is added in the system and matched with an ICT test machine and an ICT jig to realize ICT boundary scan link integration test, so that the problem of adding devices to integrate each group of boundary scan links during product design is solved, the material cost is reduced, the independent boundary scan chains are kept for facilitating the burning of programmable devices, and the design difficulty is reduced; the limitation that an ICT tester cannot perform integration test on a plurality of (more than three) boundary scan chains is solved, and the test coverage rate of the interconnection network among the chips of each boundary scan chain is improved. The ICT testing machine can be preferably an ICT testing machine of a TR8100LV model, is a conventional ICT testing machine, is mature in technology and does not need to be developed additionally.
Here, the setting of the boundary scan chain test program according to the preset link integration order may be: modifying an x. bbc file in an original program of the ICT tester according to a preset link integration sequence, specifically: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence. This approach does not require more complex changes to the entire procedure.
The method for realizing the boundary scan chain integration test firstly realizes hardware connection: connecting TDI input ends and TDO output ends of boundary scanning links of a tested board card in series according to a preset link integration sequence, connecting the integrated TDI input ends and the integrated TDO output ends after the connection in series correspondingly with TDI output ends and TDO input ends of an ICT jig respectively, connecting TCK input ends, TMS input ends and TRST input ends of the boundary scanning links of the tested board card correspondingly with TCK signal output interfaces, TMS signal output interfaces and TRST signal output interfaces in output ends of a link integration module respectively one by one, connecting TCK signal input interfaces, TMS signal input interfaces and TRST signal input interfaces of the link integration module with TCK output ends, TMS output ends and TRST output ends of the ICT jig respectively, and installing the ICT jig on an ICT testing machine; the program is then modified: and setting a boundary scan chain test program on an ICT tester according to a preset link integration sequence, executing the test, and providing a test signal to the tested board card through a probe of the ICT jig to complete the related test. Therefore, only one boundary scan link integration module is needed to be added in the method and an ICT test machine and an ICT jig are matched to realize ICT boundary scan link integration test, so that the problem that devices are added to integrate each group of boundary scan links during product design is solved, the material cost is reduced, meanwhile, the independent boundary scan chains are kept to facilitate the burning of programmable devices, and the design difficulty is reduced; the limitation that an ICT tester cannot perform integration test on a plurality of (more than three) boundary scan chains is solved, and the test coverage rate of the interconnection network among the chips of each boundary scan chain is improved. The ICT testing machine can be preferably an ICT testing machine of a TR8100LV model, is a conventional ICT testing machine, is mature in technology and does not need to be developed additionally.
Here, the setting of the boundary scan chain test program according to the preset link integration order may be: modifying an x. bbc file in an original program of the ICT tester according to a preset link integration sequence, specifically: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence. This approach does not require more complex changes to the entire procedure.
Examples
In the embodiment of the present invention, taking three boundary scan links in a board to be tested as an example, and referring to fig. 2, a structural diagram of the board to be tested during testing is shown, where the three boundary scan links are a first boundary scan link, a second boundary scan link, and a third boundary scan link, respectively, the first boundary scan link includes a TDI input terminal TDI1, a chip first U1, a chip second U2, a chip third U3, and a TDO output terminal TDO1, the second boundary scan link includes a TDI input terminal di TDI2, a chip fourth U4, a chip fifth U5, a chip sixth U6, and a TDO output terminal di TDO2, and the third boundary scan link includes a TDI input terminal tri TDI3, a chip seventh U7, a chip eighth U8, a chip ninth U9, and a TDO output terminal tri TDO 3.
According to the connection relationship in the system for realizing the boundary scan chain integration test or the hardware connection in the method for realizing the boundary scan chain integration test, the first TDO output end 1 is connected with the second TDI2 of the TDI input end, and the second TDO output end 2 is connected with the third TDI3 of the TDI input end, so that the TDI input end and the TDO output end of each boundary scan link of the board card to be tested are connected in series according to a preset link integration sequence, the first TDI1 of the TDI input end is the integration TDI input end, the third TDO output end 3 is the integration TDO output end, which is correspondingly connected with the TDI output end and the TDO input end of the ICT jig respectively, and the TDI signal sent by the ICT jig is received by the tester and the TDO signal TDO is output to the ICT tester through the ICT jig.
In the embodiment of the present invention, the input end of the link integration module receives the TCK signal TCK, the TMS signal TMS, and the TRST signal TRST sent by the ICT tester through the ICT fixture, and the input end of the link integration module correspondingly has three sets of output ends, where the first set of output ends is used to send out a TCK signal TCK1, a TMS signal TMS1, and a TRST signal TRST1 to the first boundary scan link, the second set of output ends is used to send out a TCK signal two TCK2, a TMS signal two TMS2, and a TRST signal two TRST2 to the second boundary scan link, and the third set of output ends is used to send out a TCK signal three TCK3, a TMS signal three TMS3, and a TRST signal three TRST3 to the third boundary scan link.
As can be seen from fig. 2, the number of the links in the embodiment of the present invention is three, and the connection order of the chips in the links is chip one U1, chip two U2, chip three U3, chip four U4, chip five U5, chip six U6, chip seven U7, chip eight U8, and chip nine U9.
Claims (10)
1. The link integration module is characterized by comprising a driving isolation circuit, a group of input ends and at least two groups of output ends, wherein the group of input ends and the at least two groups of output ends are respectively connected with the driving isolation circuit;
each group of output ends comprises a TCK signal output interface, a TMS signal output interface and a TRST signal output interface, and is used for corresponding to a boundary scan link on the tested board card one by one, and the TCK signal output interface, the TMS signal output interface and the TRST signal output interface in each group of output ends are respectively used for corresponding connection with a TCK input end, a TMS input end and a TRST input end of the corresponding boundary scan link;
the input end comprises a TCK signal input interface, a TMS signal input interface and a TRST signal input interface, and the TCK signal input interface, the TMS signal input interface and the TRST signal input interface are respectively used for being connected with a TCK output end, a TMS output end and a TRST output end of the ICT jig;
the drive isolation circuit is used for isolating the TCK signal output interface, the TMS signal output interface and the TRST signal output interface of each group of output ends and then connecting the TCK signal output interface, the TMS signal output interface and the TRST signal output interface to the TCK signal input interface, the TMS signal input interface and the TRST signal input interface in the input end, and keeping the corresponding pull-up and pull-down equivalent resistance unchanged.
2. The link integration module of claim 1, wherein the drive isolation circuit is designed using a 74LV245B chip.
3. The system for realizing the boundary scan chain integration test comprises an ICT tester and an ICT jig, and is characterized by further comprising the link integration module set according to claim 1 or 2, wherein the TCK signal input interface, the TMS signal input interface and the TRST signal input interface of the link integration module set are respectively used for being connected with the TCK output end, the TMS output end and the TRST output end of the ICT jig, the ICT jig is installed on the ICT tester,
connecting the TCK input end, the TMS input end and the TRST input end of each boundary scanning link of the tested board card with the TCK signal output interface, the TMS signal output interface and the TRST signal output interface in each group of output ends of the link integration module in a one-to-one correspondence manner; connecting the TDI input end and the TDO output end of each boundary scanning link of the tested board card in series according to a preset link integration sequence, wherein the integrated TDI input end and the integrated TDO output end after the connection in series are respectively and correspondingly connected with the TDI output end and the TDO input end of the ICT jig;
and setting a boundary scan chain test program on the ICT tester according to a preset link integration sequence, executing the test program, and providing test signals to the tested board card through probes of the ICT jig to complete related tests.
4. The system for implementing boundary scan chain integration testing as recited in claim 3, wherein the ICT tester is a TR8100LV model ICT tester.
5. The system for implementing boundary scan chain integration test as claimed in claim 4, wherein the setting of the boundary scan chain test program according to the predetermined link integration sequence is: and modifying the files of the star bbc in the original program of the ICT tester according to a preset link integration sequence.
6. The system for implementing boundary scan chain integration test as claimed in claim 5, wherein the modification of the file bbc in the original program of the ICT tester according to the predetermined link integration sequence is: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence.
7. The method for realizing the boundary scan chain integration test is characterized by comprising the following steps of:
step 1, connecting TDI input ends and TDO output ends of boundary scanning links of a tested board card in series according to a preset link integration sequence, wherein the integrated TDI input ends and the integrated TDO output ends after the connection in series are respectively and correspondingly connected with the TDI output ends and the TDO input ends of an ICT jig;
step 2, connecting the TCK input end, TMS input end and TRST input end of each boundary scanning link of the tested board card with the TCK signal output interface, TMS signal output interface and TRST signal output interface in each group of output ends of the link integration module in a one-to-one correspondence manner;
step 3, respectively connecting a TCK signal input interface, a TMS signal input interface and a TRST signal input interface of the link integration module with a TCK output end, a TMS output end and a TRST output end of the ICT jig;
step 4, installing an ICT jig on an ICT testing machine;
and 5, setting a boundary scan chain test program on the ICT test machine according to a preset link integration sequence, executing the test, and providing the test signal to the tested board card through a probe of the ICT jig to complete the related test.
8. The method for implementing boundary scan chain integration test as claimed in claim 7, wherein in step 4, the ICT tester is a TR8100LV model ICT tester.
9. The method as claimed in claim 8, wherein in step 5, the setting of the boundary scan chain test program according to the predetermined link integration sequence is: and modifying the files of the star bbc in the original program of the ICT tester according to a preset link integration sequence.
10. The method for implementing boundary scan chain integration test as claimed in claim 9, wherein the modifying the file of x. bbc in the original program of the ICT tester according to the preset link integration sequence is: redefining the link quantity in the bbc file and the connection sequence of chips in the link according to a preset link integration sequence.
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Application publication date: 20200310 |