CN109995359B - Metastable state observation system and method for edge trigger - Google Patents

Abstract

The invention provides an edge trigger metastable observation system and its observation method, including: an edge trigger metastable observation system, including: a pulse signal source, a delayer A, a delayer B, a trigger, an NRZ /RZ converter, bit error test unit and oscilloscope; delayer A and delayer B are respectively connected to the D terminal and CP terminal of the flip-flop, and the input delay interval τ ₀₁ of delayer A and delayer B is read out with the oscilloscope . The NRZ/RZ converter is arranged between the Q terminal of the flip-flop and the error code testing unit; the pulse rising edge of the Q terminal of the flip-flop and the pulse rising edge of the CP terminal are respectively counted by the code error testing unit. The invention has the advantages that the observation system is simple and easy to implement, has high reliability, and has important reference value for engineering technicians and teaching personnel engaged in the research on the metastable characteristics of the edge trigger.

Description

Edge Trigger Metastable State Observation System and Its Observation Method

technical field

The invention relates to the technical field of metastable state observation, in particular to an edge trigger metastable state observation system.

Background technique

As a high-speed storage memory element, flip-flop is widely used in contemporary IT hardware circuits and systems. In order to realize the reliable storage of the input data, it is required that the setup time and hold time area of the input data before and after the rising edge of the clock remain constant, otherwise a metastable state will occur, resulting in bit errors of the data stored in the flip-flop. In the study of the internal circuit of flip-flops and the application of flip-flops across clock domains, people often need to observe the occurrence of metastable states. However, because the metastable process is a random process, it is difficult to observe it in actual work.

Contents of the invention

Aiming at the defects of the prior art, the present invention provides an edge trigger metastable observation system, which can effectively solve the above-mentioned problems in the prior art.

In order to realize above object of the invention, the technical scheme that the present invention takes is as follows:

An edge trigger metastability observation system, comprising: a pulse signal source, a delayer A, a delayer B, a trigger, an NRZ/RZ converter, a bit error testing unit and an oscilloscope;

The delayer A and the delayer B are respectively connected to the D terminal and the CP terminal of the flip-flop, and the input delay interval τ ₀₁ of the delayer A and the delayer B is read out with an oscilloscope.

The NRZ/RZ converter is set between the trigger Q terminal and the error test unit;

公式得出该输入激励情况下的误码率δ₀₁。Use the bit error test unit to count the rising edge of the trigger Q terminal pulse and the rising edge of the CP terminal pulse respectively, and then press

The formula yields the bit error rate δ ₀₁ for this input excitation.

The bit error test unit is composed of NI acquisition card and Labview software.

When programming in LABVIEW, you only need to judge the rising edge of the data collected by the port of the NI acquisition card, count continuously with the shift register, and program the clear terminal.

In the procedure for judging the rising edge of the data collected by the port of the NI acquisition card, first use the index array VI to distinguish the data of the two ports, and then use the Boolean value conversion (point by point) VI to judge the rising edge. In this VI, the direction selection false-true. The clearing terminal adopts the method of writing data 0 into the shift register when the conditional structure is false, so as to achieve the purpose of data clearing.

Further, the pulse signal source outputs a 0-5V square wave with a duty cycle of 50% and a frequency of 100 Hz. Phase shifter R=100Ω.

An observation method of an edge trigger metastable state observation system, comprising the following steps:

Step 1. Observing with an oscilloscope, make the distance between the rising edge of the D terminal of the flip-flop and the rising edge of the CP terminal of the flip-flop |τ ₀₁ |>|τ _01L |.

Step 2, realizing the decreasing scan of |τ ₀₁ | within the set-up time range.

Step 3, when |τ ₀₁ |<|τ _01L |, the code error waveform can be observed with an oscilloscope at the Q terminal of the trigger. At this time, the value of τ ₀₁ can be read by the oscilloscope, and the value of δ ₀₁ can be read by the code error test unit.

Step 4, with the decrease of |τ ₀₁ |, the value of δ ₀₁ will gradually increase monotonously. When |τ ₀₁ |<|τ _01H |, the value of δ ₀₁ will reach 100%. Continue to reduce |τ ₀₁ | until it is 0, the value of δ ₀₁ will always maintain 100% value.

Compared with the prior art, the invention has the advantages of simple operation and high reliability, and has important reference value for engineering technicians and teaching personnel who are engaged in the research on the metastable characteristics of the edge trigger.

Description of drawings

Fig. 1 is the bit error curve figure in the time of establishment of the present invention;

Fig. 2 is a schematic diagram of jumping in the [τ _01L , τ _01H ] interval of the D terminal of the present invention;

Fig. 3 is the random bit error waveform figure of Q end of the present invention;

Fig. 4 is a block diagram of the metastable observation system of the present invention;

Fig. 5 is the circuit diagram of the metastable observation system of the present invention;

Fig. 6 is a structural diagram of a bit error testing unit of the present invention;

Fig. 7 is the flow chart of the experimental observation of the metastable state of the embodiment of the present invention;

Fig. 8 is the δ～τ bit error curve diagram within the establishment time of the embodiment of the present invention 74HC74

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and examples.

working principle

In the edge D flip-flop setup time T _su area, there is a bit error curve as shown in Fig. 1 .

When the data at the D terminal jumps from "0" at the moment before the jump to "1" at the next moment, the interval between the D jump edge and the CP rising edge is τ ₀₁ , and |τ _01L |>|τ ₀₁ | >|τ _01H |, as shown in Figure 2.

A stable metastable error code waveform can be observed at the Q end of the flip-flop, as shown in Figure 3.

In Figure 3, the random bit error waveform at the Q end is not certain at a certain moment, but it has a statistical law. As τ ₀₁ increases from large to small, the bit error rate will gradually rise monotonously from 0% to 100%.

Counting the rising edges of CP and Q(RZ), there is a mathematical relationship between the count values:

For the convenience of counting, it is necessary to convert the non-return-to-zero waveform Q(NRZ) output by the Q terminal into the return-to-zero waveform Q(RZ).

Composition of Metastable Observation System

The block diagram of the metastable observation system is shown in Figure 4. In order to realize the delay between the D end and the CP end, the delayer 1 and the delayer 2 are respectively connected to the D end and the CP end, and the input delay interval τ ₀₁ is read out with an oscilloscope. Use the bit error test unit to count the rising edges of the pulses at the Q terminal and the rising edges of the CP pulses respectively, and then obtain the bit error rate δ ₀₁ under the input excitation according to formula (3).

If the D terminal and CP terminal use the same pulse signal source, the delayer uses an RC delay circuit, and the NRZ/RZ circuit is obtained by phase-ANDing the Q terminal and the CP terminal, the timing shown in Figure 3 can be realized. The specific circuit of the experiment is shown in Figure 5.

In the circuit in Figure 5, the operating voltage is 5V, the pulse signal source model is RIGOL DS1102E, and the oscilloscope model is TektronixMSO58. The pulse signal source outputs a 0-5V square wave with a duty cycle of 50% and a frequency of 100Hz. Phase shifter R = 100Ω, C ₂ selects 5/20pF fine-tuning capacitor. The AND gate selects and integrates four 2-input AND gate CD4081. In order to shape and isolate, the non-gate selects the integrated six-input non-gate CD4069.

BERT

The bit error test unit is composed of NI acquisition card and Labview software, as shown in Figure 6.

The capture card is model NI USB-6001 with 13 digital ports. This experiment uses two digital I/O ports, Port P0.0, Port P0.1.

When programming in LABVIEW, you only need to judge the rising edge of the data collected by the P0.0 and P0.1 ports, count continuously with the shift register, and program the clear terminal.

In the procedure for judging the rising edge of the data collected by the data port, first use the index array VI to distinguish the data of the two ports, and then use the Boolean value conversion (point by point) VI to judge the rising edge. In this VI, the direction selection is false- true. The clearing terminal adopts the method of writing data 0 into the shift register when the conditional structure is false, so as to achieve the purpose of data clearing.

Example 1

The process of using the metastable observation system to conduct experimental observations on the edge D flip-flop is shown in Figure 7.

An observation method of an edge trigger metastable state observation system, comprising the following steps:

Step 1: Make C ₁ and C ₂ the smallest, increase C ₃ , observe with an oscilloscope, and make the distance between the rising edge of the D terminal of the trigger and the rising edge of the CP terminal of the trigger |τ ₀₁ |>|τ _01L |.

Step 2, fix C ₃ , gradually increase C ₁ , and realize the decreasing scan of |τ ₀₁ | within the set-up time range.

Step 3, when |τ ₀₁ |<|τ _01L |, the code error waveform can be observed with an oscilloscope at the Q terminal of the trigger. At this time, the value of τ ₀₁ can be read by the oscilloscope, and the value of δ ₀₁ can be read by the code error test unit.

Step 4, fix C ₁ and C ₃ and increase the value of fine-tuning capacitor C ₂ . As |τ ₀₁ | decreases, the value of δ ₀₁ will gradually increase monotonously. When |τ ₀₁ |<|τ _01H |, the value of δ ₀₁ will reach 100%. Continue to reduce |τ ₀₁ | until it is 0, the value of δ ₀₁ will always maintain 100% value.

In Fig. 5, the D flip-flop in the figure is replaced by an integrated flip-flop 74HC74 as an example of metastable state observation. The measured data are shown in Table 1.

Table 1 BER Data Record of 74HC74 Integrated Trigger

τ₀₁(ns) δ(%) -20.000 0 -10.00 0 -5.000 0 -3.000 0 -1.300 0 -1.289 3.32 -1.220 13.06 -1.197 32.03 -1.096 54.91 -1.082 62.28 -1.059 74.84 -1.036 82.59 -1.013 95.55 -0.850 100 -0.500 100 0 100

τ ₀₁ in Table 1 is read by the oscilloscope from the half-height of the D-end and CP-end waveforms.

Use an oscilloscope to monitor the Q terminal. When τ ₀₁ enters the [τ _01L , τ _01H ] interval, a metastable bit error occurs.

The bit error curve drawn from the data in Table 1 is shown in Fig. 8, τ _01L = 1.675ns, τ _01H = 1.013ns, and the bit error transition zone is located in the range of 1.675ns ~ 1.013ns.

This embodiment introduces the design idea of the edge trigger metastability observation system, and provides a specific test circuit and a detailed test process. When the delay value between the D terminal and the CP terminal of the flip-flop is within a certain interval within the settling time, the error code output waveform of the Q terminal when the metastable state occurs can be visually seen through the oscilloscope. In the embodiment, the integrated edge trigger 74HC74 is taken as an example, and it presents a monotonic and stable bit error waveform of 0% to 100% in the range of 1.675 ns to 1.013 ns in the settling time, and the test accuracy reaches 0.001 ns.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the implementation method of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (2)

1. An observation method of a metastable state observation system of an edge trigger is characterized in that:

the metastable state observation system of the edge trigger comprises: the device comprises a pulse signal source, a delayer A, a delayer B, a trigger, an NRZ/RZ converter, an error code testing unit and an oscilloscope;

respectively connecting a delay A and a delay B at the D end and the CP end of the trigger, and reading the input delay interval tau of the delay A and the delay B by using an oscilloscope ₀₁ ；

The NRZ/RZ converter is arranged between the Q end of the trigger and the error code testing unit;

using error code test unit to count the pulse up-going edge of Q end and CP end of trigger respectively, then according to the number of pulses

The error rate delta under the condition of the input excitation is obtained by a formula ₀₁ ；

The error code testing unit consists of an NI acquisition card and Labview software,

when LABVIEW programming is carried out, only data collected from an NI acquisition card port are needed to be judged on the rising edge, a shift register is used for continuous counting, and a zero clearing end is compiled;

in a rising edge judgment program of data collected by an NI collection card port, firstly, data of two ports are distinguished by using an index array VI, then rising edge judgment is carried out by respectively using Boolean value conversion (point-by-point) VI, and in the VI, false-true is selected in the direction; the zero clearing end adopts a method of writing data 0 into the shift register when the condition structure is false, so as to achieve the purpose of zero clearing of the data;

the observation method comprises the following steps:

step 1, observing through an oscilloscope to enable the distance | tau between the rising edge of the D end of the trigger and the rising edge of the CP end of the trigger ₀₁ |>|τ _01L |；

Step 2, realizing the pair of | tau ₀₁ L descending scanning in a building time range;

step 3, when | τ ₀₁ |<|τ _01L When I, the error code waveform can be observed at the Q end of the trigger by using an oscilloscope, and tau can be read by the oscilloscope at the moment ₀₁ Value by mistakeCode test cell readout delta ₀₁ A value;

step 4, follow | τ ₀₁ Reduction of |, δ ₀₁ The value will gradually increase monotonically; when | τ ₀₁ |<|τ _01H When is delta ₀₁ The value will reach 100%; continue to decrease | τ ₀₁ Delta if | is 0 ₀₁ The value will always remain at the 100% value.

2. The observation method of the metastable state observation system of the edge flip-flop according to claim 1, wherein: the pulse signal source outputs 0-5V square waves, the duty ratio is 50%, and the frequency is 100Hz; phase shifter R =100 Ω.

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